Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant's election with traverse of Group 1 in the reply filed on 7/07/25 is acknowledged. The traversal is on the ground that claims 1-14 recite the product of Group 1, rather than claims 1-12 as noted in the office action. This is found to be persuasive, in respect to claims 1-14 are related to the product made. Therefore examiner, while examining Group I will examine all of claims 1-14. However, regarding the distinction between product and process of making, this is not found persuasive because applicant fails to argue that the restriction between product and process of making is improper.
The requirement is still deemed proper and is therefore made FINAL, wherein claims 1-14 are related to Group I and claims 15-20 are related to Group II.
Applicant’s election without traverse of Species 1B in the reply filed on 7/07/2026 is acknowledged.
Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over by Kubo et al. (US Pub. 20220328413), hereinafter referred to as Kubo and Lee et al (US. Pub. 20220310515) hereinafter referred to as Lee.
Regarding claim 1, Kubo teaches t three-dimensional memory device comprising: an alternating stack of insulating layers (Kubo, 132, 232, 270 Fig. 70, paras. 122, 154, 156, 318-319) and electrically conductive layers (Kubo, 146, 246, Fig. 70, para. 319),
wherein the electrically conductive layers comprise a first electrically conductive layer (Kubo, 146, Fig. 69C, see diagram below), second electrically conductive layers (Kubo, 146, Fig. 69C, see diagram below) that overlie the first electrically conductive layer, and third (Kubo, 146, Fig. 69C, see diagram below) electrically conductive layers that underlie the first electrically conductive layer; a memory opening vertically extending through the alternating stack (Kubo, 59, Fig. 16D, 69 C, para. 307); a memory opening fill structure located in memory opening and comprising a vertical stack of memory elements (Kubo, 52, 54, 56, Fig. 16D, para. 164) located at levels of the electrically conductive layers and a vertical semiconductor channel (Kubo, 62, Fig. 16D, para. 168); and a layer contact assembly (Kubo, 86, Fig. 69C, para. 212) comprising: a layer contact via structure (Kubo, 86, Fig. 69C, para. 319) vertically extending through each of the second electrically conductive layers and laterally contacting a surface of the first electrically conductive layer; a dielectric support pillar structure (Kubo, 220B, Fig. 69C, para. 316) vertically extending through each of the third electrically conductive layers and contacting a bottom surface of the layer contact via structure; first annular insulating fins (Kub0, 384, Fig. 69C, 384, Fig. 68, para. 311) laterally surrounding the layer contact via structure and located at each level of the second electrically conductive layers; and a second annular insulating fin (Kubo, 332, Fig. 69C, para. 310) having an inner cylindrical sidewall surface that contacts a first cylindrical surface segment of the dielectric support pillar structure.
Kubo teaches the claimed layer contact assembly, including the layer contact via structure (86). However, Kubo’s layer contact via structure (86) is formed directly on a top surface of the electrically conductive layer (Kubo, para. [0319]), rather than laterally contacting a surface of the first electrically conductive layer as claimed.
Lee teaches a 3D memory device having gate contact plugs (289) that include protrusions (289E) protruding in a horizontal direction to contact the gate pads (Lee, Fig. 11A; para. [0202]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the layer contact via structure of Kubo to include the horizontal protrusions taught by Lee. A person of ordinary skill in the art would have been motivated to make this modification to increase the contact area between the contact plug and the conductive layer, thereby reducing contact resistance and improving device reliability, as is standard practice in 3D memory staircase contact design.
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Regarding claim 5, modified Kubo teaches the three-dimensional memory device of Claim 1, wherein the layer contact via structure comprises: a pillar portion (Kubo, 86, Figs 69C, 70) that vertically extends through each of the second electrically conductive layers and the first electrically conductive layer; and a fin portion (Lee 289E, Fig. 11A, para. 202) located at a level of the first electrically conductive layer and adjoined to and laterally protruding from a bottom portion of the pillar portion (In Kubo the pillar portion stops at the first electrically conductive layer and is supported beneath by support pillars 220B) and having an outer sidewall that contacts the cylindrical surface of the first electrically conductive layer (Lee, Fig. 11A).
Regarding claim 13, modified Kubo teaches the three-dimensional memory device of Claim 1, wherein each of the first annular insulating fins (Kubo, 384F, Fig. 68) contacts, or is laterally spaced by a respective backside blocking dielectric layer from, a respective one of the second electrically conductive layers (Kubo, 146, Fig. 68, para. 319) (the fin portions 384F of insulating spacer 384 are in contact with the electrically conductive layers, 146).
Regarding claim 14, modified Kubo teaches the three-dimensional memory device of Claim 1, further comprising an additional dielectric support pillar structure (Kubo, 220A, Fig. 70) having a same material composition as the dielectric support pillar structure (Kubo, para. 291), has a bottom surface located within a horizontal plane including a bottom surface of the dielectric support pillar structure (Kubo, Fig. 70), and has a top surface located within a horizontal plane including a topmost surface of the alternating stack (Kubo, Fig. 70, additional support pillar 220A ends at the same horizontal plane as insulating cap 270, which is considered as part of the alternating stack because it is an insulating layer directly atop a conductive layer and is made up of the same material (silicon oxide, see para. 156) as the insulating layers 132.
Allowable Subject Matter
Claims 2-4, and 6-12 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, modified Kubo teaches the three-dimensional memory device of Claim 1, but does not teach, nor does the prior art of record suggest, wherein the second annular insulating fin is located at a level of a topmost third electrically conductive layer of the third electrically conductive layers.
Regarding claim 6, modified Kubo teaches the three-dimensional memory device of Claim 5, wherein the fin portion comprises: a plate portion (Lee, 289E, Fig. 11A, para. 202).
Modified Kubo does not teach, nor does the prior art of record suggest a first annular rim extending outward from the plate portion and having a top surface within a horizontal plane including a top surface of the plate portion; and a second annular rim extending outward from the plate portion and having a bottom surface within a horizontal plane including a bottom surface of the plate portion.
Claims 3 and 4 are allowed as depending from allowed claim 2.
Claims 7-12 are allowed as depending from allowed claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsuno et al. (US Pub 20220352197) teaches a memory opening fill structure located in memory opening and comprising a vertical stack of memory elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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