DETAILED ACTION
This Office Action is in response to the Election filed on December 1, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 2-13 in the reply filed on December 1, 2025 is acknowledged.
Claims 14-21 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “forming a first memory array associated with a first level above a substrate” and “forming a first memory array associated with a first level above a substrate.” The memory array being “associated” does not convey structure or configuration so its not understood how the memory arrays physical relate to the levels. The claim limitation in question needs to be corrected to show some form of structural relationship or connection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-13 are rejected under 35 U.S.C. 102 (a)1) as being anticipated by Beigel et al. (WO 2019/133744 A1).
In re claim 1, Beigel et al. shows (figs. 1 & 2; pg. 10, line 21 - pg. 11, line 18) a method, comprising: forming a column decoder (206; fig. 2) of a memory die; forming a first memory array (108C; fig.1) associated with a first level (108) above a substrate of the
memory die, the first memory array comprising a first plurality of digit lines each
operable to couple with the column decoder via a respective first transistor (108B) of the
first level ; and forming a second memory array (106C; fig. 1) associated with a second level (106) above the substrate of the memory die, the second memory array comprising a second plurality of digit lines each operable to couple with the column decoder via a respective second transistor (106B) of the second level.
In re claim 3, Beigel et al. shows (figs. 1 & 2; pg. 10, line 21 - pg. 11, line 18)
a plurality of conductors each coupled with one of the first transistors of the first level,
one of the second transistors of the second level, and the column decoder.
In re claims 4-7, Beigel et al. shows (figs. 3) each of the first transistors
comprises a respective channel portion of the first level; and each of the second
transistors comprises a respective channel portion of the second level. The channel
portion of each of the first transistors is operable to form a respective channel that is
aligned along a direction relative to the substrate; and the channel portion of each of the
second transistors is operable to form a respective channel that is aligned along the
direction relative to the substrate. One or more first conductors of the first level each
operable to modulate a conductivity of the channel portion of each of the first
transistors; and one or more second conductors of the second level each operable to
modulate a conductivity of the channel portion of each of the second transistors. The
channel portion of each of the first transistors comprises a respective set of one or more
first semiconductor pillars over the substrate of the memory die in the first level and in
contact with the respective digit line of the first plurality of digit lines; and he channel
portion of each of the second transistors comprises a respective set of one or more
second semiconductor pillars over the substrate of the memory die in the second level
and in contact with the respective digit line of the second plurality of digit lines.
In re claim 8, Beigel et al. shows (figs. 1 & 2; pg. 10, line 21 - pg. 11, line 18)
each memory cell of a first plurality of memory cells of the first memory array is
associated with a respective third transistor of the first level operable to couple the
memory cell with a digit line of the first plurality of digit lines, each of the third transistors
comprising a respective channel portion comprising a respective set of one or more
third semiconductor pillars overlapping, along a height dimension relative to the
substrate, with the first semiconductor pillars; and each memory cell of a second
plurality of memory cells of the second memory array is associated with a respective
fourth transistor of the second level operable to couple the memory cell with a digit line
of the second plurality of digit lines, each of the fourth transistors comprising a
respective channel portion comprising a respective set of one or more fourth
semiconductor pillars overlapping, along the height dimension relative to the substrate,
with the second semiconductor pillars.
In re claim 8, Beigel et al. shows (figs. 1 & 2; pg. 10, line 21 - pg. 11, line 18) a
plurality of third transistors of the first level each operable to couple a respective
memory cell of a first plurality of memory cells of the first memory array with a digit line
of the first plurality of digit lines; and a plurality of fourth transistors of the second level
each operable to couple a respective memory cell of a second plurality of memory cells
of the second memory array with a digit line of the second plurality of digit lines.
In re claims 9-11, Beigel et al. shows (figs. 1 & 2; pg. 10, line 21 - pg. 11, line 18) a plurality of word line conductors each operable to activate a respective row of the
plurality of third transistors and to activate a respective row of the plurality of fourth
transistors. The column decoder is associated with a third level of the memory die, and
the second level is positioned between the first level and the third level. The column
decoder comprises a plurality of transistors, each transistor of the plurality of transistors
comprising a respective channel portion formed at least in part by a doped portion of the
substrate.
In re claims 12, 13, Beigel et al. shows (figs. 1 & 2; pg. 10, line 21 - pg. 11, line
18) the column decoder is operable to couple digit lines of the first plurality of digit lines
or of the second plurality of digit lines with a sense component for accessing memory cells of the first memory array or of the second memory array, wherein the sense
component comprises a plurality of transistors, each transistor of the plurality of
transistors comprising a respective channel portion formed at least in part by a doped
portion of the substrate. each of the first transistors of the first level comprises a
respective first channel portion formed at least in part by a polycrystalline
semiconductor material over the substrate in the first level; and each of the second
transistors of the second level comprises a respective second channel portion formed at
least in part by the polycrystalline semiconductor material over the substrate in the
second level. The substrate comprises a crystalline semiconductor material.
Conclusion
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815