Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 7/7/2026, has been entered.
Claims 1-7 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onodera et al. (US Pub. No. 2022/0320049 A1), hereafter referred to as Onodera.
As to claim 1, Onodera discloses a semiconductor device (figs 1-7 and fig 20, 1A), comprising:
a substrate (fig 9, 10) including a semiconductor element (40) provided on a mounting face of the substrate (surface of 10), the substrate having one side and another side that are opposite to each other in a first direction (X-direction) parallel to the mounting face (fig 7, left side and right side of substrate 10); and
a first main terminal (51A) and a second main terminal (51B) that are located at the one side of the substrate (right side of 10), the first main terminal and the second main terminal facing each other in a second direction (Y-direction) parallel to the mounting face and orthogonal to the first direction (fig 7, 51A and 51B face each other in the second direction),
wherein the first main terminal (51A) includes a first external connection portion (51a) connected to an external conductor (84A), and
a first narrow portion (51b) connecting the first external connection portion (51a) to the substrate (10) in the second direction, the first narrow portion having a width smaller than a width of the first external connection portion (width of 51b is narrower than 51a),
the second main terminal (51B) includes a second external connection portion (51a) connected to an external conductor (84B), and
a second narrow portion (51b) connecting the second external connection portion (51a) to the substrate (10) in the second direction, the second narrow portion having a width smaller than a width of the second external connection portion (width of 51b is narrower than 51a),
in the second direction, a center of the first narrow portion is located closer to the second main terminal than is a center of the first external connection portion (see annotated figure 7 below),
in the second direction, a center of the second narrow portion is located closer to the first main terminal than is a center of the second external connection portion (see annotated fig 7 below), and
an entirety of the first narrow portion is located, in the second direction (y-direction), between two opposite ends of the first external connection portion (see annotated fig 7 below), and an entirety of the second narrow portion is located, in the second direction (y-direction), between two opposite ends of the second external connection portion (see annotated fig 7 below).
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As to claim 2, Onodera discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the first narrow portion (51b) of the first main terminal (51A) is connected to one side of the first main terminal in the second direction at an end thereof that is closer to the second main terminal than is a center thereof (51b of 51A shown closer to 51B then center line shown in annotated figure 7 above), and
the second narrow portion (51b) of the second main terminal (51B is connected to one side of the second main terminal in the second direction at an end thereof that is closer to the first main terminal than is a center thereof (51b of 51B shown closer to 51A then center line shown in annotated figure 7 above).
As to claim 3, Onodera discloses the semiconductor device according to claim 2 (paragraphs above),
wherein a surface of the first main terminal parallel to the first direction and a surface of the second main terminal parallel to the first direction, which face each other, are each flat (surfaces of 51A and 51B facing each other are shown as flat).
As to claim 4, Onodera discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the first main terminal and the second main terminal have a line-symmetric shape with respect to a line in the first direction (fig 7, 51A and 51B; [0071]).
As to claim 5, Onodera discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the width of the first narrow portion in the second direction is equal to or less than half of the width of the first external connection portion in the second direction (fig 7, width of 51b is less than half of the width of 51a for 51A), and
the width of the second narrow portion in the second direction is equal to or less than half of the width of the second external connection portion in the second direction (fig 7, width of 51b is less than half of the width of 51a for 51B).
As to claim 6, Onodera discloses the semiconductor device according to claim 5 (paragraphs above),
wherein the entirety of the first narrow portion is located closer to the second main terminal than is the center of the first external connection portion in the second direction (51b closer to 51B than center line of 51a of 51A shown in annotated figure 7 above), and
the entirety of the second narrow portion is located closer to the first main terminal than is the center of the second external connection portion in the second direction (51b closer to 51A than center line of 51a of 51B shown in annotated figure 7 above).
As to claim 7, Onodera discloses the semiconductor device according to claim 1 (paragraphs above),
a third main terminal (52A) located on the other side of the substrate (10) opposite in the first direction to the one side of the substrate where the first main terminal (51A) and the second main terminal (51B) are disposed,
wherein the third main terminal (52A) includes a third external connection portion (52a) connected to an external conductor (85A) and a third narrow portion (52b) connected to the third external connection portion (52a) and to the substrate (10), the third narrow portion (52b) having a width in the second direction smaller than a width of the third external connection portion (52a), and
a position of the third narrow portion (52b) in the second direction overlaps in the first direction a position of a gap between the first main terminal (51A) and the second main terminal (51B) in the second direction (see annotated figure 7 below).
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Response to Arguments
Applicant's arguments filed 7/7/2026 have been fully considered but they are not persuasive.
Applicant argued that Onodera does not disclose the amended claim limitation. Specifically, that the end portion of connection portion 51b protrudes beyond the corresponding end of exposed portion 51a in the Y-direction.
Examiner agrees that the entirety of the narrow portion 51b pointed to in the last office action is not between the two opposite ends of the external connection portion. However, as newly presented in this office action, the entirety of the narrow portion now pointed to in the annotated figure 7 and figure 20 is located between the two opposite ends of the external connection portion, while also meeting the limitations with respect to the center of the narrow portions relative to the center of the external connection portions.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2024/0421132A1; US Pub. No. 2023/0369183 A1; US Pub. No. 2021/0407875A1; and US Pub. No. 2021/0305147A1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 8/16/2026
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