DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/07/2024 have been entered and considered. Initialed copies of the PTO-1449 by the Examiner are attached.
Specification
The abstract of the disclosure is objected to because there is a full stop in line 4 (which is not at the end of a sentence) of the abstract. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract without significantly more.
Independent Claim 1
Step 1 Analysis: Claim 1 is directed to a processor, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 1, in part recites “identify one or more pixels within a polygon based, at least in part, on whether the one or more pixels are adjacent to one or more pixels that cross one or more polygon boundaries”. The “identify” step of the claim encompass determining the locations of pixels and their relation to each other by performing calculations. Such “calculation” or evaluations fall within the “mathematical calculations” grouping of abstract ideas.
Step 2A Prong 2 Analysis: The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application. In particular, the claim in part recites the additional elements –
one or more circuits
The “one or more circuits” are recited at a high level of generality and amounts to circuits used to apply the exception and are parts of a generic computer.
Step 2B Analysis: The claim does not include additional elements that are
sufficient to amount to significantly more than the judicial exception. For the reasons
given in Step 2A Prong 2. Thus, the claim is not patent eligible.
Accordingly, the dependent claims 2-7 do not provide elements that overcome the deficiencies of the independent claim 1.
Dependent claims 2-7
Claim 2 recites in part “wherein the one or more circuits are to identify an amount of one or more pixels within the polygon based, at least in part, on an amount of one or more edges of the one or more pixels covered by one or more edges of the polygon“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 3 recites in part “wherein the one or more circuits are to use one or more prefix sums along one or more dimensions to identify an amount of one or more pixels within the polygon” do not overcome the rejection of the parent claim 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 4 recites in part “w wherein the one or more circuits are to use one or more prefix sums along one or more dimensions to identify an amount of one or more pixels within the polygon “ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 5 recites in part “wherein the one or more circuits are to use the identified one or more pixels to, at least in part, perform computational lithography tasks“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 6 recites in part “wherein the one or more circuits are to identify one or more portions of one or more edges of the polygon based, at least in part, on one or more intersections between the one or more edges and one or more pixels adjacent to the one or more pixels. “ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 7 recites in part “wherein the one or more circuits are to identify an amount of one or more pixels within a polygon based, at least in part, on one or more portions of one or more edges of the polygon “ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Independent Claim 8
Step 1 Analysis: Claim 8 is directed to a system, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 8, in part recites “identify one or more pixels within a polygon based, at least in part, on whether the one or more pixels are adjacent to one or more pixels that cross one or more polygon boundaries”. The “identify” step of the claim encompass determining the locations of pixels and their relation to each other by performing calculations. Such “calculations” or evaluations fall within the “mathematical calculations” grouping of abstract ideas.
Step 2A Prong 2 Analysis: The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application. In particular, the claim in part recites the additional elements –
processor
The “processor” is recited at a high level of generality and amounts to no more than a processor used to apply the exception and are parts of a generic computer.
Step 2B Analysis: The claim does not include additional elements that are
sufficient to amount to significantly more than the judicial exception. For the reasons
given in Step 2A Prong 2. Thus, the claim is not patent eligible.
Dependent claims 9-14
Claim 9 recites in part “wherein the one or more processors are to identify an amount of one or more pixels within the polygon based, at least in part, on a fraction of one or more edges of the one or more pixels covered by one or more edges of the polygon “ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 10 recites in part “wherein the one or more processors are to use one or more prefix sums along one or more rows of one or more pixels to identify an amount of one or more pixels within the polygon“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 11 recites in part “wherein the one or more processors are to parallelize computations of an amount of one or more edges of one or more pixels covered by the polygon over two or more edges of the polygon “ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 12 recites in part “wherein the one or more processors are to identify the one or more pixels within a polygon to be used with computational lithography “ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 13 recites in part “wherein the one or more processors are to identify one or more portions of one or more edges of the polygon based, at least in part, on one or more locations where two or more edges of the polygon meet“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 14 recites in part “wherein the one or more processors are to identify an amount of one or more pixels within a polygon by using one or more width values based, at least in part, on one or more portions of one or more edges of the polygon“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Independent Claim 15
Step 1 Analysis: Claim 15 is directed to a method, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 15, in part recites “identify one or more pixels within a polygon based, at least in part, on whether the one or more pixels are adjacent to one or more pixels that cross one or more polygon boundaries”. The “identify” step of the claim encompass determining the locations of pixels and their relation to each other by performing calculations. Such “calculations” or evaluations fall within the “mathematical calculations” grouping of abstract ideas.
Step 2A Prong 2 Analysis: The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application.
Step 2B Analysis: The claim does not include additional elements that are
sufficient to amount to significantly more than the judicial exception. For the reasons
given in Step 2A Prong 2. Thus, the claim is not patent eligible.
Dependent claims 16-20
Claim 16 recites in part “identifying an amount of one or more pixels within the polygon based, at least in part, on a projection of one or more portions of one or more edges of the polygon onto an edge of one or more adjacent pixels“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 17 recites in part “using one or more prefix sums of amounts of one or more edges of the one or more pixels covered by one or more edges of the polygon “ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 18 recites in part “parallelizing computations of one or more amounts of one or more pixels within the polygon over two or more portions of one or more edges of the polygon“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 19 recites in part “identifying the one or more pixels within a polygon to be used with rasterization“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim 20 recites in part “identifying one or more portions of one or more edges of the polygon that traverse one or more pixels“ do not overcome the rejection of the parent claims 1 as stated above because the additional elements does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-10, 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (Pub No.: US20160314556A1) in view of Bhattacharyya et al (Pub No.: US20210150788A1) in view of Tuomi et al (US20030095134A1).
Regarding independent claim 1, Yang teaches a processor (CPU, 1202 – see Fig 12 and the processing logic 112 may be implemented by executing software on a processor wherein the software is written such that when it is executed it causes the processor to perform the operations of the tiling unit 108 – see [p][0036]) comprising: one or more circuits to identify one or more pixels within a polygon based ([t]he results of the tiling tests (including the per-edge results, which as described above are for use in inferring whether tiles do not include the primitive) for the subset of tiles can then be analysed (in step S422) to determine whether there are 3×3 blocks of tiles which have tiles from the subset of tiles in the corners, wherein those tiles of the subset have the same tiling test results. If this is the case then the remaining five tiles in the 3×3 block can be assigned the same results as the relevant tiles of the subset (in step S424), without performing specific tiling calculations for those five tiles. For example, the 3×3 block of tiles shown in FIG. 9 in the top left corner of the bounding box (i.e. the first three tiles in the first three rows of the bounding box) includes tiles of the subset (tiles T1,1, T1,3, T3,1 and T3,3) in the four corners for which the tiling test results indicate that the primitive 904 is outside those tiles and in particular, that the primitive 904 is outside those tiles because the tiles are all outside the same edge of the primitive 904 (e.g. outside the left edge of the primitive 904 as shown in FIG. 9) – see [p][0066]). Yang does not explicitly disclose at least in part, on whether the one or more pixels are adjacent to one or more pixels.
Bhattacharyya explicitly teaches at least in part, on whether the one or more pixels are adjacent to one or more pixels (edge pixels include pixels that are directly adjacent to pixels outside of an object. In the example discussed above, the next pixel is pixel 1, which is identified as an edge pixel – see [p][0154]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Bhattacharyya at least in part, on whether the one or more pixels are adjacent to one or more pixels.
Wherein having Yang at least in part, on whether the one or more pixels are adjacent to one or more pixels.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while convert media into a vector format, since both Yang and Bhattacharyya relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bhattacharyya convert media into vector format by determining a plurality of gradient intensity values corresponding to a plurality of pixels in a frame of the at least one scene (Please see Yang (US20210150788A1), Abstract, and Bhattacharyya (US20210150788A1), [p][0004]).
Yang in view of Bhattacharyya does not explicitly teach that cross one or more polygon boundaries.
Tuomi explicitly teaches that cross one or more polygon boundaries ([o]f these pixels 410, three are completely within the triangle and seven pixels are only partially within the triangle 404 with the associated TLC contained fully within the triangle 404. Therefore, these seven edge pixels 410 having the associated TLC contained fully within the triangle 404 will be set to the color of the triangle 404, a conventional rasterization process – see [p][0055]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Tuomi a that cross one or more polygon boundaries.
Wherein having Yang that cross one or more polygon boundaries.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while performing anti-aliasing on pixels proximate the edge of a polygon, since both Yang and Tuomi relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Tuomi for performing anti-aliasing on pixels proximate the edge of a polygon (Please see Yang (US20160314556A1), Abstract, and Tuomi et al (US20030095134A1), [p][0004]).
Regarding claim 2, Yang in view of Bhattacharyya further in view of Tuomi teach the processor of claim 1, Yang in view of Tuomi fail to explicitly teach wherein the one or more circuits are to identify an amount of one or more pixels within the polygon based, at least in part, on an amount of one or more edges of the one or more pixels covered by one or more edges of the polygon.
However, Bhattacharyya explicitly teaches wherein the one or more circuits are to identify an amount of one or more pixels within the polygon based, at least in part, on an amount of one or more edges of the one or more pixels covered by one or more edges of the polygon ([a]t act 308, a gradient intensity of the frame is determined. For example, an edge detection operator may be executed to determine values indicative of gradients in a horizontal and vertical dimension of the frame. The values indicative of the gradients in the horizontal and vertical dimensions of the frame may be utilized to identify objects' edges throughout the frame – see [p][0110] and [a]t act 906, object corner pixels are identified from the edge pixels. Corner pixels may include each pixel for which a line connecting the respective pixel to a first adjacent edge pixel is not parallel to a second adjacent edge pixel. For example, in FIG. 10, pixel 1 is a corner pixel because a line connecting pixel 1 to pixel 2 is horizontal, whereas a line connecting pixel 1 to pixel 28 is vertical – see [p][0143]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya further in view of Tuomi of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Bhattacharyya wherein the one or more circuits are to identify an amount of one or more pixels within the polygon based, at least in part, on an amount of one or more edges of the one or more pixels covered by one or more edges of the polygon.
Wherein having Yang wherein, the one or more circuits are to identify an amount of one or more pixels within the polygon based, at least in part, on an amount of one or more edges of the one or more pixels covered by one or more edges of the polygon.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while convert media into a vector format, since both Yang and Bhattacharyya relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bhattacharyya convert media into vector format by determining a plurality of gradient intensity values corresponding to a plurality of pixels in a frame of the at least one scene (Please see Yang (US20210150788A1), Abstract, and Bhattacharyya (US20210150788A1), [p][0004]).
Regarding claim 3, Yang in view of Bhattacharyya further in view of Tuomi teach the processor of claim 1, Yang in view of Tuomi fail to explicitly teach wherein the one or more circuits are to use one or more prefix sums along one or more dimensions to identify an amount of one or more pixels within the polygon.
Bhattacharyya explicitly teaches wherein the one or more circuits are to use one or more prefix sums along one or more dimensions to identify an amount of one or more pixels within the polygon ([k]ey point matching may include determining one or more differences between a subject key point in a first frame and each key point in a second, successive frame to determine whether the key point corresponds to any key point in the second frame. The one or more differences may include determining a difference in Euclidean space, determining a difference in neighborhood curvature (that is, curvature of a contour around the key point), and a difference in orientation of the neighborhood curvature's angle (for example, with respect to an axis, such as the x-axis), each difference being between the subject key point and each key point in the second frame. The three differences may be individually squared and summed to determine a sum-of-squares error for the subject key point and each key point in the second frame. In some examples, certain differences may be given higher or lower weights than other differences. A key point in the second frame having a lowest sum-of-squares error with the subject key point may be determined to be the same key point. In some examples, the sum-of-squares error may be required to be below a certain threshold error. If the lowest error is still not below the threshold error, then it may be determined that the subject key point is not present in the second frame – see [p][0302]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya further in view of Tuomi of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Bhattacharyya wherein the one or more circuits are to use one or more prefix sums along one or more dimensions to identify an amount of one or more pixels within the polygon.
Wherein having Yang wherein the one or more circuits are to use one or more prefix sums along one or more dimensions to identify an amount of one or more pixels within the polygon.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while convert media into a vector format, since both Yang and Bhattacharyya relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bhattacharyya convert media into vector format by determining a plurality of gradient intensity values corresponding to a plurality of pixels in a frame of the at least one scene (Please see Yang (US20160314556A1), Abstract, and Bhattacharyya (US20210150788A1), [p][0004]).
Regarding claim 6, Yang in view of Bhattacharyya further in view of Tuomi teach the processor of claim 1, Yang explicitly teaches wherein the one or more circuits are to identify one or more portions of one or more edges of the polygon based, at least in part, on one or more intersections between the one or more edges and one or more pixels adjacent to the one or more pixels (tiling unit 108 determines intersection points of the tile boundary with edges of the primitive, and uses the determined intersection points to determine which of the tiles in the bounding box the primitive is in – see [p][0076]).
Regarding claim 7, Yang in view of Bhattacharyya further in view of Tuomi teach the processor of claim 1, Yang explicitly teaches wherein the one or more circuits are to identify an amount of one or more pixels within a polygon based, at least in part, on one or more portions of one or more edges of the polygon (the at least one other tile is located within a region bounded by the two or more of the tiles of the subset. If a particular tile is surrounded by tiles from the subset which all have the same tiling test results then it can be inferred that the particular tile will also have the same results – see [p][0056]).
Regarding independent claim 8, Yang discloses a system (CPU, 1202 – see Fig 12 and the processing logic 112 may be implemented by executing software on a processor wherein the software is written such that when it is executed it causes the processor to perform the operations of the tiling unit 108 – see [p][0036]) comprising: one or more processors (CPU, 1202 – see Fig 12) to identify one or more pixels within a polygon based ([t]he results of the tiling tests (including the per-edge results, which as described above are for use in inferring whether tiles do not include the primitive) for the subset of tiles can then be analysed (in step S422) to determine whether there are 3×3 blocks of tiles which have tiles from the subset of tiles in the corners, wherein those tiles of the subset have the same tiling test results. If this is the case then the remaining five tiles in the 3×3 block can be assigned the same results as the relevant tiles of the subset (in step S424), without performing specific tiling calculations for those five tiles. For example, the 3×3 block of tiles shown in FIG. 9 in the top left corner of the bounding box (i.e. the first three tiles in the first three rows of the bounding box) includes tiles of the subset (tiles T1,1, T1,3, T3,1 and T3,3) in the four corners for which the tiling test results indicate that the primitive 904 is outside those tiles and in particular, that the primitive 904 is outside those tiles because the tiles are all outside the same edge of the primitive 904 (e.g. outside the left edge of the primitive 904 as shown in FIG. 9) – see [p][0066]). Yang does not explicitly disclose at least in part, on whether the one or more pixels are adjacent to one or more pixels.
Bhattacharyya explicitly teaches at least in part, on whether the one or more pixels are adjacent to one or more pixels (edge pixels include pixels that are directly adjacent to pixels outside of an object. In the example discussed above, the next pixel is pixel 1, which is identified as an edge pixel – see [p][0154]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Bhattacharyya at least in part, on whether the one or more pixels are adjacent to one or more pixels.
Wherein having Yang at least in part, on whether the one or more pixels are adjacent to one or more pixels.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while convert media into a vector format, since both Yang and Bhattacharyya relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bhattacharyya convert media into vector format by determining a plurality of gradient intensity values corresponding to a plurality of pixels in a frame of the at least one scene (Please see Yang (US20210150788A1), Abstract, and Bhattacharyya (US20210150788A1), [p][0004]).
Yang in view of Bhattacharyya does not explicitly teach pixels that cross one or more polygon boundaries.
Tuomi explicitly teach pixels that cross one or more polygon boundaries ([o]f these pixels 410, three are completely within the triangle and seven pixels are only partially within the triangle 404 with the associated TLC contained fully within the triangle 404. Therefore, these seven edge pixels 410 having the associated TLC contained fully within the triangle 404 will be set to the color of the triangle 404, a conventional rasterization process – see [p][0055]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Tuomi pixels that cross one or more polygon boundaries.
Wherein having Yang pixels that cross one or more polygon boundaries.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while performing anti-aliasing on pixels proximate the edge of a polygon, since both Yang and Tuomi relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bhattacharyya for performing anti-aliasing on pixels proximate the edge of a polygon (Please see Yang (US20160314556A1), Abstract, and Tuomi et al (US20030095134A1), [p][0004]).
Regarding claim 10, which corresponds to claim 3 except for reciting a different statutory category of a system. Therefore, the rejection analysis of claim 3 are fully applicable to claim 10.
Regarding claim 13, Yang in view of Bhattacharyya further in view of Tuomi teach the system of claim 8, Yang explicitly teaches wherein the one or more processors are to identify one or more portions of one or more edges of the polygon based, at least in part, on one or more locations where two or more edges of the polygon meet (see Fig 2 – show a triangle with edges that meet).
Regarding independent claim 15, Yang discloses a method (processing logic 112 may be implemented by executing software on a processor wherein the software is written such that when it is executed it causes the processor to perform the operations of the tiling unit 108 – see [p][0036]) comprising: identify one or more pixels within a polygon based ([t]he results of the tiling tests (including the per-edge results, which as described above are for use in inferring whether tiles do not include the primitive) for the subset of tiles can then be analysed (in step S422) to determine whether there are 3×3 blocks of tiles which have tiles from the subset of tiles in the corners, wherein those tiles of the subset have the same tiling test results. If this is the case then the remaining five tiles in the 3×3 block can be assigned the same results as the relevant tiles of the subset (in step S424), without performing specific tiling calculations for those five tiles. For example, the 3×3 block of tiles shown in FIG. 9 in the top left corner of the bounding box (i.e. the first three tiles in the first three rows of the bounding box) includes tiles of the subset (tiles T1,1, T1,3, T3,1 and T3,3) in the four corners for which the tiling test results indicate that the primitive 904 is outside those tiles and in particular, that the primitive 904 is outside those tiles because the tiles are all outside the same edge of the primitive 904 (e.g. outside the left edge of the primitive 904 as shown in FIG. 9) – see [p][0066]). Yang does not explicitly disclose at least in part, on whether the one or more pixels are adjacent to one or more pixels.
Bhattacharyya explicitly teaches at least in part, on whether the one or more pixels are adjacent to one or more pixels (edge pixels include pixels that are directly adjacent to pixels outside of an object. In the example discussed above, the next pixel is pixel 1, which is identified as an edge pixel – see [p][0154]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya further in view of Tuom of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Bhattacharyya at least in part, on whether the one or more pixels are adjacent to one or more pixels.
Wherein having Yang at least in part, on whether the one or more pixels are adjacent to one or more pixels.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while convert media into a vector format, since both Yang and Bhattacharyya relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bhattacharyya convert media into vector format by determining a plurality of gradient intensity values corresponding to a plurality of pixels in a frame of the at least one scene (Please see Yang (US20160314556A1), Abstract, and Bhattacharyya (US20210150788A1), [p][0004]).
Yang in view of Bhattacharyya does not explicitly teach pixels that cross one or more polygon boundaries.
Tuomi explicitly teach pixels that cross one or more polygon boundaries ([o]f these pixels 410, three are completely within the triangle and seven pixels are only partially within the triangle 404 with the associated TLC contained fully within the triangle 404. Therefore, these seven edge pixels 410 having the associated TLC contained fully within the triangle 404 will be set to the color of the triangle 404, a conventional rasterization process – see [p][0055]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Tuomi pixels that cross one or more polygon boundaries.
Wherein having Yang pixels that cross one or more polygon boundaries.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while performing anti-aliasing on pixels proximate the edge of a polygon, since both Yang and Tuomi relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Tuomi for performing anti-aliasing on pixels proximate the edge of a polygon (Please see Yang (US20210150788A1), Abstract, and Tuomi et al (US20030095134A1), [p][0004]).
Regarding claim 16, Yang in view of Bhattacharyya further in view of Tuomi teach the method of claim 15, Yang explicitly teaches further comprising identifying an amount of one or more pixels within the polygon based, at least in part, on a projection of one or more portions of one or more edges of the polygon onto an edge of one or more adjacent pixels (pre-processing module 106 may also project the primitives into screen-space and a primitive may be completely in one tile or may overlap two or more of the tiles of the rendering space whereby the bounding box may be increased in size such that the edges of the bounding box fall on tile boundaries – see [p][0004-0006]).
Regarding claim 17, Yang in view of Bhattacharyya further in view of Tuomi teach the method of claim 15, Yang in view of Tuomi fail to explicitly teach further comprising using one or more prefix sums of amounts of one or more edges of the one or more pixels covered by one or more edges of the polygon.
Bhattacharyya explicitly teaches further comprising using one or more prefix sums of amounts of one or more edges of the one or more pixels covered by one or more edges of the polygon ([k]ey point matching may include determining one or more differences between a subject key point in a first frame and each key point in a second, successive frame to determine whether the key point corresponds to any key point in the second frame. The one or more differences may include determining a difference in Euclidean space, determining a difference in neighborhood curvature (that is, curvature of a contour around the key point), and a difference in orientation of the neighborhood curvature's angle (for example, with respect to an axis, such as the x-axis), each difference being between the subject key point and each key point in the second frame. The three differences may be individually squared and summed to determine a sum-of-squares error for the subject key point and each key point in the second frame. In some examples, certain differences may be given higher or lower weights than other differences. A key point in the second frame having a lowest sum-of-squares error with the subject key point may be determined to be the same key point. In some examples, the sum-of-squares error may be required to be below a certain threshold error. If the lowest error is still not below the threshold error, then it may be determined that the subject key point is not present in the second frame – see [p][0302]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya further in view of Tuomi of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Bhattacharyya further comprising using one or more prefix sums of amounts of one or more edges of the one or more pixels covered by one or more edges of the polygon.
Wherein having Yang further comprising using one or more prefix sums of amounts of one or more edges of the one or more pixels covered by one or more edges of the polygon.
The motivation behind the modification would have been to reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system for rendering a primitive while convert media into a vector format, since both Yang and Bhattacharyya relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bhattacharyya convert media into vector format by determining a plurality of gradient intensity values corresponding to a plurality of pixels in a frame of the at least one scene (Please see Yang (US20160314556A1), Abstract, and Bhattacharyya (US20210150788A1), [p][0004]).
Regarding claim 19, Yang in view of Bhattacharyya further in view of Tuomi teach the method of claim 15, Yang explicitly teaches further comprising identifying the one or more pixels within a polygon to be used with rasterization (a method of processing a primitive in a graphics processing system, the method comprising tiling the primitive to determine which of a plurality of tiles of a rendering space the primitive is in, said tiling the primitive comprising: for each tile of a subset of the tiles, performing a tiling test to determine whether the primitive is in the tile; and using results of the tiling tests for two or more of the tiles of the subset to determine whether the primitive is in at least one other tile which is located within a region bounded by said two or more of the tiles of the subset. – see [p][0011]).
Regarding claim 20, Yang in view of Bhattacharyya further in view of Tuomi teach the method of claim 15, Yang explicitly teaches further comprising identifying one or more portions of one or more edges of the polygon that traverse one or more pixels (see Fig 2)
Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (Pub No.: US20160314556A1) in view of Bhattacharyya et al (Pub No.: US20210150788A1) in view of Tuomi et al (US20030095134A1) as applied claim 1 further in view of Bruce (Pub No.: US20210256298A1).
Regarding claim 4, Yang, Bhattacharyya and Tuomi teach the processor of claim 1, Yang teaches wherein the one or more circuits are to parallelize computations of an amount of one or more pixels (render an image of a 3D scene, the graphics data describing the primitives can be sent to the GPU 102 (a specialized electronic circuit designed for rapid parallel processing), and the GPU 102 can render the scene – see [p][0094]). Yang in view of Bhattacharyya further in view of Tuomi does not explicitly teach covered by the polygon over two or more edges of the polygon.
Bruce explicitly teaches covered by the polygon over two or more edges of the polygon (for e.g. element 084 shows that the polygon covers or crosses two or more boundaries – see Fig 4B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya further in view of Tuomi of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Bruce covered by the polygon over two or more edges of the polygon.
Wherein having Yang covered by the polygon over two or more edges of the polygon
The motivation behind the modification would have been for generating an indication of one or more characteristics of the input image based on at least the first cluster, and outputting the indication system for rendering a primitive while convert media into a vector format, since both Yang and Bruce relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bruce for generating an indication of one or more characteristics of the input image based on at least the first cluster, and outputting the indication (Please see Yang (US20160314556A1), Abstract, and Bruce (US20210256298A1), [p][0005]).
Regarding claim 11, which corresponds to claim 4 except for reciting a different statutory category of a system. Therefore, the rejection analysis of claim 4 are fully applicable to claim 11.
Regarding claim 18, which corresponds to claim 4 except for reciting a different statutory category of a method. Therefore, the rejection analysis of claim 4 are fully applicable to claim 18.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (Pub No.: US20160314556A1) in view of Bhattacharyya et al (Pub No.: US20210150788A1) in view of Tuomi et al (US20030095134A1) as applied claim 1 further in view of Tsai (Pub No.: US20130311960A1).
Regarding claim 5, Yang, Bhattacharyya and Tuomi teach the processor of claim 1, Yang teaches wherein the one or more circuits are to use the identified one or more pixels to (identified as being on the edge of the primitive 1102 – see [p][0079]).
Yang does not explicitly teach at least in part, perform computational lithography tasks (detailed full-chip computational lithography process modeling – see [p][0006]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Tsai at least in part, perform computational lithography tasks.
Wherein having Tsai at least in part, perform computational lithography tasks.
The motivation behind the modification would have been for resolution enhancement by performing model-based sub-resolution assist feature generation and manipulation while convert media into a vector format, since both Yang and Tsai relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bruce for resolution enhancement by performing model-based sub-resolution assist feature generation and manipulation (Please see Yang (US20210150788A1), Abstract, and Tsai (US20130311960A1), [p][0002]).
Regarding claim 12, which corresponds to claim 5 except for reciting a different statutory category of a system. Therefore, the rejection analysis of claim 5 are fully applicable to claim 12.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (Pub No.: US20160314556A1) in view of Bhattacharyya et al (Pub No.: US20210150788A1) in view of Tuomi et al (US20030095134A1) as applied claim 1 further in view of Dorbie et al (Pub No.: US 20080122866A1).
Regarding claim 9, Yang in view of Bhattacharyya further in view of Tuomi does not explicitly teach wherein the one or more processors are to identify an amount of one or more pixels within the polygon based, at least in part, on a fraction of one or more edges of the one or more pixels covered by one or more edges of the polygon
Dorbie explicitly teaches wherein the one or more processors are to identify an amount of one or more pixels within the polygon based, at least in part, on a fraction of one or more edges of the one or more pixels covered by one or more edges of the polygon (the coverage data includes fractional coverage data that indicates the fraction of each mask pixel that is covered by the shape and primitives are employed to approximate different surfaces, points, or edge in an image. – see [p][0018][0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya further in view of Tuomi of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Dorbie wherein the one or more processors are to identify an amount of one or more pixels within the polygon based, at least in part, on a fraction of one or more edges of the one or more pixels covered by one or more edges of the polygon
Wherein having Yang wherein the one or more processors are to identify an amount of one or more pixels within the polygon based, at least in part, on a fraction of one or more edges of the one or more pixels covered by one or more edges of the polygon.
The motivation behind the modification would have been for increasing the efficiency of the graphics system, and outputting the indication system for rendering a primitive while convert media into a vector format, since both Yang and Dorbie relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Bruce uses the coverage data both in screening primitive pixels and also in anti-aliasing can further increase the efficiency of the graphics system (Please see Yang (US20160314556A1), Abstract, and Dorbie (Pub No.: 20080122866A1), [p][0018]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (Pub No.: US20160314556A1) in view of Bhattacharyya et al (Pub No.: US20210150788A1) in view of Tuomi et al (US20030095134A1) as applied claim 1 further in view of Vaswaniet al (US Patent No.: 6252606).
Regarding claim 14, Yang in view of Bhattacharyya further in view of Tuomi does not explicitly teach wherein the one or more processors are to identify an amount of one or more pixels within a polygon by using one or more width values based, at least in part, on one or more portions of one or more edges of the polygon.
Vaswani explicitly teaches wherein the one or more processors are to identify an amount of one or more pixels within a polygon by using one or more width values based, at least in part, on one or more portions of one or more edges of the polygon ([f]or each consecutive scan line, the graphics processor then uses the width values of the polygon to draw each horizontal row of polygon pixels into the frame buffer. Such an algorithm is known as the Incremental Line-Drawing algorithm, or Digital Differential Analyzer (DDA) -see col 1, lines 54-56).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Yang in view of Bhattacharyya further in view of Tuomi of a processor comprising: one or more circuits to identify one or more pixels within a polygon, with the teachings of Vaswani wherein the one or more processors are to identify an amount of one or more pixels within a polygon by using one or more width values based, at least in part, on one or more portions of one or more edges of the polygon.
Wherein having Yang wherein the one or more processors are to identify an amount of one or more pixels within a polygon by using one or more width values based, at least in part, on one or more portions of one or more edges of the polygon.
The motivation behind the modification would have been for i adjusting the initial and incremental gradient parameters for each pixel characteristic and outputting the indication system for rendering a primitive while convert media into a vector format, since both Yang and Vaswani relate to processing graphics images, wherein Yang determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset without performing tiling calculations for all of the tiles in the bounding box for a primitive thus reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive while Vaswani utilizing an error correction circuit for adjusting the initial and incremental gradient parameters for each pixel characteristic and then rendering each scan line with the proper orthogonal adjustment. (Please see Yang (US20160314556A1), Abstract, and Vaswani (US Patent No: 6252606), see Abstract).
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
14 Claims 1-2, 6, 8, 10, 15 and 17 are provisionally rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claim 1-2, 6, 8 10, 15 and 17 of copending Application No. 18/415464. The conflicting claims are not identical because copending application claim 1 recites “one or more prefix sums that operate on one or more values”. However, the conflicting claims are not patentably distinct from each other because:
· Claims 1 and copending claim 1 recite common subject matter;
· Whereby claim 1, which recites the open ended transitional phrase “comprising”, does not preclude the method as being performed by an apparatus, and
· Whereby the elements of claim 1 are fully anticipated by copending application claim 1, and anticipation is “the ultimate or epitome of obviousness” (In re Kalm, 154 USPQ 10 (CCPA 1967), also In re Dailey, 178 USPQ 293 (CCPA 1973) and In re Pearson, 181 USPQ 641 (CCPA 1974)).
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
This Application No.: 18589214
Copending Application 18/415464
1 A processor comprising: one or more circuits to identify one or more pixels within a polygon based, at least in part, on whether the one or more pixels are adjacent to one or more pixels that cross one or more polygon boundaries.
1. One or more processors, comprising: circuitry to identify one or more pixels within one or more polygons based, at least in part, on one or more prefix sums that operate on one or more values assigned to one or more portions of one or more pixels adjacent to the one or more pixels.
2. The processor of claim 1, wherein the one or more circuits are to identify an amount of one or more pixels within the polygon based, at least in part, on an amount of one or more edges of the one or more pixels covered by one or more edges of the polygon.
6 The one or more processors of claim 1 wherein the circuitry is to identify the one or more pixels within the one or more polygons by at least identifying portions of the one or more pixels within the one or more polygons.
6. The processor of claim 1, wherein the one or more circuits are to identify one or more portions of one or more edges of the polygon based, at least in part, on one or more intersections between the one or more edges and one or more pixels adjacent to the one or more pixels.
2. The one or more processors of claim 1 wherein the one or more values assigned to the one or more portions comprise one or more gradients assigned to one or more corners of the one or more adjacent pixel
8. A system, comprising: one or more processors to identify one or more pixels within a polygon based, at least in part, on whether the one or more pixels are adjacent to one or more pixels that cross one or more polygon boundaries.
8. (Currently Amended) A system, comprising: one or more processors to identify one or more pixels within one or more polygons based, at least in part, on one or more prefix sums that operate on one or more values assigned to one or more portions of one or more pixels adjacent to the one or more pixels
10. The system of claim 8, wherein the one or more processors are to use one or more prefix sums along one or more rows of one or more pixels to identify an amount of one or more pixels within the polygon.
10. (Currently Amended) The system of claim 8, wherein the one or more prefix sums comprise one or more inclusive prefix sums that use information indicating whether the one or more adjacent pixels in a column are partially outside the one or more polygons.
15. A method, comprising: identifying one or more pixels within a polygon based, at least in part, on whether the one or more pixels are adjacent to one or more pixels that cross one or more polygon boundaries.
15. (Currently Amended) A method, comprising: identifying one or more pixels within one or more polygons based, at least in part, on one or more prefix sums that operate on one or more values assigned to one or more portions of one or more pixels adjacent to the one or more pixels
17. The method of claim 15, further comprising using one or more prefix sums of amounts of one or more edges of the one or more pixels covered by one or more edges of the polygon.
17. The method of claim 15, wherein the one or more prefix sums use, as inputs, gradients of corners of the one or more adjacent pixels.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Barone et al (Pub No.: 20090046098 ) discloses a primitive binning method includes detecting border tiles of a primitive defined by at least three vertexes. The detecting includes: defining a left edge and a right edge of the primitive compared to a direction of exploring tiles; calculating a slope sign for the left edge using an edge equation for the left edge; calculating a slope sign for the right edge using an edge equation for the right edge; and checking if a tile is crossed by one of the edges by evaluating an edge equation of a single corner of a tile. The corner is selected according to the one of the edges being a left or a right edge and according to the slope sign of the one of the edges.
Barone et al (Pub No.: 20090147016 ) discloses a method detects border tiles or border pixels of a primitive corresponding to an object to be displayed on a display screen. The detecting includes: calculating the number of border tiles or pixels covered by an edge of the primitive; identifying a plurality of vertices that divide the edge in a plurality of segments of equal length; calculating coordinates of the vertices; and associating a tile or pixel with the coordinates of each vertex. The number of vertices for the edge is greater than or equal to the number of border tiles or pixels.
STEPUCH (Pub No.: 20240005444 ) discloses a computer-implemented method of defining bounding boxes for a primitive in a tile-based graphics processing pipeline comprising determining a part-way point on the primitive, wherein, for each pair of vertices, a part-way point is part-way between that pair of vertices, and defining a plurality of bounding boxes, wherein each bounding box intersects a part-way point. Also provided is a bounding box generation circuit comprising a part-way point calculation circuit to determine a part-way point on the primitive, wherein, for each pair of vertices, a part-way point is part-way between that pair of vertices, wherein the bounding box generation circuit to define a plurality of bounding boxes based upon the determined part-way point, wherein each bounding box intersects a part-way point. A method of defining bounding boxes for a point primitive is also provided.
Drill et al (Pub No.: 20120044245 ) discloses a primitive rasterizing method that involves scanning a first row (18a) of tiles (12), one tile at a time, starting from a first point and scanning in a first direction (1). A tile comprises a block of pixels. Immediately after scanning, the first row of tiles is moved from the first point to a second point in an orthogonal direction relative to the first row. Immediately after moving from the first point to the second point, a second row (18b) of tiles (30) is scanned, one tile at a time, starting from the second point and scanning in the first direction.
Inquiries
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/ANDRAE S ALLISON/Primary Examiner, Art Unit 2673
February 11, 2026