DETAILED ACTION
This action responds to Application No. 18/589259, filed 02/27/2024, and to the preliminary amendment dated 05/06/2024.
At this point, claim 1 has been cancelled. Claims 2-21 have been added. Claims 2-21 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/27/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Re claim 21, the terms “data port means”, “memory means”, “interface means”, and “data path means” are subject to interpretation under 35 USC § 112(f).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2, 3-5, 6-7, 8, 9-11, 12-15, 16, 17-19, 20, and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 7-8, 6, 3-5, 9-12, 1, 6, 8, and 1, respectively, of U.S. Patent No. 11947474. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims merely represent broadened versions of the claims of Patent No. 11947474. Similarly, the instant claims represent broadened versions of the claims in Patent Nos. 10762010 and 11379392, respectively, which have both been subject to a terminal disclaimer over Patent No. 11947474 (See terminal disclaimer filed 02/25/2022).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Shaeffer (US 2013/0033954 A1).
Re claim 16, Shaeffer discloses the following:
A memory component comprising: an integrated circuit package comprising: (Fig. 1; ¶ 38). The memory module 110, or any combination of its sub-components, can be considered a “memory component”, as the memory module comprises it. Furthermore, Shaeffer suggests that one skilled in the art would be able to integrate the various circuits described in the invention into an integrated circuit (¶ 38);
a plurality of memory component data ports (Fig. 1, MDG0-15). The term “A memory component” may broadly be interpreted at least 3 ways. First, it may be interpreted as “a set of one or more memory components comprising”. Under this interpretation, the 8 memory components in each rank, or the 16 memory components in each memory module, are collectively connected to their respective component data ports comprising SDQ0/1; these collectively comprise the “at least one memory component. Second, since the rank is on memory, anything in said rank can be interpreted as a “memory component”. In addition to the memory devices 112A-112B, the ranks also contain secondary command buses SCA0/1, as well as resistors (see next to DDG0 and DDG12); any of these can be considered “memory components”, and the remaining set of memory devices 112A/B can be considered as a group to be another “memory component. Third, “a memory component” can be interpreted as meaning that for at least one specific memory component, that specific memory component comprises a plurality of data ports. Shaeffer discloses this for 3 reasons: 1) The data output from each components is routed through the plurality of data ports MDG0-15; accordingly, the path from a memory through this plurality of data ports can collectively be considered a “memory component”, and 2) it would have been an obvious design choice to group a plurality of the memory devices 112A/B, along with their respective ports, into a group called a “memory component”, because it would be a merely making them integral (see MPEP § 2144.04), and 3) the instant claims contain a plurality of memory ranks (groups), each containing a plurality of memory components (subgroups) that perform the function of sending data over the data ports. Shaeffer discloses a plurality of modules (groups), each containing a plurality of ranks (subgroups) that perform the function of sending data over the data ports. The functionality is the same, the only difference is which level of memory granularity is performing the function; accordingly, it would be an obvious design choice to structure the memory levels as rank/component rather than module/rank, as it is a mere change in size (MPEP § 2144.04);
a single memory core to store data; and (Fig. 1, memory devices 112A-B). Applicant has not explicitly defined “single memory core”, and the presence of the words “comprising […] single” does not explicitly preclude there from being additional memory cores (it does not require only a single core. Accordingly, Examiner interprets the memory devices 112A-B to collectively be a “single memory core”; moreover, even assuming, arguendo, that the memory devices were not “a single core”, it would nonetheless have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the memory devices, which already are grouped into a single “module”, into a single “core”, as it would be merely making the devices integral (see MPEP § 2144.04(V)(B);
a data interface to transfer data between the single memory core and the plurality of memory component data ports, the data interface supporting a first data width mode in which the data interface transfers data at a first bit width via a first set of the plurality of memory component data ports, the data interface supporting a second data width mode in which the data interface transfers data at a second bit width via a second set of the plurality of memory component data ports (p. 2, ¶ 19-20). The router (data interface) transfers data from the memory module/ranks (core) to the various ports MDG0-15. It supports 2 modes; full-width mode with a width of 2N (first set of data ports), and half-width mode with a width of N (second set of data ports; 2N is greater than N;
As noted above, Shaeffer discloses selecting first and second bit widths of N and 2N, respectively, and gives an example of N being 32 bits and 2N being 64; separately, it discloses that each memory device is 4 bits, and that the devices share 6x8 lines (lines 16-17 and 19); however, these are separately described as being disclosed “in one such embodiment”, so it is unclear whether they all refer to the same embodiment. Nonetheless, Shaeffer suggests that it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) that “the concepts above can be extended to any combination of external and internal data widths; memory die in accordance with some embodiments can be soldered directly to a board and either permanently or programmably configured to a particular width” (¶ 39). Accordingly, it would have been obvious to try selecting various first, second, and third widths for the respective components. Furthermore, as noted above, it would have been obvious to integrate the components of Shaeffer into an integrated circuit package, because Shaeffer suggests that one of ordinary skill in the art would be able to do so (¶ 38). Furthermore, it would be obvious to make the described components integral (See MPEP § 2144.04(V)(B)).
Re claim 17, Shaeffer discloses the memory component of claim 16, and further discloses that the first bit width is greater than the second bit width (¶ 19-20). The router (data interface) transfers data from the memory module/ranks (core) to the various ports MDG0-15. It supports 2 modes; full-width mode with a width of 2N (first set of data ports), and half-width mode with a width of N (second set of data ports). 2N is greater than N.
Re claim 21, Shaeffer discloses the memory component of claim 16 above; accordingly, it also discloses a memory component comprising means for implementing that memory component, as in claim 21 (see Shaeffer, claim 1).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shaeffer in view of Srinivasan (US 2009/0033954 A1).
Re claim 18 Shaeffer discloses the memory component of claim 16, and further discloses wherein in the first data width mode the data interface transfers the data at the first bit width and a first burst length, and in the second data width mode the data interface transfers the data at the second bit width and a second burst length (¶ 19-20). See claim 17 above. The time it takes to transfer data over the interface at the first bit width is the first burst length, and the time to transfer at the second bit width is the second burst length.
While Shaeffer discloses modes utilizing 2 different bit width, it does not explicitly disclose a first bit width and first burst length, and a second bit width and a second burst length, wherein the second burst length is different from the first burst length.
Srinivasan discloses that in the first data width mode the data interface transfers the data at the first bit width and a first burst length, and in the second data width mode the data interface transfers the data at the second bit width and a second burst length that is different than the first burst length (¶ 94). Under one setting (first bit width mode), the first bit width is 4 bytes (32 bits) and the burst length is 4. In the second setting (second bit width mode), the second bit width is 2 bytes (16 bits) and the burst length is 8. Accordingly, the first mode has a wider bit width and shorter (different) burst length than the second mode.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the burst length of Shaeffer, such that in a wider bit width mode, the burst length is shorter, as in Srinivasan, because it would be applying a known technique to improve a similar memory module in the same way. Shaeffer discloses a memory module which can operate in two different bit width modes, with corresponding burst lengths. Srinivasan also discloses a similar memory module which operates at different bit widths, and corresponding burst lengths, which has been modified in a similar way to the claimed invention, to compensate for bit width differences by using different burst lengths. It would have been obvious to one having ordinary skill in the art to modify the burst lengths of the different modes of Shaeffer to use a shorter burst length for a wider bit width, and a longer burst length for a narrower bit width, as in Srinivasan, because it would yield the predictable improvement of ensuring that the same amount of total data would be transmitted during a burst in either mode.
Re claim 19, Shaeffer and Srinivasan disclose the memory component of claim 18, and Srinivasan further discloses that the first burst length is shorter than the second burst length (¶ 94). Under one setting (first bit width), the first bit width is 4 bytes (32 bits) and the burst length is 4. In the second setting (second bit width), the second bit width is 2 bytes (16 bits) and the burst length is 8. Accordingly, the second mode has a narrower bit width and longer burst length than the first mode.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Shaeffer and Srinivasan, for the reasons noted in claim 18 above.
Re claim 20, Shaeffer and Srinivasan disclose the memory component of claim 19, and Srinivasan further discloses that the first bit width is eight bits and the first burst length is eight, and the second bit width is four bits and the second burst length is sixteen (¶ 33 and 45). Srinivasan discloses that a range of bit widths and burst lengths can be used, and that the data width (bit width x burst length) can be 64 bits (¶ 33). Accordingly, Srinivasan contemplated that combinations of bit widths times burst lengths that can be multiplied to produce 64 bits can be used, such as 8x8 and 4x16.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify try modifying the bit width/burst length combinations that add up to 64 bits of Srinivasan (combined with Shaeffer) to utilize 8x8 and 4x16 combinations, because it would be choosing from a finite number of identified, predictable solutions with reasonable expectation of success. A 64 bit data word width can be accomplished by a bit width/burst length combination of 1x64, 2x32, 4x16, 8x8, 16x4, 32x2, or 64x1, and choosing any one of them would yield predictable expectation of success (sending data at a data word width of 64 bits).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Li et al (US 2017/0270017). Discloses a memory with pluralities of ranks, banks, and chips (¶ 6).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132