DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is in response to communication received 11/13/2025. There are a total of 20 claims pending in the application. Claims 1, 5-6, 12, and 17 have been amended. Claims 21-23 have been added. No claims have been canceled.
IFORMATION CONCENING DRAWING:
3. Application’s drawing submitted on 02/27/2024 are acceptable for examination purposes.
INFORMATION CONCERNING FOREIGN PRIORITY:
4. Acknowledgment is made of applicant’s claim for foreign priority based on an application fled in Japan on O3/10/2023.
NFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
5. Claims 5-6 and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
6. Claim 5 has been amended to recite the limitation:
“wherein the integer value is inputted from the memory controller.”
The claimed specification does not appear to describe/support the limitation as described above.
7. Claim 6 has been amended to recite the limitation:
“wherein the buffer includes a plurality of buffer regions corresponding to different types of operations, and the control circuit stores the first address in one of the buffer regions corresponding to the type of the operation designated by the first instruction
8. Claim 18 has been amended to recite the limitation:
“wherein the buffer includes a plurality of buffer regions corresponding to different types of operations, and the control circuit stores the first address in one of the buffer regions corresponding to the type of the operation designated by the first command
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-10, 12, 15, 17-19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. “Lu” (US 20230280929 A1) in view of RHO “RHO” (US 20210382656 A1).
9. Regarding claim 1 Lu teaches or suggests:
“A memory system (e.g., Fig. 1) comprising: a nonvolatile memory;” (e.g., Fig. 1, ¶ 0055, flash memory device 110).
“a memory controller;” (e.g., Fig. 1, ¶ 0055, flash memory controller 105).
“and a control circuit including a buffer (e.g., Figs 2, ¶ 0062, the received address(es) buffered by the address register 1105) and configured to: in response to a first instruction received from the memory controller, the first instruction including a first address, store the first address in the buffer and output the first instruction to the nonvolatile memory,” (e.g., Fig. 22, ¶ 0136, the flash memory controller 105 sends the first command sub-sequence including the specific indication command 0xAA, page program command 0×80, block address and page address information of an LSB page of the m-th plane, multiple toggle LSB page data to be programed, and an intermediate confirm command such as a change write command such as the command 0×1A (but not limited). The addresses received from flash memory controller stored in the address register).
and in response to a second instruction that is received from the memory controller subsequent to the first instruction after a sense, data-out, program, or erase operation designated by the first instruction is executed by the nonvolatile memory” (e.g., Fig. 22, ¶ 0136, Then, the flash memory controller 105 sends the second command sub-sequence including the specific indication command 0×AA, page program command 0×80, block address and page address information of a CSB page of the m-th plane, multiple toggle CSB page data to be programed, and the command 0×1A).
“generate a second address based on the first address stored in the buffer ¶ 0011, using the address control circuit to control the at least address decoder accessing at least one data unit, indicated by the address information transmitted from the address register, for at least one plane of the memory cell array; wherein the address information is first address information which is used for the first plane), and transmit the generated second address to the nonvolatile memory,” (e.g., Fig. 2, ¶ 0010, The address control circuit is arranged to automatically generate second address information associated with the second plane according to the first address information of the first plane). Lu teaches that sets of simplified sequential commands such as read, write (or program), and erase command send by the flash memory controller to the control section flash memory and stored in registers. The commands and address are transmitted from the control section to be executed by the non-volatile memory.
“wherein the nonvolatile memory is configured to execute the sense, data-out, program, or erase operation designated by the first instruction received from the control circuit,” (e.g., Fig. 2, ¶ 0096, selecting multiple data units at the first plane and the second plane based on the first address information and the second address information in response to the command information buffered in the command register 1106 so as to perform an access operation upon the multiple data units at the first plane and the second plane). However, the Examiner chosen to include disclosure by RHO comprising timing information:
“and to execute another sense, data-out, program, or erase operation based on the generated second address received from the control circuit.” (e.g., RHO: Fig. 5, ¶ 0070, Referring to FIG. 5, a first command sequence 502 and a second command sequence 504 are page read commands for each target plane; ¶ 0072, The first command sequence 502 may include a “01h/02h/03h” signal, a “00h” signal, a “C1-C2” signal indicating a column address of a target page, an “R1-R2-R3” signal indicating a row address of the target page and a “32h” signal. The “01h/02h/03h” signal may be selected according to which one of LSB, CSB and MSB of a selected page is read when a memory cell of the selected page is, for example, a triple level cell (TLC); ¶ 0072, The second command sequence 504 may include a “01h/02h/03h” signal, a “00h” signal, a “C1-C2” signal, an “R1-R2-R3” signal and a “30h” signal. The “01h/02h/03h” signal, the “00h” signal, the “C1-C2” signal and the “R1-R2-R3” signal are the same as described in the first command sequence 502. The “30h” signal may indicate that a corresponding command is the last page read command for the multi-plane read operation). Fig. 5, shows a timing diagram for multi-plane read operations. It shows a first sequence of commands denoted as 502 in the Fig. (e.g., first timing). The Fig. 5 also shows a second sequence of commands denoted as 504 in the Fig. (e.g., second timing) after a busy time tWB.
Disclosures by Lu and RHO are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller disclosed by Lu to include performing different command operations in different portions of the non-volatile memory device (e.g., planes) taught by RHO.
The motivation to enable performing different command operations in different portions of the non-volatile memory includes to reduce a time, required for a multi-plane read operation of a memory device (e.g., see par. 0005 of RHO).
Therefore, it would have been obvious to combine teaching of RHO with Lu to obtain the invention as specified in the claim.
10. Regarding claim 12 Lu teaches or suggests:
“A memory system (e.g., Fig. 1) comprising: a nonvolatile memory;” (e.g., Fig. 1, ¶ 0055, flash memory device 110).
“a memory controller;” (e.g., Fig. 1, ¶ 0055, flash memory controller 105).
“and a control circuit including a buffer and configured to: in response to a command received from the memory controller, store the command in the buffer and output the command to the nonvolatile memory (e.g., ¶ 0010, address control circuit is arranged to automatically generate second address information associated with the second plane according to the first address information of the first plane… in response to the command information buffered in the command register).
“and in response to an instruction that is received from the memory controller after a sense, data-out, program, or erase operation designated by the command is executed by the nonvolatile memory, transmit the command stored in the buffer to the nonvolatile memory (e.g., Fig. 22, ¶ 0136, the flash memory controller 105 sends the first command sub-sequence including the specific indication command 0xAA, page program command 0×80, block address and page address information of an LSB page of the m-th plane, multiple toggle LSB page data to be programed, and an intermediate confirm command such as a change write command such as the command 0×1A (but not limited). The addresses received from flash memory controller stored in the address register). However, the Examiner chosen to include disclosure by RHO comprising timing information:
“wherein the nonvolatile memory is configured to execute the sense, data-out, program, or erase operation designated by the command received from the control circuit at the (e.g., RHO: Fig. 5, ¶ 0070, Referring to FIG. 5, a first command sequence 502 and a second command sequence 504 are page read commands for each target plane; ¶ 0072, The first command sequence 502 may include a “01h/02h/03h” signal, a “00h” signal, a “C1-C2” signal indicating a column address of a target page, an “R1-R2-R3” signal indicating a row address of the target page and a “32h” signal. The “01h/02h/03h” signal may be selected according to which one of LSB, CSB and MSB of a selected page is read when a memory cell of the selected page is, for example, a triple level cell (TLC); ¶ 0072, The second command sequence 504 may include a “01h/02h/03h” signal, a “00h” signal, a “C1-C2” signal, an “R1-R2-R3” signal and a “30h” signal. The “01h/02h/03h” signal, the “00h” signal, the “C1-C2” signal and the “R1-R2-R3” signal are the same as described in the first command sequence 502. The “30h” signal may indicate that a corresponding command is the last page read command for the multi-plane read operation). Fig. 5, shows a timing diagram for multi-plane read operations. It shows a first sequence of commands denoted as 502 in the Fig. (e.g., first timing). The Fig. 5 also shows a second sequence of commands denoted as 504 in the Fig. (e.g., second timing) after a busy time tWB
. The motivation for combining is based on the same rational presented for rejection of claim 1.
13. Regarding claim 17 Lu teaches or suggests:
“A method of processing a sequence of commands issued by a memory controller (e.g., ¶¶ 0053, 106), the commands in the sequence including a first command followed by a second command (e.g., Fig. 2, ¶ 0059, command sequences), said method comprising: storing in a buffer a first address that is transmitted by the memory controller and associated with the first command;” (e.g., ¶ 0010, The command register is coupled to the I/O control circuit and used for buffering command information sent from the flash memory controller and transmitted through the I/O control circuit. The address register is coupled to the I/O control circuit and used for buffering address information sent from the flash memory controller and transmitted through the I/O control circuit).
“generating a second address based on the first address stored in the buffer;” (e.g., ¶ 0010, address control circuit is arranged to automatically generate second address information associated with the second plane according to the first address information of the first plane… in response to the command information buffered in the command register).
“and transmitting the first command and the first address to a nonvolatile memory for execution of a sense, data-out, program, or erase operation designated by the first command by the nonvolatile memory;” (e.g., Fig. 22, ¶ 0136, the flash memory controller 105 sends the first command sub-sequence including the specific indication command 0xAA, page program command 0×80, block address and page address information of an LSB page of the m-th plane, multiple toggle LSB page data to be programed, and an intermediate confirm command such as a change write command such as the command 0×1A (but not limited). The addresses received from flash memory controller stored in the address register).
“generating a second address based on the first address stored in the buffer in response to receiving the instruction;” (e.g., ¶ 0010, address control circuit is arranged to automatically generate second address information associated with the second plane according to the first address information of the first plane… in response to the command information buffered in the command register).
“and transmitting the second command and the second address to the nonvolatile memory for execution of another sense, data-out, program, or erase operation designated by the second command, by the nonvolatile memory.” (e.g., Fig. 22, ¶ 0136, Then, the flash memory controller 105 sends the second command sub-sequence including the specific indication command 0×AA, page program command 0×80, block address and page address information of a CSB page of the m-th plane, multiple toggle CSB page data to be programed, and the command 0×1A). However, the Examiner chosen to include disclosure by RHO comprising timing information:
“receiving an instruction outputted from the memory controller after execution of the sense, data-out, program, or erase operation designated by the first command, by the nonvolatile memory;” (e.g., RHO: Fig. 5, ¶ 0070, Referring to FIG. 5, a first command sequence 502 and a second command sequence 504 are page read commands for each target plane; ¶ 0072, The first command sequence 502 may include a “01h/02h/03h” signal, a “00h” signal, a “C1-C2” signal indicating a column address of a target page, an “R1-R2-R3” signal indicating a row address of the target page and a “32h” signal. The “01h/02h/03h” signal may be selected according to which one of LSB, CSB and MSB of a selected page is read when a memory cell of the selected page is, for example, a triple level cell (TLC); ¶ 0072, The second command sequence 504 may include a “01h/02h/03h” signal, a “00h” signal, a “C1-C2” signal, an “R1-R2-R3” signal and a “30h” signal. The “01h/02h/03h” signal, the “00h” signal, the “C1-C2” signal and the “R1-R2-R3” signal are the same as described in the first command sequence 502. The “30h” signal may indicate that a corresponding command is the last page read command for the multi-plane read operation). Fig. 5, shows a timing diagram for multi-plane read operations. It shows a first sequence of commands denoted as 502 in the Fig. (e.g., first timing). The Fig. 5 also shows a second sequence of commands denoted as 504 in the Fig. (e.g., second timing) after a busy time tWB. The motivation for combining is based on the same rational presented for rejection of claim 1.
14. Regarding claim 2 Lu further teaches:
“wherein the second address is an address that is continuous to the first address in a physical address space of the nonvolatile memory.” (e.g., Fig. 22, ¶ 0136, FIG. 22 shows two examples of the command sequence sent by the flash memory controller 105 for the write operation of TLC mode according to another embodiment of the invention…page address information of an LSB page of the m-th plane…page address information of a CSB page of the m-th plane…the command sub-subsequence associate with the MSB page). Fig. 3 of Lu teaches Programming a TLC (Triple-Level cell). The programming of a TLC comprises three level or pages of the memory cell to be programmed. There are LSB (Least Significant Bit), CSB (Center Significant Bit, and MSB (Most Significant Bit). The LSB/CSB/MSB address are continuous.
15. Regarding claim 3, Lu further teaches:
wherein the control circuit generates the second address when locations of the nonvolatile memory are being sequentially accessed.” (e.g., ¶ 0070, flash memory device 110, can be enabled and configured as a sequential data read mode which will be arranged to sequentially transmit block data or page data of all the different planes from the flash memory device 110 to the flash memory controller).
16. Regarding claim 4, Lu further teaches:
“wherein the control circuit generates the second address by adding or subtracting an integer value to or from the first address.” (e.g., Figs. 33-35, ¶ 0168, the flash memory controller 105 can send a simplified command sequence, associated with an access operation such as the data read, copy back read, erase, or the write operation, in which plane bit map information and/or block address information is/are added to indicate whether to change some plane/block address information). The address information associated with the command is/are added (or subtracted in the command in order to change/generate plane/block address information.
17. Regarding claim 5, Lu further teaches:
“wherein (e.g., ¶ 0010, address control circuit is arranged to automatically generate second address information associated with the second plane according to the first address information of the first plane; Figs. 33-35 and corresponding text description). Address information associated with block/plane address (or number) may be added to generate a second or different addresses.
18. Regarding claims 6 and 18, Lu further teaches:
“wherein the buffer includes a plurality of buffer regions corresponding to different types of operations, and the control circuit stores the first address in one of the buffer regions corresponding to the type of operation designated by instruction (e.g., ¶ 0010, The command register is coupled to the I/O control circuit and used for buffering command information sent from the flash memory controller and transmitted through the I/O control circuit; ¶ 0055, sending access (e.g. read, write, or erase)). Lu does not expressly buffer includes a plurality regions corresponding to different type of operation but teaches the command register used to buffer differ different types of commands such read, write, or erase for performing read, write/program, and erase operation. The different types of command must be stored in different locations (regions) in command register. Lu inherently teaches the limitation.
19. Regarding claims 7 and 19, Lu further teaches:
“wherein the buffer includes a plurality of buffer regions corresponding to different planes of the nonvolatile memory, and the control circuit stores the first address in one of the buffer regions corresponding to the plane of the nonvolatile memory that is being accessed in connection with the transmission of the first address by the memory controller.” (e.g., Fig. 2, ¶ 0062, the control circuit 1103 of the flash memory device 110 is arranged to control the row address decoder 1108 and the column address decoder 1109 to control the memory cell array 1107 outputting corresponding block data or page data to the data register 1110 based on the received address(es) buffered by the address register 1105 and the received command(s) buffered by the command register 1106, so that the corresponding block data or page data of the different planes PLN0, PLN1, PLN2, and PLN3 can be transmitted from the memory cell array 1107 to and buffered in the buffers of the data register 1110; Fig. 22, ¶ 0136, FIG. 22 shows two examples of the command sequence sent by the flash memory controller 105 for the write operation of TLC mode according to another embodiment of the invention). Fig. 22 describes writing data to TLC memory comprising writing to three-level or page of memory.
20. Regarding claim 9, Lu further teaches:
“wherein the buffer includes a first buffer region in which the first address is stored and a second buffer region in which a command transmitted by the memory controller is stored, and the control circuit is configured to transmit the command stored in the second buffer region along with the second address to the nonvolatile memory.” (e.g., Fig. 2, ¶ 0062, the control circuit 1103 of the flash memory device 110 is arranged to control the row address decoder 1108 and the column address decoder 1109 to control the memory cell array 1107 outputting corresponding block data or page data to the data register 1110 based on the received address(es) buffered by the address register 1105 and the received command(s) buffered by the command register 1106, so that the corresponding block data or page data of the different planes PLN0, PLN1, PLN2, and PLN3 can be transmitted from the memory cell array 1107 to and buffered in the buffers of the data register 1110).
21. Regarding claim 10, Lu further teaches:
“wherein the memory controller transmits the first address to the control circuit using a first signal line (e.g., Fig. 2, ¶ 0060, in the first sub-step of FIG. 2), and the control circuit transmits the command stored in the second buffer region along with the second address to the nonvolatile memory based on an external control signal that is transmitted from the memory controller to the control circuit using a second signal line different from the first signal line.” (e.g., Fig. 2, ¶ 0062, second sub-step of FIG. 2).
22. Regarding claim 15, Lu further teaches:
“ wherein the memory controller transmits the command to the control circuit using a first signal line, and the control circuit transmits the command stored in the buffer to the nonvolatile memory in response to an instruction that is transmitted from the memory controller to the control circuit using a second signal line different from the first signal line.” (e.g., Fig. 2, ¶ 0062; Figs. 1-2 and corresponding text descriptions).
23. Regarding claim 21, Lu further teaches:
“wherein the first instruction includes a first command designating one of the sense, data-out, program, and erase operations.” (e.g., ¶ 0126, the flash memory controller 105 sequentially sending an SLC programming instruction/command such as 0xA2 (but not limited)).
24. Regarding claim 22, Lu further teaches:
“wherein the control circuit is configured to receive an address based on an assertion of a first signal and receive the command based on an assertion of a second signal different from the first signal, and the instruction includes a simultaneous assertion of the first signal and the second signal.” (e.g., ¶ 0061, memory controller 105 controls the signal of the pin ALE at a low level and controls the signal of the pin CLE at a high level so that the flash memory device 110 can know that the data received via the pins DQ0-DQ7 is command data and then can store the received command data into the command register of FIG. 1). Controlling ALE to be at low level and CLE at high level comprises simultaneous (e.g., at the same time) assertion of the signal at stated level.
25. Regarding claim 23, Lu further teaches:
“wherein the first signal is an address latch enable signal (e.g., ALE), and the second signal is a command latch enable signal.” (e.g., ¶ 0056, logic control pins such as CLE (Command Latch Enable), ALE (Address Latch Enable)).
Claims 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view RHO as applied to claims 1 and 12 above, and further in view of Kanapathippillai et al. “Kanapathippillai” (US 20080094808 A1).
12. Regarding claims 11 and 16, Lu in view of RHO teaches all limitations included in claims 1 and 12 but does not expressly teach while Kanapathippillai discloses:
“wherein the nonvolatile memory and the control circuit are included in one package.” (e.g., Fig. 5c, ¶ 0078, The multi-chip packaged flash memory/support ASIC part 510 includes one or more unpackaged flash memory dice 118' and an unpackaged address/control/data support ASIC die 550 coupled together as shown) including address/control circuits with flash memory in the same package.
Disclosures by Lu, RHO and Kanapathippillai are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller disclosed by Lu to include performing different command operations in different portions of the non-volatile memory device (e.g., planes) taught by RHO; furthermore to include address/control circuit with flash memory die in the same package taught by Kanapathippillai.
The motivation to enable performing different command operations in different portions of the non-volatile memory includes to reduce a time, required for a multi-plane read operation of a memory device (e.g., see par. 0005 of RHO); furthermore, the motivation for including the address/control circuit with flash memory die in the same package as taught by Kanapathippillai is to reduce the number of PCB traces and further reduce the height of the PCB and DIMM. In this manner, a flash DIMM may be more widely sold and used to achieve economies of scale (e.g., see paragraphs [0035-0037 of Kanapathippillai).
Therefore, it would have been obvious to combine teaching of Kanapathippillai and RHO with Lu to obtain the invention as specified in the claim.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view RHO as applied to claims 1 and 12 above, and further in view of Moon “Moon” (US 20080094808 A1).
13. Regarding claim 13, Lu in view of RHO teaches all limitations included in claim 12 but does not expressly teach while Moon discloses:
“wherein the control circuit stores a plurality of commands in the buffer, and transmits the plurality of commands stored in the buffer to the nonvolatile memory in the same order as they were stored in the buffer.” (e.g., Fig. 2, ¶ 0060, the command queue 120 may include a plurality of plane queues, each of which may queue-in and queue-out commands on a first in first out (FIFO) basis. The command queue 120 may receive (i.e., queue-in) a command from the CPU 110 and output (i.e., queue-out) the received (i.e., queued-in) command to a plane corresponding to each plane queue in response to control of the command queue controller 140) storing command in FIFO queue (e.g., buffer) maintain the order of inputting and outputting the.
Disclosures by Lu, RHO, and Moon are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller disclosed by Lu to include performing different command operations in different portions of the non-volatile memory device (e.g., plane
s) taught by RHO; furthermore to include outputting (e.g., transmitting commands in the same order they are inputted (e.g., stored) in the queue.
The motivation to enable performing different command operations in different portions of the non-volatile memory includes to reduce a time, required for a multi-plane read operation of a memory device (e.g., see par. 0005 of RHO); furthermore; the motivation for including the FIFO queue to store command is to improve the command management.
Therefore, it would have been obvious to combine teaching of Moon and RHO with Lu to obtain the invention as specified in the claim.
14. Regarding claim 14, Lu further teaches:
“wherein the buffer includes a first buffer region in which a first address transmitted by the memory controller is stored, and a second buffer region in which the plurality of commands transmitted by the memory controller are stored , and the control circuit is configured to generate a second address based on the first address stored in the first buffer region, and transmit the generated second address to the nonvolatile memory after transmitting the plurality of commands stored in the second buffer region to the nonvolatile memory.” (e.g., ¶0010, The address control circuit is arranged to automatically generate second address information associated with the second plane according to the first address information of the first plane, and then selecting multiple data units at the first plane and the second plane based on the first address information and the second address information in response to the command information buffered in the command register so as to perform an access operation upon the multiple data units at the first plane and the second plane).
Allowable Subject Matter
Claims objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Remarks
Applicant’s arguments have been fully considered but they are not persuasive.
Page 7 of the Remark recites:
“According to amended claim 1, the control circuit (1) stores a first address in its buffer in “response to a first instruction received from the memory controller" and (2) generates a second address based on the first address stored in the buffer and transmit the generated second address to the nonvolatile memory "in response to a second instruction that is received from the memory controller subsequent to the first instruction after a sense, data-out, program, or erase operation designated by the first instruction is executed by the nonvolatile memory." It is noted herein that paragraph [0071] of the application equates "setup" with "sense" and "read" with "data-out," and paragraph [0081] of the application uses the terms "write operation" and "program operation" interchangeably.”” (Emphasis added).
The paragraphs [0071] and [0081] describes the types of operation specified by commands/instructions and addresses used to access a non-volatile memory. They don’t describe/support the amended limitation highlighted above and included in the independent claims. In fact, the specification is silence regarding “second instruction” or “second command”. Page 8 of the Remarks recites:
“The cited prior art does not teach any circuit that generates a second address based on a first address stored in the buffer and transmits the generated second address to the nonvolatile memory responsive to "a second instruction that is received from the memory controller subsequent to the first instruction after a sense, data-out, program, or erase operation designated by the first instruction is executed by the nonvolatile memory."”
The Examiner respectfully disagrees. Lu teaches:
“[0011] According to the embodiments, a method of the above-mentioned flash memory device is disclosed. The method comprises: using the command register to buffer command information sent from the flash memory controller and transmitted through the I/O control circuit; using the address register to buffer address information sent from the flash memory controller and transmitted through the I/O control circuit; using the address control circuit to control the at least address decoder accessing at least one data unit, indicated by the address information transmitted from the address register, for at least one plane of the memory cell array; wherein the address information is first address information which is used for the first plane and is carried by a single command sequence; the step of using the address control circuit comprises: controlling the address control circuit automatically generating second address information associated with the second plane according to the first address information of the first plane, and then selecting multiple data units at the first plane and the second plane based on the first address information and the second address information in response to the command information buffered in the command register so as to perform an access operation upon the multiple data units at the first plane and the second plane.” (Emphasis added).
As noted above, Lu teaches an address register for storing address information received from the memory controller (e.g., address register 1105 in Fig. 10) and a command register for storing command received from the memory controller ((e.g., command register 1106 in Fig. 10). Applicant make a reference to Fig. 17 of Lu and appears to agree that there are sequence of commands for writing data into a plurality of planes, but states “however none of these commands received from the memory controller. Par. [0125] of Lu recites in part: “FIG. 17 shows three examples of the command sequence sent by the flash memory controller 105 …”. In Fig. 17 data sequentially is written to the plurality of planes m to plane p. sequentially means data first written to plane m then plane n and so on. Furthermore, par. [0136] of Lu recites:
[0136] In other embodiment, the address control circuit 1112 can be arranged to automatically generate the page address information pages of an LSB/CSB/MSB super page in the different planes in response to page address of only one LSB/CSB/MSB page at one plane. FIG. 22 shows two examples of the command sequence sent by the flash memory controller 105 for the write operation of TLC mode according to another embodiment of the invention. In the example of FIG. 22, the flash memory controller 105 sequentially sends three command sub-sequences. At the first, the flash memory controller 105 sends the first command sub-sequence including the specific indication command 0xAA, page program command 0×80, block address and page address information of an LSB page of the m-th plane, multiple toggle LSB page data to be programed, and an intermediate confirm command such as a change write command such as the command 0×1A (but not limited). The command 0×1A is used to indicate the end of a command sub-sequence. Then, the flash memory controller 105 sends the second command sub-sequence including the specific indication command 0×AA, page program command 0×80, block address and page address information of a CSB page of the m-th plane, multiple toggle CSB page data to be programed, and the command 0×1A. Finally, the flash memory controller 105 sends the third command sub-sequence including the specific indication command 0×AA, page program command 0×80, block address and page address information of an MSB page of the m-th plane, and the write confirm command 0×10. It should be noted that the order of the above command sub-sequences can be changed, and for example the command sub-subsequence associate with the MSB page data can be transmitted at first while the command sub-subsequence associate with the LSB page data can be transmitted finally; this also falls within the scope of the invention.” (emphasis added).
It is clear, at least from the above paragraph, command sub-sequences are sequentially sent from the memory controller. However, in response to new amendment specifically in regard to different time limitation, the Examiner has included disclosure of RHO that teaches timing diagram for multiple read commands sequences by additional busy time tWB (e.g., see Fig. 5 of RHO) between the set of read commands.
In summary, the Examiner respectfully submits that Lu in view of RHO and the other prior art of record that relied on, teach or render obvious all limitations recited in the rejected claims. Thus, Examiner maintains his position.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138