Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Species X1, reading on claims 1-8, 11-18 in the reply filed on 06/15/2026 is acknowledged.
Claims 9-10, 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/15/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-8, 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gan et al. (US 20210118988 A1; hereinafter “Gan”) in view of Cai et al. (US 8445356 B1; hereinafter “Cai”) and Liu et al. (US 20210118989 A1; hereinafter “Liu”).
In re claim 1, Gan discloses in figs. 1-9, a semiconductor storage device comprising:
a first chip 400 and a second chip 500 that are bonded to each other (¶106),
wherein the first chip 400 includes a semiconductor substrate 430 having a first surface 430-1 (the surface of substrate 430 onto which transistors 450A, 450B have been formed) and a second surface (the opposite surface of the substrate 430 which has been thinned down from backside 430-2; hereinafter “430-2’”) intersecting a first direction Z (figs. 4, 9; ¶68);
a plurality of transistors provided on the first surface of the semiconductor substrate,
a plurality of transistors 450A, 450B provided on the first surface of the semiconductor substrate 430-1 (¶67, 69),
a plurality of first contacts 464 extending in the first direction Z and connected to the plurality of transistors 450A, 450B (¶83), and
a plurality of first bonding electrodes 486 electrically connected to the plurality of transistors 450A, 450B via the plurality of first contacts 464 (¶101),
the second chip 500 includes a plurality of first conductive layers 574 arranged in the first direction Z (¶94),
a semiconductor column 338 extending in the first direction Z and facing the plurality of first conductive layers 574 (¶95-96),
a plurality of second contacts 214 extending in the first direction Z and connected to the plurality of first conductive layers 574 (¶98), and
a plurality of second bonding electrodes 586 (¶101),
the plurality of first bonding electrodes 486 are bonded to the plurality of second bonding electrodes 586 (¶101),
the plurality of transistors include a first transistor 450A and a second transistor 450B adjacent to each other in a second direction X intersecting the first direction Z,
the semiconductor substrate 430 includes a first insulating member 452 provided between the first transistor 450A and the second transistor 450B and extending in the first direction Z from the first surface of the semiconductor substrate 430-1 to a first position (e.g., an upper surface position of the STI 452; hereinafter “452_top”) between the first surface 430-1 and the second surface 430-2’ of the semiconductor substrate (fig. 9; ¶70, 116-117), and
a second insulating member 994 provided at a position overlapping the first insulating member 452 when viewed in the first direction Z and extending in the first direction Z from the second surface of the semiconductor substrate 430-2’ to the first position of the semiconductor substrate 452_top (fig. 9; ¶119).
Gan does not expressly disclose a width of the second insulating member in the second direction at the second surface is larger than a width of the first insulating member in the second direction at the first surface.
In the same field of endeavor, Cai discloses in fig. 8, a semiconductor device comprising a first insulating member 28 (e.g., STI), a second insulating member 30 (e.g., DTI) provided at a position overlapping the first insulating member 28, wherein a width of the second insulating member 30 in a horizontal direction at a lower surface is larger than a width of the first insulating member 28 in the horizontal direction at an upper first surface (C. 5, para. 4-5).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to make a width of the second insulating member in the second direction at the second surface is larger than a width of the first insulating member in the second direction at the first surface in the device of Gan as Cai teaches the presence of the wider, bottle-shaped lower portion of the DTI 30 beneficially relaxes the inter-well overlay precision requirements, thereby improving yield while providing enhanced inter-well isolation and reduced well resistance (C. 5, para. 4).
Gan, as modified by Cai, does not expressly disclose the plurality of second bonding electrodes connected to the plurality of first conductive layers via the plurality of second contacts.
In the same field of endeavor, Liu discloses in figs. 1-9, a semiconductor storage device comprising:
a plurality of second bonding electrodes 586 connected to a plurality of first conductive layers 574 via a plurality of second contacts 214 (¶93, 96).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Liu into in the storage device of Gan to select word lines via a peripheral circuitry that is vertically stacked above the storage device and can address the density limitation in planar memory cells (¶2-4 of Liu).
In re claim 4, Gan, as modified by Cai and Liu, discloses the semiconductor device according to claim 1 outlined above.
Gan further discloses in figs. 8-9, wherein the width of the first insulating member 452 in the second direction X at the first surface 430-1 is larger than a width in the second direction X at the first position 452_top, and the width of the second insulating member 994 in the second direction X at the second surface 430-2’ is larger than a width in the second direction X at the first position 452_top (¶117).
In re claim 5, Gan, as modified by Cai and Liu, discloses the semiconductor device according to claim 1 outlined above.
Gan further discloses the cross-sectional shapes and numbers of deep isolation trenches can be determined by various factors, such as the amount of need for device isolation and the type of devices (¶117). Gan does not expressly disclose wherein a width of the second insulating member in the second direction at the first position is larger than a width of the first insulating member in the second direction at the first position.
However, it has been held to be within the general skill of a worker in the art to select a width of the second insulating member in the second direction at the first position is larger than a width of the first insulating member in the second direction at the first position on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to experiment with the widths of the first insulating member (e.g., STI) and second insulating member (e.g., DTI) and select a width of the second insulating member in the second direction at the first position is larger than a width of the first insulating member in the second direction at the first position in order to prevent crosstalk between adjacent structures, such as between wells of different doping types and to prevent an electrical short circuit between wells that are coupled to different bias voltages (¶119 of Gan).
In re claim 6, Gan, as modified by Cai and Liu, discloses the semiconductor device according to claim 1 outlined above.
Gan further discloses in figs. 8-9, 10B, wherein the plurality of transistors includes a first group of transistors (e.g., the left column of 1010B, 1010A in fig. 10B) that are arranged in a third direction Y intersecting the first direction Z and the second direction X, and
a second group of transistors (e.g., the right column of 1010B, 1010A in fig. 10B) that are arranged in the third direction Y and spaced apart from the first group (i.e., the left column of 1010B, 1010A in fig. 10B) in the second direction X, and
the second insulating member 1094 extends in the third direction Y (e.g., at least partially extend) between the first group of transistors (i.e., the left column of 1010B, 1010A in fig. 10B) and the second group of transistors (i.e., the right column of 1010B, 1010A in fig. 10B).
In re claim 7, Gan, as modified by Cai and Liu, discloses the semiconductor device according to claim 6 outlined above.
Gan further discloses in figs. 8-9, 10B, wherein the plurality of first conductive layers 574 extend in the third direction Y (e.g., in and out of the paper direction).
In re claim 8, Gan, as modified by Cai and Liu, discloses the semiconductor device according to claim 1 outlined above.
Gan further discloses in fig. 9, wherein the first chip 400 includes a third contact (e.g., S/D contact of the MOSFET 450A; hereinafter “CNT3”) extending in the first direction Z from the first surface of the semiconductor substrate 430-1,
the semiconductor substrate 430 includes a first region (e.g., the bulk region underneath the wells 451, 454) containing a first conductivity-type impurity (e.g., p-type), and
a second region (e.g., S/D region of the PFET 450A) in contact with the third contact CNT3 and containing the first conductivity-type impurity (i.e., p-type), and
a concentration of the first conductivity-type impurity in the second region (S/D region) is higher than a concentration of the first conductivity-type impurity in the first region (bulk substrate region) (¶69, 79-81).
In re claim 11, Gan, as modified by Cai and Liu, discloses the semiconductor device according to claim 1 outlined above.
Gan further discloses in fig. 9, wherein the semiconductor substrate 430 contains a first conductivity-type impurity (e.g., p-type; ¶71) and includes a first well 454, 451 containing a second conductivity-type impurity (e.g., n-type; ¶67) different from the first conductivity-type, and
a second well 457 provided at a position overlapping the first well 454 when viewed in the first direction Z and containing the first conductivity-type impurity (e.g., p-type; ¶67), and
one of the plurality of the transistors 450B are provided in the second well 457.
Gan does not expressly disclose a plurality of the transistors are provided in the second well.
In re claim 12, Gan, as modified by Cai and Liu, discloses the semiconductor device according to claim 11 outlined above.
Gan further discloses in fig. 9, wherein the first chip 400 includes a fifth contact (one of the S/D contact of the MOSFET 450A; hereinafter “CNT5”) extending in the first direction Z from the first surface of the semiconductor substrate 430-1 (¶92), and
a sixth contact (the right S/D contact of the MOSFET 450B; hereinafter “CNT6”) extending in the first direction Z from the first surface of the semiconductor substrate 430-1 (¶92),
the semiconductor substrate 430 includes a fourth region 460 formed in the first well 451 at the first surface 430-1, in contact with the fifth contact CNT5, and containing the second conductive type impurity (e.g., p-type, because MOSFET 450A is a PFET; ¶69), and
a fifth region (e.g., S/D diffusion region of the NFET 450B) formed in the second well 457 at the first surface 430-1, in contact with the sixth contact CNT6, and containing the first conductive type impurity (e.g., n-type, because MOSFET 450B is an NFET; ¶69).
Gan does not have expressed teachings of a concentration of the second conductivity-type impurity in the fourth region 460 in 450A is higher than a concentration of the second conductivity-type impurity in the first well 451 (¶80-81), and a concentration of the first conductivity-type impurity in the fifth region 460 in 450B is higher than a concentration of the first conductivity-type impurity in the second well 457.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the source/drain regions having higher doping concentrations than the wells in order to reduce contact resistance of the source/drain regions.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gan in view of Cai and Liu, as applied to claim 1 above and further in view of Chen et al. (US 20230299042 A1; hereinafter “Chen”).
In re claim 2, Gan, as modified by Cai and Liu, discloses the semiconductor device according to claim 1 outlined above.
Gan further discloses in figs. 8-9, wherein the semiconductor substrate 430 includes a first semiconductor region 451, 454 surrounded by the second insulating member 994 at the first surface of the semiconductor substrate 430-1 (¶67, 119),
the plurality of transistors include the first transistor 450A having a channel region provided in the first semiconductor region 451 and a third transistor 450B having a channel region.
Gan, as modified by Cai and Liu, does not expressly disclose the third transistor having a channel region provided in the first semiconductor region, and the first semiconductor region is continuous from a channel region of the first transistor to a channel region of the third transistor.
In the same field of endeavor, Chen discloses in fig. 13, a semiconductor storage device comprising:
a third transistor 408 having a channel region provided in the first semiconductor region 402, and the first semiconductor region 402 is continuous from a channel region of a first transistor 408 to a channel region of the third transistor 408 (¶59-60; middle two transistors 408 have continuous channel regions).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen into the device Gan/Cai/Liu in order to form various logic devices to control the memory devices formed thereon.
In re claim 3, Gan, as modified by Cai, Liu and Chen, discloses the semiconductor device according to claim 2 outlined above.
Gan further discloses in figs. 8-9, wherein the semiconductor substrate 430 further includes a third insulating member (e.g., 452 in between MOSFETs 450A and 450B) (¶69) provided between the first transistor 450A and the third transistor 450B and extending in the first direction Z from the first surface of the semiconductor substrate 430-1 to a second position (e.g., a second position that below the upper surface of the well 451 as shown in fig. 9) between the first surface 430-1 and the second surface of the semiconductor substrate 430-2.
Claim(s) 13, 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gan et al. (US 20210118988 A1; hereinafter “Gan”) in view of Cai et al. (US 8445356 B1; hereinafter “Cai”).
In re claim 13, Gan discloses in figs. 1-9, a semiconductor device comprising:
a semiconductor substrate 430 having a first surface 430-1 (the surface of substrate 430 onto which transistors 450A, 450B have been formed) and a second surface (the opposite surface of the substrate 430 which has been thinned down from backside 430-2; hereinafter “430-2’”) intersecting a first direction Z (figs. 4, 9; ¶68); and
a plurality of transistors 450A, 450B provided on the first surface of the semiconductor substrate 430-1, wherein the plurality of transistors include a first transistor 450A and a second transistor 450B adjacent to each other in a second direction X intersecting the first direction Z (¶67, 69),
the semiconductor substrate 430 includes a first insulating member 452 provided between the first transistor 450A and the second transistor 450B and extending in the first direction Z from the first surface of the semiconductor substrate 430-1 to a first position (e.g., an upper surface position of the STI 452; hereinafter “452_top”) between the first surface 430-1 and the second surface 430-2’ of the semiconductor substrate (fig. 9; ¶70, 116-117), and
a second insulating member 994 provided at a position overlapping the first insulating member 452 when viewed in the first direction Z and extending in the first direction Z from the second surface of the semiconductor substrate 430-2’ to the first position of the semiconductor substrate 452_top (fig. 9; ¶119).
Gan does not expressly disclose a width of the second insulating member in the second direction at the second surface is larger than a width of the first insulating member in the second direction at the first surface.
In the same field of endeavor, Cai discloses in fig. 8, a semiconductor device comprising a first insulating member 28 (e.g., STI), a second insulating member 30 (e.g., DTI) provided at a position overlapping the first insulating member 28, wherein a width of the second insulating member 30 in a horizontal direction at a lower surface is larger than a width of the first insulating member 28 in the horizontal direction at an upper first surface (C. 5, para. 4-5).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to make a width of the second insulating member in the second direction at the second surface is larger than a width of the first insulating member in the second direction at the first surface in the device of Gan as Cai teaches the presence of the wider, bottle-shaped lower portion of the DTI 30 beneficially relaxes the inter-well overlay precision requirements, thereby improving yield while providing enhanced inter-well isolation and reduced well resistance (C. 5, para. 4).
In re claim 16, Han, as modified by Cai, discloses the semiconductor device according to claim 13 outlined above.
Gan further discloses in figs. 8-9, wherein the width of the first insulating member 452 in the second direction X at the first surface 430-1 is larger than a width in the second direction X at the first position 452_top, and the width of the second insulating member 994 in the second direction X at the second surface 430-2’ is larger than a width in the second direction X at the first position 452_top (¶117).
In re claim 17, Han, as modified by Cai, discloses the semiconductor device according to claim 13 outlined above.
Gan further discloses the cross-sectional shapes and numbers of deep isolation trenches can be determined by various factors, such as the amount of need for device isolation and the type of devices (¶117). Gan does not expressly disclose wherein a width of the second insulating member in the second direction at the first position is larger than a width of the first insulating member in the second direction at the first position.
However, it has been held to be within the general skill of a worker in the art to select a width of the second insulating member in the second direction at the first position is larger than a width of the first insulating member in the second direction at the first position on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to experiment with the widths of the first insulating member (e.g., STI) and second insulating member (e.g., DTI) and select a width of the second insulating member in the second direction at the first position is larger than a width of the first insulating member in the second direction at the first position in order to prevent crosstalk between adjacent structures, such as between wells of different doping types and to prevent an electrical short circuit between wells that are coupled to different bias voltages (¶119 of Gan).
In re claim 18, Han, as modified by Cai, discloses the semiconductor device according to claim 13 outlined above.
Gan further discloses in fig. 9, the device further comprising:
a first via contact electrode (e.g., S/D contact of the MOSFET 450A; hereinafter “Via”) that extends in the first direction Z from the first surface of the semiconductor substrate 430-1,
wherein the semiconductor substrate 430 includes a first region (e.g., the bulk region underneath the wells 451, 454) containing a first conductivity-type impurity (e.g., p-type), and
a second region (e.g., S/D region of the PFET 450A) in contact with the first via contact electrode Via and containing the first conductivity-type impurity (i.e., p-type), and
a concentration of the first conductivity-type impurity in the second region (S/D region) is higher than a concentration of the first conductivity-type impurity in the first region (bulk substrate region) (¶69, 79-81).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gan in view of Cai, as applied to claim 1 above and further in view of Chen et al. (US 20230299042 A1; hereinafter “Chen”).
In re claim 14, Gan, as modified by Cai, discloses the semiconductor device according to claim 13 outlined above.
Gan further discloses in figs. 8-9, wherein the semiconductor substrate 430 includes a first semiconductor region 451, 454 surrounded by the second insulating member 994 at the first surface of the semiconductor substrate 430-1 (¶67, 119),
the plurality of transistors include the first transistor 450A having a channel region provided in the first semiconductor region 451 and a third transistor 450B having a channel region.
Gan, as modified by Cai and Liu, does not expressly disclose the third transistor having a channel region provided in the first semiconductor region, and the first semiconductor region is continuous from a channel region of the first transistor to a channel region of the third transistor.
In the same field of endeavor, Chen discloses in fig. 13, a semiconductor storage device comprising:
a third transistor 408 having a channel region provided in the first semiconductor region 402, and the first semiconductor region 402 is continuous from a channel region of a first transistor 408 to a channel region of the third transistor 408 (¶59-60; middle two transistors 408 have continuous channel regions).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen into the device Gan/Cai in order to form various logic devices to control the memory devices formed thereon.
In re claim 15, Han, as modified by Cai and Chen, discloses the semiconductor device according to claim 14 outlined above.
Gan further discloses in figs. 8-9, wherein the semiconductor substrate 430 further includes a third insulating member (e.g., 452 in between MOSFETs 450A and 450B) (¶69) provided between the first transistor 450A and the third transistor 450B and extending in the first direction Z from the first surface of the semiconductor substrate 430-1 to a second position (e.g., a second position that below the upper surface of the well 451 as shown in fig. 9) between the first surface 430-1 and the second surface of the semiconductor substrate 430-2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Heineck et al. (US 20240079361 A1) discloses a memory chip and a peripheral chip vertically bonded to each other having STI and DTI in the peripheral circuit chip.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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