DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schultz et al., hereinafter Schultz, US Publication No. 2020/0092230.
Regarding Claim 1, Schultz teaches a method comprising:
receiving a circuit design (Schultz paragraphs [0071]-[0073], wherein a circuit design is received as source files, e.g. an RTL source, traffic specification, and constraints);
generating connections within a network-on-chip (NoC) by analyzing the circuit design to detect a first connection attribute, wherein the first connection attribute defines a first NoC master unit (NMU) and a first NoC slave unit (NSU) (Schultz paragraphs [0073], [0076], [0078] and [0083]-[0084], wherein the source files are analyzed and used to generate connections in a NoC, the traffic specification defining paths having connection attributes and which specify the NMUs and the NSUs to be connected); and
generating a first NoC configuration including the connections determined based on the first NMU and the first NSU (Schultz paragraphs [0077]-[0079], wherein the configuration of the NoC is generated and implemented including the paths).
Regarding Claim 2, Schultz further teaches analyzing the circuit design to determine a first constraint of the first NMU, and wherein the first NoC configuration is further generated based on the first constraint (Schultz paragraphs [0073] and [0078], wherein the constraint file specifies constraints for the NoC including the NMUs, with the configuration of the NoC generated to meet the constraints).
Regarding Claim 3, Schultz further teaches analyzing the circuit design to determine a second constraint of the first NSU, and wherein the first NoC configuration is further generated based on the second constraint (Schultz paragraphs [0073] and [0078], wherein the constraint file specifies constraints for the NoC including the NSUs, with the configuration of the NoC generated to meet the constraints).
Regarding Claim 4, Schultz further teaches wherein the first constraint is provided via a first constraint file associated with the circuit design, and analyzing the circuit design to determine the first constraint and the second constraint comprises analyzing the first constraint file (Schultz paragraph [0073], wherein the constraints are contained within the constraint files which are utilized to generate the configuration of the SoC).
Regarding Claim 5, Schultz further teaches wherein the first constraint and the second constraint define a connection between the first NMU and the first NSU (Schultz paragraph [0073], wherein the constraints include timing performance requirements which define the connection between components including the paths between the NMUs and the NSUs).
Regarding Claim 6, Schultz further teaches detecting the first connection attribute within one or more of an attribute portion or comment portion of the circuit design (Schultz paragraphs [0073] and [0076], wherein the connection attributes are contained within the traffic specification, the traffic specification being an attribute portion of the circuit design).
Regarding Claim 7, Schultz further teaches generating a block model based on the circuit design and the first NoC configuration determining a design topology of the circuit design (Schultz paragraphs [0073] and [0076], wherein a high-level block model may be generated of the circuit design).
Regarding Claim 8, Schultz further teaches wherein generating the block model includes parsing sources of the circuit design to determine the design topology and parsing connection attributes of the NoC to determine NoC configuration information (Schultz paragraph [0073], wherein the RTL source files and traffic specification are read to determine the block model and attributes of the NoC), and wherein the block model is generated based on the design topology and the NoC configuration information (Schultz paragraphs [0073] and [0076], wherein a high-level block model may be generated of the circuit design).
Regarding Claim 9, Schultz teaches a system comprising:
a memory device comprising instructions stored thereon (Schultz paragraph [0069], see system memory storing instructions);
a processing device (Schultz paragraph [0069], see CPU) coupled to the memory device and configured to execute the instructions, the instructions when executed cause the processing device to:
receive a circuit design (Schultz paragraphs [0071]-[0073], wherein a circuit design is received as source files, e.g. an RTL source, traffic specification, and constraints);
generate connections within a network-on-chip (NoC) by analyzing the circuit design to detect a first connection attribute, wherein the first connection attribute defines a first NoC master unit (NMU) and a first NoC slave unit (NSU) (Schultz paragraphs [0073], [0076], [0078] and [0083]-[0084], wherein the source files are analyzed and used to generate connections in a NoC, the traffic specification defining paths having connection attributes and which specify the NMUs and the NSUs to be connected); and
generate a first NoC configuration including the connections determined based on the first NMU and the first NSU (Schultz paragraphs [0077]-[0079], wherein the configuration of the NoC is generated and implemented including the paths).
Regarding Claim 10, Schultz further teaches wherein the processing device is further caused to analyze the circuit design to determine a first constraint of the first NMU, and wherein the first NoC configuration is further generated based on the first constraint (Schultz paragraphs [0073] and [0078], wherein the constraint file specifies constraints for the NoC including the NMUs, with the configuration of the NoC generated to meet the constraints).
Regarding Claim 11, Schultz further teaches wherein the processing device is further caused to analyze the circuit design to determine a second constraint of the first NSU, and wherein the first NoC configuration is further generated based on the second constraint (Schultz paragraphs [0073] and [0078], wherein the constraint file specifies constraints for the NoC including the NSUs, with the configuration of the NoC generated to meet the constraints).
Regarding Claim 12, Schultz further teaches wherein the first constraint is provided via a first constraint file associated with the circuit design, and analyzing the circuit design to determine the first constraint and the second constraint comprises analyzing the first constraint file (Schultz paragraph [0073], wherein the constraints are contained within the constraint files which are utilized to generate the configuration of the SoC).
Regarding Claim 13, Schultz further teaches wherein the first constraint and the second constraint define a connection between the first NMU and the first NSU (Schultz paragraph [0073], wherein the constraints include timing performance requirements which define the connection between components including the paths between the NMUs and the NSUs).
Regarding Claim 14, Schultz further teaches wherein the processing device is further caused to detect the first connection attribute within one or more of an attribute portion or comment portion of the circuit design (Schultz paragraphs [0073] and [0076], wherein the connection attributes are contained within the traffic specification, the traffic specification being an attribute portion of the circuit design).
Regarding Claim 15, Schultz further teaches wherein the processing device is further caused generate a block model based on the circuit design and the first NoC configuration determine a design topology of the circuit design (Schultz paragraphs [0073] and [0076], wherein a high-level block model may be generated of the circuit design).
Regarding Claim 16, Schultz further teaches wherein generating the block model includes parsing sources of the circuit design to determine the design topology and parsing connection parameters of the NoC to determine NoC configuration information (Schultz paragraph [0073], wherein the RTL source files and traffic specification are read to determine the block model and attributes of the NoC), and wherein the block model is generated based on the design topology and the NoC configuration information (Schultz paragraphs [0073] and [0076], wherein a high-level block model may be generated of the circuit design).
Regarding Claim 17, Schultz teaches a non-transitory computer readable medium comprising stored instructions (Schultz paragraph [0069], see system memory storing instructions), which when executed by a processing device, cause the processing device to:
receive a circuit design (Schultz paragraphs [0071]-[0073], wherein a circuit design is received as source files, e.g. an RTL source, traffic specification, and constraints);
generate connections within a network-on-chip (NoC) by analyzing the circuit design to detect a first connection attribute, wherein the first connection attribute defines a first NoC master unit (NMU) and a first NoC slave unit (NSU) (Schultz paragraphs [0073], [0076], [0078] and [0083]-[0084], wherein the source files are analyzed and used to generate connections in a NoC, the traffic specification defining paths having connection attributes and which specify the NMUs and the NSUs to be connected); and
generate a first NoC configuration including the connections determined based on the first NMU and the first NSU (Schultz paragraphs [0077]-[0079], wherein the configuration of the NoC is generated and implemented including the paths).
Regarding Claim 18, Schultz further teaches wherein the processing device is further caused to:
analyze the circuit design to determine a first constraint of the first NMU (Schultz paragraphs [0073] and [0078], wherein the constraint file specifies constraints for the NoC including the NMUs, with the configuration of the NoC generated to meet the constraints); and
analyze the circuit design to determine a second constraint of the first NSU (Schultz paragraphs [0073] and [0078], wherein the constraint file specifies constraints for the NoC including the NSUs, with the configuration of the NoC generated to meet the constraints), and wherein the first NoC configuration is further generated based on the first constraint and the second constraint (Schultz paragraphs [0073] and [0078], wherein the configuration of the NoC generated to meet the constraints).
Regarding Claim 19, Schultz further teaches wherein the processing device is further caused to detect the first connection attribute within one or more of an attribute portion or comment portion of the circuit design (Schultz paragraphs [0073] and [0076], wherein the connection attributes are contained within the traffic specification, the traffic specification being an attribute portion of the circuit design).
Regarding Claim 20, Schultz further teaches wherein the processing device is further caused to generate a block model based on the circuit design and the first NoC configuration determining a design topology of the circuit design (Schultz paragraphs [0073] and [0076], wherein a high-level block model may be generated of the circuit design), wherein generating the block model includes parsing sources of the circuit design to determine the design topology and parsing connection attributes of the NoC to determine NoC configuration information (Schultz paragraph [0073], wherein the RTL source files and traffic specification are read to determine the block model and attributes of the NoC), and wherein the block model is generated based on the design topology and the NoC configuration information (Schultz paragraphs [0073] and [0076], wherein a high-level block model may be generated of the circuit design).
Conclusion
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/ERIC D LEE/Primary Examiner, Art Unit 2851
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