Prosecution Insights
Last updated: April 19, 2026
Application No. 18/589,423

PROBER AND TEMPERATURE MEASUREMENT METHOD

Non-Final OA §102
Filed
Feb 28, 2024
Examiner
SHAH, NEEL D
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Seimitsu Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
531 granted / 611 resolved
+18.9% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
19 currently pending
Career history
630
Total Applications
across all art units

Statute-Specific Performance

§101
8.5%
-31.5% vs TC avg
§103
50.1%
+10.1% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 611 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority 2. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2023-059126, filed on 3/31/23. Information Disclosure Statement 3. The information disclosure statement (IDS) submitted on 2/28/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 5. Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Yamasaki et al. (US 2020/0209072). (“Yamasaki”). 6. Regarding claim 1, Yamasaki teaches A prober for performing an electric test of a wafer [Figures 1-9, a prober 1 for performing an electric test of a wafer is shown], the prober comprising: a wafer chuck configured to support the wafer [Figures 1-9, a wafer chuck 51 to support the wafer W is shown]; a conveyance device configured to transfer a probe card to the wafer chuck [Figures 1-9, a conveyance device 12/30 to transfer a probe card 80 to the wafer chuck 51 is shown]; and a conveyance controller configured to control an operation of the conveyance device [Figures 1-9, a conveyance controller to control an operation of the conveyance device 12/30 is taught], wherein the conveyance device is configured to support a temperature measurement jig when a temperature measurement of the wafer chuck is performed, the temperature measurement jig being able to be supported at a position where the probe card is supported when the probe card is conveyed, the temperature measurement jig having one or more temperature sensors [Figures 1-9, the conveyance device 12/30 supports a temperature measurement jig 90 when a temperature measurement of the wafer chuck 51 is performed, the temperature measurement jig being able to be supported at a position where the probe card 80 is supported, the temperature measurement jig 90 has one or more sensors 93], and the conveyance controller performs an operation control of the conveyance device for making the one or more temperature sensors contact a surface of the wafer chuck to be measured in a state that the conveyance device supports the temperature measurement jig [Figures 1-9, the conveyance controller performs an operation control of the conveyance device 12/30 to making temperature sensors 93 contact a surface of the wafer chuck 51, the conveyance device 12/30 supports the temperature measurement jig 90]. 7. Regarding claim 2, Yamasaki teaches wherein a measured data collecting device for collecting a temperature measurement data of the wafer chuck transmitted from the one or more temperature sensors is configured to be attached to the conveyance device [Figures 1-9, a measured data collecting device 90 collects temperature data]. 8. Regarding claim 3, Yamasaki teaches wherein the conveyance device is configured to support the temperature measurement jig by a tip of an arm extending outward from a main body, the measured data collecting device is configured to be electrically connected with each of the one or more temperature sensors using an electric wiring, and the electric wiring is configured to be supported by using the arm [Figures 1-9, the conveyance device 12/30 supports the temperature measurement jig 90 by a tip of an arm extending from a main body 13]. 9. Regarding claim 4, Yamasaki teaches wherein the one or more temperature sensors include a contactor with which the surface of the wafer chuck to be measured is in surface contact [Figures 1-9, see temperature sensors 93 contacting the surface of the wafer chuck 51]. 10. Regarding claim 5, Yamasaki teaches A temperature measurement method for measuring a temperature of a wafer chuck which is configured to support a wafer in a prober for performing an electric test of the wafer [Figures 1-9, a temperature measurement method for measuring a temperature of a wafer chuck 51 which is configured to support a wafer W in a prober 1 is taught], the method comprising the steps of: conveying a temperature measurement jig using a conveyance device configured to transfer a probe card to the wafer chuck, the temperature measurement jig being able to be supported at a position where the probe card is supported when the probe card is conveyed, the temperature measurement jig having one or more temperature sensors [Figures 1-9, a temperature measurement jig 90 is conveyed using a conveyance device 12/30 to transfer a probe card 80 to the wafer chuck 51, the temperature measurement jig is supported at a position where the probe card is supported, the temperature measurement jig has one or more temperature sensors 93]; and making the one or more temperature sensors contact a surface of the wafer chuck to be measured in a state that the conveyance device supports the temperature measurement jig [Figures 1-9, temperature sensors 93 contacts a surface of the wafer chuck 51 to be measured in a state that the conveyance device 12/30 supports the temperature measurement jig 90]. 11. Regarding claim 6, Yamasaki teaches wherein a temperature measurement data of the wafer chuck transmitted from the one or more temperature sensors is collected [Figures 1-9, a temperature measurement data of the wafer chuck 51 transmitted from temperature sensors 93 is collected]. 12. Regarding claim 7, Yamasaki teaches A prober for performing an electric test of a wafer [Figures 1-9, a prober 1 for performing an electric test of a wafer W is shown], the prober comprising: a wafer chuck configured to support the wafer [Figures 1-9, a wafer chuck 51 to support the wafer W is shown]; an alignment device configured to adjust a position of the wafer chuck [Figures 1-9, an alignment device 50/53 to adjust a position of the wafer chuck 51 is shown]; an alignment controller configured to control an operation of the alignment device [Figures 1-9, an alignment controller 50/53 controls an operation of the alignment device is taught; see P(0043, 0045-0048)]; and a head stage to which a probe card is attached when the electric test is performed [Figures 1-9, a head stage 40 to which a probe card 80 is attached is shown], wherein a temperature measurement jig is configured to be attached to the head stage when a temperature measurement of the wafer chuck is performed, the temperature measurement jig being able to be attached to the head stage at a position where the probe card is attached when the electric test is performed, the temperature measurement jig having one or more temperature sensors [Figures 1-9, a temperature measurement jig 90 is configured to be attached to the head stage 40, the temperature measurement jig is attached to the head stage at a position where the probe card 80 is attached when the test is performed, one or more temperature sensors 93 is shown], and the alignment controller is configured to control the operation of the alignment device for making the one or more temperature sensors contact a surface of the wafer chuck to be measured [Figures 1-9, the alignment controller 50/53 is configured to control the operation of the alignment device for making temperature sensors 93 contact a surface of the wafer chuck 51 to be measured]. 13. Regarding claim 8, Yamasaki teaches wherein a fixing member is provided for fixing the wafer chuck to the head stage [Figures 1-9, a fixing member 50 is shown]. 14. Regarding claim 9, Yamasaki teaches further comprising: a head stage moving mechanism configured to move the head stage between a temperature measurement position at which the head stage is arranged when measuring the temperature of the wafer chuck and a maintenance position at which the head stage is arranged when attaching the temperature measurement jig to the head stage [Figures 1-9, a temperature measurement jig 90 and a head stage 40 is shown]. 15. Regarding claim 10, Yamasaki teaches wherein the one or more temperature sensors include a contactor with which the surface of the wafer chuck to be measured is in surface contact [Figures 1-9, temperature sensors 93 contacts the surface of the wafer chuck 51]. 16. Regarding claim 11, Yamasaki teaches A temperature measurement method for measuring a temperature of a wafer chuck which is configured to support a wafer in a prober for performing an electric test of the wafer [Figures 1-9, a temperature measurement method for measuring a temperature of a wafer chuck 51 which is configured to support a wafer W in a prober 1 is taught], the method comprising the steps of: attaching a temperature measurement jig to a head stage at a position where a probe card is attached when the electric test is performed, the temperature measurement jig having one or more temperature sensors [Figures 1-9, a temperature measurement jig 90 is attached to a head stage 40 where a probe card 80 is attached, see temperature sensors 93], and making the one or more temperature sensors contact a surface of the wafer chuck to be measured [Figures 1-9, the temperature sensors 93 contact a surface of the wafer chuck 51 to be measured]. 17. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Nishida Tomoya (JP 2019050389, provided in the IDS). (“Nishida”). 18. Regarding claim 1, Nishida teaches A prober for performing an electric test of a wafer [Figures 1-18, a prober 10 for performing an electric test of a wafer is shown], the prober comprising: a wafer chuck configured to support the wafer [Figures 1-18, a wafer chuck 18 to support the wafer W is shown]; a conveyance device configured to transfer a probe card to the wafer chuck [Figures 1-18, a conveyance device 14/16 to transfer a probe card PC to the wafer chuck 18 is shown]; and a conveyance controller configured to control an operation of the conveyance device [Figures 1-18, a conveyance controller 14/16 to control an operation of the conveyance device is taught], wherein the conveyance device is configured to support a temperature measurement jig when a temperature measurement of the wafer chuck is performed, the temperature measurement jig being able to be supported at a position where the probe card is supported when the probe card is conveyed, the temperature measurement jig having one or more temperature sensors [Figures 1-18, the conveyance device 14/16 supports a temperature measurement jig 68 when a temperature measurement of the wafer chuck 18 is performed, the temperature measurement jig being able to be supported at a position where the probe card 80 is supported, the temperature measurement jig 68 has one or more sensors 68a, 68b, 68c], and the conveyance controller performs an operation control of the conveyance device for making the one or more temperature sensors contact a surface of the wafer chuck to be measured in a state that the conveyance device supports the temperature measurement jig [Figures 1-18, the conveyance controller performs an operation control of the conveyance device 14/16 to making temperature sensors 68a, 68b, 68c contact a surface of the wafer chuck 18, the conveyance device 14/16 supports the temperature measurement jig 68]. Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. OTA et al. (US 2024/0402021), Figures 1-15 teaches a temperature calibration system, comprising wafer carrying mechanism, wafer stage, wafer alignment, temperature sensors and so on. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEEL D SHAH whose telephone number is (571)270-3766. The examiner can normally be reached M-F: 9AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NEEL D SHAH/Primary Examiner, Art Unit 2858
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Prosecution Timeline

Feb 28, 2024
Application Filed
Mar 12, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+7.3%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 611 resolved cases by this examiner. Grant probability derived from career allow rate.

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