DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
Applicants’ arguments, dated 08/13/2026,with respect to claim(s) 1 and 16, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The previous rejection of claims 1 and 16 has been upheld. New claims 21 and 22 have been added. As to the Applicant’s argument on pages 10-14, the amended limitations of claims 1 and 16 “… and the inter substrate interconnect structure, wherein the encapsulation layer includes a different material from the dielectric layer.” are rejected under 35 USC § 103 as being unpatentable over Kuo et al. (US 20180151389) in view of Patil et al. (US 20220148952).
However, the reference Kuo does not cure the deficiencies of Liao regarding the allowable limitations of claims 9-11 and claim 20.
Claim Objections
Claims 11 and 12 are objected to because of the following informalities: The claims recite repetitive language “The package of The package of wherein the inner interconnect…”. In order to advance prosecution, it is assumed the Applicant meant, “The package of claim 9 wherein the inner interconnect…” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. All obviousness rationales stated below are rationales that would have been obvious prior to the earliest effective filing date of the application.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8, and 13-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (US 20180151389) herein referred to as Kuo in view of Patil et al. (US 20220148952) herein referred to as Patil.
As to claims 1 and 16, a package comprising: a first substrate and a method for fabricating package, comprising: providing;
an integrated device (Fig. 3, 101b, Kuo) coupled to the first substrate (Fig. 3, 106a + 104a +130, Kuo)
an inter substrate interconnect structure (Fig. 3, via structure 108 + 110 + 112, Kuo) coupled to the first substrate wherein
the inter substrate interconnect structure comprises:
an inner interconnect ([0037] conductive TIV 108, Kuo);
a dielectric layer coupled to the inner interconnect (Fig. 3, [0038] polyimide dielectric 110, Kuo), wherein
the dielectric layer (110, Kuo) laterally surrounds the inner interconnect (108, Kuo); and
an interconnect coupled to the dielectric layer (110, Kuo), wherein
the interconnect (Fig. 3, 112 + 114, Kuo) laterally surrounds the dielectric layer (110, Kuo) and the inner interconnect (108, Kuo), and wherein
the dielectric layer (110, Kuo) is located laterally between the inner interconnect (108, Kuo) and the interconnect (Fig. 3, 112 + 114, Kuo)
a second substrate (Fig. 3, via layer 106b, Kuo) coupled to the inter substrate interconnect structure (Fig. 3, via structure 108 + 110 + 112, Kuo); and
an encapsulation layer (Fig. 3, 114, which is not a ployimide, Kuo) coupled to the first substrate (Fig. 3 106a + 104a +130, Kuo)
the second substrate (106b, Kuo), and the inter substrate interconnect structure, wherein the encapsulation layer (114 , which is not a ployimide, Kuo) includes a different material from the dielectric layer (polyimide 110, Kuo)
Kuo does not appear to expressly disclose:
a first plurality of solder interconnects coupling an integrated device to the first substrate.
a second plurality of solder interconnects coupling an inter substrate interconnect structure to the first substrate.
a third plurality of solder interconnects coupling an inter substrate interconnect structure to the second substrate.
However, Patil teaches in [0023], Fig. 2 “The integrated device 205 is coupled to a second surface (e.g., top surface) of the second substrate 204 through a plurality of solder interconnects (254, Patil).” It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to couple an integrated device to the first substrate through a first plurality of solder interconnects such as is disclosed in the Patil device so as to enable a cost-effective, high-yield method to create reliable electrical, mechanical, and thermal connections.
Patil also teaches in [0022], Fig. 2 “A plurality of solder interconnects (244, Patil) may be used to couple the gradient interconnect structure 206 to the first substrate 202.” It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to couple an inter substrate interconnect structure to the first substrate through a second plurality of solder interconnects such as is disclosed in the Patil device so as to enable a cost-effective, high-yield method to create reliable electrical, mechanical, and thermal connections.
Patil also teaches in [0024], Fig. 2 “The plurality of interconnects 242 is coupled to the at least one interconnect 262 through the plurality of solder interconnects (264, Patil).” It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to couple an inter substrate interconnect structure to the second substrate through a third plurality of solder interconnects such as is disclosed in the Patil device so as to enable a cost-effective, high-yield method to create reliable electrical, mechanical, and thermal connections.
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As to claims 2 and 17, the Kuo/Patil combination discloses the elements of the package of claim 1 as discussed above and further discloses, and the method of claim 16 respectively, wherein
the second plurality of solder interconnects (244 of Annotated 2nd plurality of solder interconnect, Patil) comprises a first solder interconnect and a second solder interconnect wherein
the third plurality of solder interconnects (264 of Annotated 3rd plurality of solder interconnect, Patil) comprises a third solder interconnect and a fourth solder, wherein
the first solder interconnect (254 of combined Kuo/Patil) is coupled to the first substrate (Fig. 3 106a + 104a +130, Kuo)
and the inner interconnect ([0037] conductive TIV 108, Kuo) of the inter substrate interconnect structure (Fig. 3, via structure 108 + 110 + 112, Kuo), wherein
the second solder interconnect (254 of combined Kuo/ Patil) is coupled to the first substrate (Fig. 3 106a + 104a +130, Kuo) and the interconnect of the inter substrate interconnect structure (Fig. 3, via structure 108 + 110 + 112, Kuo), wherein
the third solder interconnect (244/264 of combined Kuo/ Patil) of the inter substrate interconnect structure (Fig. 3, via structure 108 + 110 + 112, Kuo), and wherein
the fourth solder interconnect (244/264 of combined Kuo / Patil) is coupled to the second substrate (Fig. 3, via layer 106b, Kuo) and the interconnect of the inter substrate interconnect structure (Fig. 3, via structure 108 + 110 + 112, Kuo).
As to claim 3, the Kuo /Patil combination discloses the elements of the package of claim 1, as discussed above and further discloses wherein
the inter substrate interconnect structure (Fig. 3, via structure 108 + 110 + 112, Kuo) comprises an inter substrate concentric interconnect structure (Fig 3, [0040] In some embodiments, the ground shielding layer 112 fully encircles the sides of the TIV 108).
As to claim 4, the Kuo /Patil combination discloses the elements of the package of claim 1, as discussed above and further discloses wherein
the inner interconnect (108, Kuo) comprises a wire or a pin (obvious).
The Kuo/Patil combination device does not appear to expressly disclose " the inner interconnect comprises a wire or a pin”. However, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, that in the semiconductor industry, the inner conductive core 108 of a semiconductor device is typically referred to as a bonding wire. The bonding wire or pin (obvious) connects the silicon chip (die) to the lead frame or package terminals, enabling electrical connectivity, creating a functioning device.
As to claim 5, the Kuo/Patil combination discloses the elements of the package of claim 1, as discussed above and further discloses wherein
the inner interconnect (108, Kuo) is configured to provide a first electrical path ([0037] “A through-insulator via (TIV) 108 extends through the insulating layer 114 and couples a first via 140a formed in the first via layer 106a of the first semiconductor package element 101a to a second via 140b formed in the first via layer 106b of the second semiconductor package element 101b. The TIV 108 includes a conductive material configured to transmit a signal from the first via 140a to the second via 140b.”) between the first substrate (Fig. 10, carrier substrate 102 + 104 + 106, Liao) and the second substrate (Fig. 13, dielectric layer 130, Liao).
As to claim 6, the Kuo/Patil combination discloses the elements of the package of claim 5, as discussed above and further discloses wherein
the interconnect (Fig. 3, 112 + 114, Kuo) is configured to provide a second electrical path between the first substrate (Fig. 3, 106a + 104a +130, Kuo) and the second substrate (Fig. 3, via layer 106b, Kuo).
As to claim 7, the Kuo/Patil combination discloses the elements of the package of claim 6, as discussed above and further discloses wherein
the first electrical path is configured as an electrical path for signal or power between the first substrate and the second ([0037] “A through-insulator via (TIV) 108 extends through the insulating layer 114 and couples a first via 140a formed in the first via layer 106a of the first semiconductor package element 101a to a second via 140b formed in the first via layer 106b of the second semiconductor package element 101b. The TIV 108 includes a conductive material configured to transmit a signal from the first via 140a to the second via 140b.” Kuo)
As to claim 8, the Kuo/Patil combination discloses the elements of the package of claim 7, as discussed above and further discloses wherein
the second electrical path is configured as an electrical path for ground between the first substrate and the second substrate ([0036] FIG. 3 illustrates a semiconductor package 100 including a ground shielded transmission path 102 coupling a first semiconductor package element 101a and a second semiconductor package element 101b, according to some embodiments.”)
As to claim 13, the Kuo/Patil combination discloses the elements of the package of claim 1, as discussed above
a second integrated device coupled to the second substrate.([0044] “The solder bumps 134 and/or the SMD contacts are configured to couple the semiconductor package 100 to one or more additional circuit elements, such as a circuit board, using surface-mount technology.”
As to claim 14, the Kuo/Patil combination discloses the elements of the package of claim 1, as discussed above and further discloses wherein
the interconnect of the inter substrate interconnect structure comprises a ring interconnect ([0040] “In some embodiments, the ground shielding layer 112 fully encircles the sides of the TIV 108.” And [0057]“plurality of coaxial connectors”)) that surrounds the inner interconnect.
As to claim 15, the Kuo/Patil combination discloses the elements of the package of claim 1, as discussed above and further discloses
a plurality of inter substrate interconnect structures ([0026] “FIG. 22 illustrates the partial semiconductor package of FIG. 21 having a plurality of conductive layers and vias coupling the first and second semiconductor dies to a connection pad…”, Kuo), wherein
the inter substrate interconnect structure is part of the plurality of inter substrate interconnect structures wherein the plurality of inter substrate interconnect structures are coupled to the first substrate through at least the second plurality of solder interconnects (244, Kuo/Patil), and wherein
the plurality of inter substrate interconnect structures are coupled to the second substrate through at least the third plurality of solder interconnects (264, Kuo/Patil).
As to claim 18, the Kuo/Patil combination discloses the elements of the method of claim 16, as discussed above and further discloses wherein
the inter substrate interconnect structure comprises an inter substrate concentric interconnect structure ([0057]“plurality of coaxial connectors”) wherein
the inner interconnect is configured to provide a first electrical path between the first substrate and the second substrate ([0037] “A through-insulator via (TIV) 108 extends through the insulating layer 114 and couples a first via 140a formed in the first via layer 106a of the first semiconductor package element 101a to a second via 140b formed in the first via layer 106b of the second semiconductor package element 101b”), and wherein
the interconnect is configured to provide a second electrical path between the first substrate and the second substrate ([0039] “In some embodiments, the ground shielded transmission path 102 includes a ground shielding layer 112 disposed over and/or around an outer surface of the insulating layer 110 and the TIV 108 and extending from the first semiconductor package element 101a to the second semiconductor package element 101b”)
As to claim 19, the Kuo/Patil combination discloses the elements of the method of claim 18, as discussed above and further discloses wherein
the first electrical path is configured as an electrical path for signal or power between the first substrate and the second substrate ([0037] “The TIV 108 includes a conductive material configured to transmit a signal from the first via 140a to the second via 140b.”) and wherein
the second electrical path is configured as an electrical path for ground between the first substrate and the second substrate. ([0039] “In some embodiments, the ground shielded transmission path 102 includes a ground shielding layer 112 disposed over and/or around an outer surface of the insulating layer 110 and the TIV 108 and extending from the first semiconductor package element 101a to the second semiconductor package element 101b”)
As to claim 21, the Kuo/Patil package of claim 1, wherein
the encapsulation layer (Fig. 3, insulating layer 114, not a polyimide, Kuo) includes a mold, a resin and/or an epoxy.
As to claim 22, the package of claim 21, wherein
the dielectric layer ([0038] 110, “The insulating layer 110 includes an insulating material, such as, for example, a polyimide material.”, Kuo) includes polyimide or silicon nitride.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (US 20180151389) herein referred to as Kuo in view of Patil et al. (US 20220148952 ) herein referred to as Patil and further in view of Liao, Wen-Shiang (US 20240021537) herein referred to as Liao.
As to claim 12, the Kuo/Patil combination discloses the elements of the package of claim 1, as discussed above but does not appear to explicitly disclose:
wherein “the inter substrate interconnect structure comprises a structure width of about 160-180 micrometers, wherein the inner interconnect comprises a width of about 35-45 micrometers, wherein the interconnect comprises an interconnect width of about 35-45 micrometers, and wherein a space between the inner interconnect and the interconnect is about 20-30 micrometers”
However Liao teaches the inter substrate interconnect structure (113: comprising concentric layers 120 + 121 + the inside portion of 128, Liao) The inter-substrate interconnect structure (ISIS) widths of layers must be optimized to balance electrical performance, thermal management, mechanical reliability, and manufacturing yield in advanced semiconductor packaging.
120: [0026] “each of the inner conductive cores 120 may have a width W1 that is in a range from 10 μm to 300 μm”, Liao)
121:[0031] “the outer conductive shielding layer 121) may be in a range from 10 μm to 500 μm.”
128: [0031] “the molding material 128 between each inner conductive core and its corresponding outer conductive shielding layer 121 may have a width W3 that is in a range from 0.5 μm to 200 μm”
comprises a structure width of about 160-180 micrometers , wherein
the inner interconnect (120, Liao [0026] “each of the inner conductive cores 120 may have a width W1 that is in a range from 10 μm to 300 μm”, Liao) comprises a width of about 35-45 micrometers, wherein
the interconnect comprises an interconnect width (121, Liao “the outer conductive shielding layer 121 may be in a range from 10 μm to 500 μm.”) of about 35-45 micrometers, and wherein
a space between the inner interconnect (120, Liao) and the interconnect (121, Liao) is about 20-30 micrometers (Space between 120 and 121 is space 128: 128 [0031] “the molding material 128 between each inner conductive core and its corresponding outer conductive shielding layer 121 may have a width W3 that is in a range from 0.5 μm to 200 μm, Liao)
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the width ranges of the layers of the inter-substrate interconnect structure, such as is disclosed in the Liao device so as to balance electrical performance, thermal management, mechanical reliability, and manufacture an optimal yield so as to use an industrially tested and accepted method of manufacturing.
Furthermore, the Applicant has not shown that: the inter substrate interconnect structure width of about 160-180 micrometers, the inner interconnect width of about 35-45 micrometers, the interconnect width of about 35-45 micrometers, and a space between the inner interconnect and the interconnect is about 20-30 micrometers are novel and would not have been found through routine experimentation. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable range involves only routine skill in the art. In re AIler, 105 USPQ 233. )
Allowable Subject Matter
Claim(s) 9 is allowable. Claims 9 contains allowable subject matter. Claim 20 is/are objected to as being dependent upon a rejected base claim 1, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 20 contains allowable subject matter.
The following is an examiner's statement of reasons of allowable subject matter: The prior art taken either singularly or in combination, fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. The closest prior art is Kuo et al. (US 20180151389) in view of Patil et al. (US 20220148952) in view of Liao (US 20240021537) which teach an analogous device.
As to claims 9 and 20, the Kuo/Patil/ Liao combination discloses the elements of the package of claim 1, as discussed above, but does not disclose the limitations of claim 9 as shown in the applicant’s Fig. 7, which illustrates the protection layer (704) as a separate metal protection layer on the side, coupled to and touching the interconnect (204). The Applicant’s protection layers (702) on the top of (202), and protection layer (706) on the bottom of (202), is taught by Liao. See Fig. 15 of Liao. Liao illustrates in Fig. 15, a 1st and 2nd protection layer (132) and (110) respectively, on the via (113), but Liao does not teach a separate protection layer on the side of the via(113) between the encapsulation layer (128) and the outside of (113). The allowable subject matter is as follows:
Claim 9 (a separate protection layer on the side of the via between the encapsulation layer and the outside of (the interconnect via structure (113) of Liao).
Claim 10 (first, second, and third protection layers, (not found in the Kuo device).
Claim 11 (first metal protection layer, the second metal protection layer and/or the third metal protection layer comprises nickel (Ni) and/or tin (Sn).
Nonetheless, claims (10-11), are allowable at least because they depend from allowable claim 9.
Conclusion
THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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