DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, claims 1-20, in the reply filed on 7/2/2026 is acknowledged.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the plurality of main electrodes of the first and second semiconductor element, and the first and second control electrode, as found in claim 7; and the one main electrode of the first semiconductor element and the other one main electrode of the second semiconductor element in the first wiring layer connected to a plurality of electrically isolated wirings as found in claim 10, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 1) It is unclear if “the first semiconductor element being thermally coupled to the first substrate and the first connection member between the first substrate and the first connection member, and the second semiconductor element being thermally coupled to the second substrate and the second connection member between the second substrate and the second connection member” requires the respective semiconductor elements themselves to be between their associated first and second substrates and connection members, or if it is sufficient for some element – not necessarily a semiconductor element – that thermally couples the first semiconductor element and the second semiconductor element to be between the substrates and connection members as claimed.
During examination, the quoted limitation was read as “the first semiconductor element is both thermally coupled to and between the first substrate and the first connection member and the second semiconductor element is both thermally coupled to and between the second substrate and the second connection member”.
Claims 2-19 inherit this rejection for indefiniteness.
(Re Claim 6) “the base material” alone lacks antecedence.
During examination, this was read as “the third base material”.
Claims 7-10 inherit this rejection for lack of antecedence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 11-14, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harada (US 2016/0027711).
(Re Claim 1) Harada teaches a semiconductor device, comprising: a first substrate (5; Fig. 2) including a first base material (ceramic; ¶37) that includes a first face (top face; Fig. 2) and a second face (bottom face; Fig. 2) opposite to the first face, and has thermal conductivity (due to metal of 1a; ¶37); a second substrate (4; Fig. 4) including a second base material (ceramic; ¶36) that includes a third face (bottom face; Fig. 4) facing the first face and a fourth face (top face; Fig. 4) opposite to the third face, and has thermal conductivity (due to metal of 1b and 1c; ¶36); a first semiconductor element (6b; Fig. 4) provided on the first face side; a second semiconductor element (6a; Fig. 4) provided on the third face side; and a third substrate (8; Fig. 4) that is provided between the first substrate and the second substrate, and includes a third base material (due to the insulating plate 8a made of e.g., glass epoxy; ¶35) including a fifth face (bottom face; Fig. 4) facing the first face and a sixth face (top face; Fig. 4) opposite to the fifth face, the third substrate including, a first connection member (12b; Fig. 4) that penetrates from the fifth face to the sixth face and has thermal conductivity (due to copper; ¶35), and a second connection member (12a; Fig. 4) that penetrates from the fifth face to the sixth face, is provided apart from the first connection member (Fig. 4), and has thermal conductivity (due to copper; ¶35), the first semiconductor element being thermally coupled to the first substrate and the first connection member between the first substrate and the first connection member (¶47), and the second semiconductor element being thermally coupled to the second substrate and the second connection member between the second substrate and the second connection member (¶46).
(Re Claim 2) Harada teaches the device according to claim 1, wherein each of the first connection member and the second connection member has a shape selected among a circular column (circular column; Fig. 15(a), ¶96), an elliptical column, a square column, and a truncated pyramid shape.
(Re Claim 5) Harada teaches the device according to claim 1, wherein each of the first connection member and the second connection member is electrically conductive (due to copper; ¶35), the first substrate includes a first wiring layer (1b; Fig. 4) on the first face, the second substrate includes a second wiring layer (1a; Fig. 4) on the third face, the first semiconductor element is electrically connected to the first wiring layer (¶41) on the first face side, and is electrically connected to the first connection member (¶41) on the fifth face side, and the second semiconductor element is electrically connected to the second wiring layer (¶40) on the third face side, and is electrically connected to the second connection member (¶40) on the sixth face side.
(Re Claim 11) Harada teaches the device according to claim 1, wherein the first connection member includes a first mounting face (region of 12b coextensive with the contact interface between 12b and the element 7 contacting 13b) that is thermally coupled to the first semiconductor element (¶47), and an area of the first mounting face in plan view is equal (at least equal to the area due to 100% coverage; ¶54) to or larger than an area of a main electrode (a bottom electrode; ¶41) on a face (top face) opposed to the first mounting face in the first semiconductor element.
(Re Claim 12) Harada teaches the device according to claim 11, wherein the second connection member includes a second mounting face (region of 12a coextensive with the contact interface between 12a and the element 7 contacting 13a) that is thermally coupled to the second semiconductor element (¶46), and an area of the second mounting face in plan view is equal to (at least equal to the area due to 100% coverage; ¶54) or larger than an area of a main electrode (a top electrode; ¶40) on a face (bottom face) opposed to the second mounting face in the second semiconductor element.
(Re Claim 13) Harada teaches the device according to claim 1, wherein the first connection member and the second connection member contain Cu (¶35) or Al.
(Re Claim 14) Harada teaches the device according to claim 1, wherein the first semiconductor element is one among an IGBT (¶39), a MOSFET, a GTO, and a diode, and the second semiconductor element is one among an IGBT (¶39), a MOSFET, a GTO, and a diode.
(Re Claim 16) Harada teaches the device according to claim 1, wherein the first base material contains any one among Al2O3 (alumina; ¶38), AlN, Cu, and Al, and the second base material contains any one among Al2O3 (alumina; ¶38), AlN, Cu, and Al.
(Re Claim 17) Harada teaches the device according to claim 1, further comprising: a casing (10; Fig. 8) that accommodates the first substrate, the second substrate, the third substrate, the first semiconductor element, and the second semiconductor element.
(Re Claim 18) Harada teaches the device according to claim 17, wherein the casing contains an insulating resin (sealing resin; ¶44).
(Re Claim 19) Harada teaches the device according to claim 1, wherein thermal conductivity of the third base material is lower than any of the thermal conductivity of the first connection member and the thermal conductivity of the second connection member (third base material has thermal conductivity on the order of 1/1000 of copper; ¶55).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2016/0027711) as applied to claim 1 above.
(Re Claim 3) Harada teaches the device according to claim 1, but has not been explicitly shown to teach the device further comprising: a first heat sink that is provided on the second face side and is thermally coupled to the first substrate.
Harada does teach adding a heat sink that is provided on the second face side and that is thermally coupled to the first substrate when the device is formed in a single-sided cooling configuration (¶¶44, 49).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to attach a first heat sink such that it is provided on the second face side and is thermally coupled to the first substrate after sealing the device such that the second face side is exposed (as shown in Fig. 2), as taught by Harada, to improve cooling efficiency (¶69).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2016/0027711) as applied to claim 3 above, and further in view of Rizza et al. (US 2017/0064808).
(Re Claim 4) Modified Harada teaches the device according to claim 3, but has not been explicitly shown to teach the device further comprising: a second heat sink that is provided on the fourth face side, and is thermally coupled to the second substrate.
Harada does describe adding a heat sink to the fourth face side such that it is thermally coupled to the second substrate if the device is formed such that the fourth face side is exposed (¶69).
Rizza teaches utilizing a first heat sink (108; Fig. 13) on a second face side (top of 29; Fig. 13) and second heat sink (31; Fig. 13) on a fourth face side (bottom of 23).
A PHOSITA would find it obvious to attach a second heat sink on the fourth face side that is thermally coupled to the second substrate, as taught by Rizza, to provide for additional heat dissipation from the second substrate (Harada: ¶44). See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Claim 6-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2016/0027711) as applied to claim 5 above, and further in view of Bayerer (US 2018/0174946), Takano et al. (US 2020/0027836), Wang et al. (US 2017/0012030), and Tsunoda (US 5,488,256).
(Re Claim 6) Harada teaches the device according to claim 5, wherein the third substrate includes a third wiring layer (13b; Fig. 2) provided on the fifth face, a fourth wiring layer (13a; Fig. 2) provided on the sixth face.
Harada has not been explicitly shown to teach a conductive layer provided in an inner layer of the base material, the third substrate further includes, a first circuit component that is provided on the fifth face side and is electrically connected to the third wiring layer, and a second circuit component that is provided on the sixth face side and is electrically connected to the fourth wiring layer, and the conductive layer is provided between the first circuit component and the second circuit component.
Bayerer teaches forming a third substrate (600; Fig. 15) including a third wiring layer (602; Fig. 15, ¶62) provided on a fifth face (bottom surface of 600; Fig. 15) and a fourth wiring layer (604; Fig. 15, ¶62) provided on a sixth face (top surface of 600; Fig. 15).
A PHOSITA would find it obvious to utilize the multi-layers of wiring layers of Bayerer (Bayerer: this includes layers 602, 604, 606, and 608; Fig. 15) for the wiring layers of the third substrate of Harada, to provide for even current spread (Bayerer: ¶62).
A PHOSITA would find it obvious to retain the first and second connection members and their associated connections as shown in Harada’s Fig. 2 to preserve their heat dissipating function.
Takano teaches forming circuit components outside of a casing (24; Fig. 1, ¶16), on a third substrate (31+33; Fig. 1), that may be used to control semiconductor elements (“The part to be mounted on the mounting surface 31a is not limited to the first semiconductor part 10 and the second semiconductor part 20, and may include a control IC that drives them” (¶37); Fig. 1).
A PHOSITA would find it obvious to form at least one circuit component on a side of the third substrate as taught by Takano, to control at least one of the semiconductor elements of modified Harada; and a PHOSITA would find it obvious to provide the at least one circuit component in an area of the third substrate with wiring dedicated to controlling a gate of a semiconductor element of modified Harada, as taught by Bayerer (Fig. 15), to provide for the shortest routing and prevent interference with control signals.
Wang teaches providing a first circuit component (left 53; Fig. 5B) and a second circuit component (right 53; Fig. 5B) on opposite faces of a third substrate (541+542+543; Fig. 5B).
A PHOSITA would find it obvious to provide the first circuit component on the fifth face and a second circuit component on the sixth face of modified Harada’s third substrate, such that they are oppositely placed across the third substrate, to reduce the parasitic inductance when switching the first and second semiconductor elements (Wang: ¶45).
Tsunoda teaches forming a conductive layer (94; Fig. 9B) in an inner layer of a base material (material of 61; Fig. 9B).
A PHOSITA would find it obvious to form a conductive layer in an inner layer (this layer is at the same level as the conductive layer) of the base material of modified Harada, such that the third substrate is divided as taught by Tsunoda (Fig. 9B), to reduce interference between the devices placed on either face of the third substrate (Tsunoda: col. 7 ln. 3-6). The conductive layer added to modified Harada extends to the edges of the third substrate as shown by Tsunoda.
(Re Claim 7) Modified Harada teaches the device according to claim 6, wherein the first semiconductor element includes a plurality of main electrodes (emitter and collector; ¶39), and a first control electrode (gate electrode; ¶39), the second semiconductor element includes a plurality of main electrodes (emitter and collector electrode; ¶39) and a second control electrode (gate electrode; ¶39).
Modified Harada has not been explicitly shown to teach the first circuit component is electrically connected to the first control electrode and the second circuit component is electrically connected to the second control electrode.
Wang teaches electrically connecting a first (left 53; Fig. 5B) and second circuit component (right 53; Fig. 5B) to a first control electrode (G1; ¶43) and a second control electrode (G2; ¶43).
Bayerer teaches forming a first semiconductor element (618; Fig. 15) with a first control (gate electrode; Fig. 15) electrode contacting a fifth face (bottom face) of a third substrate (600; Fig. 15) and a second semiconductor element (620; Fig. 15) with a second control electrode (gate electrode; Fig. 15) contacting a sixth face (top face) of the third substrate.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious it obvious to route the control signals from the first and second circuit components of modified Harada, such that the first circuit component is electrically connected to the first control electrode and the second circuit component is electrically connected to the second control electrode, as taught by Wang, to allow for the semiconductor elements of modified Harada to be switched on and off.
Furthermore, a PHOSITA would find it obvious to route those same control signals through the third and fourth wiring layers of the third substrate, to respective first and second control electrodes contacting respectively the fifth and sixth face, as taught by Bayerer, to provide for shorter trace length and to have even current spreading (Bayerer: ¶62).
(Re Claim 9) Modified Harada teaches the device according to claim 7, but has not been explicitly shown to teach one main electrode of the first semiconductor element is electrically connected to the first wiring layer, another one main electrode of the first semiconductor element is electrically connected to the first connection member, one main electrode of the second semiconductor element is electrically connected to the second wiring layer, and another one main electrode of the second semiconductor element is electrically connected to the second connection member.
Bayerer teaches forming a first semiconductor element with one main electrode on a one side (collector terminal is disposed at the backside; ¶34), and both another one main electrode (emitter terminal is disposed at the frontside; ¶34) and a control electrode (gate terminal is disposed at the frontside; ¶34) on another side.
A PHOSITA would find it obvious to form one main electrode of the first and second semiconductor element such that it is on a side opposite to another respective one main electrode and first and second control electrodes of the first and second semiconductor elements, as a configuration with one main electrode on one side and another main electrode on another side allows for current to flow vertically through the semiconductor element (Bayerer: ¶34). See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004). Furthermore, forming the one main electrode as a collector terminal and another one main electrode as the emitter terminal, where the emitter terminals contact a third substrate as taught by Bayerer, allows for the third substrate of modified Harada to have even current spread, due to the different connections for the emitter and gate terminals.
Therefore, modified Harada teaches one main electrode (bottom collector electrode; Harada: ¶41) of the first semiconductor element is electrically connected to the first wiring layer (Harada: ¶41), another one main electrode (top emitter electrode; Harada: ¶41 of the first semiconductor element is electrically connected to the first connection member (Harada: ¶41), one main electrode (top collector electrode; Harada: ¶40) of the second semiconductor element is electrically connected to the second wiring layer (Harada: ¶40), and another one main electrode (bottom emitter electrode; Harada: ¶40) of the second semiconductor element is electrically connected to the second connection member (Harada: ¶40).
(Re Claim 10) Modified Harada teaches the device according to claim 9, wherein in the first wiring layer, the one main electrode of the first semiconductor element and the other one main electrode of the second semiconductor element are connected to a plurality of electrically isolated wirings (respectively electrically connected to 1b and 1c, which are electrically isolated; Fig. 2; ¶68 describes an alternative embodiment that causes 1b and 1c to no longer be electrically separated, demonstrating that 1b and 1c of Fig. 2 are electrically separated).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2016/0027711), Bayerer (US 2018/0174946), Takano et al. (US 2020/0027836), Wang et al. (US 2017/0012030), and Tsunoda (US 5,488,256), as applied to claim 7 above, and further in view of Hong et al. (US 2021/0175184).
(Re Claim 8) Modified Harada teaches the device according to claim 7, wherein the third wiring layer has a first wiring (Bayerer: 602 for DC power; Fig. 15) and a second wiring (Bayerer: 602 for control electrode connections, i.e., the gates; Fig. 15); and the fourth wiring layer has a third wiring (Bayerer: 604 for DC power; Fig. 15) and a fourth wiring (Bayerer: 604 for control electrode connections, i.e., the gates; Fig. 15).
Modified Harada has not been explicitly shown to teach the third wiring layer includes a first wiring having a first thickness, and a second wiring having a second thickness smaller than the first thickness, the fourth wiring layer includes a third wiring having a third thickness, and a fourth wiring having a fourth thickness smaller than the third thickness, the second wiring electrically connects the first circuit component and the first control electrode, and the fourth wiring electrically connects the second circuit component and the second control electrode.
Hong teaches that a wiring layer (20; Fig. 6A) used for sending signals from a control electrode to a semiconductor element used for switching (¶63) is thinner (¶67) than the wiring layer (16; Fig. 6A) used for carrying current from the semiconductor element used for switching.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the first wiring layer with a first thickness, and a second wiring layer with a second thickness smaller than the first thickness, as thicker wiring layers are more expensive (Hong: ¶70) but can handle larger currents, and wiring only carrying a control signal does not need to handle the same current sizes, allowing for overall costs to be reduced while preserving device function.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2016/0027711), as applied to claim 14 above, and further in view of Takano et al. (US 2020/0027836).
(Re Claim 15) Harada teaches the device according to claim 14, but has not been explicitly shown to teach the first semiconductor element contains any one among Si, SiC, and GaN, and the second semiconductor element contains any one among Si, SiC, and GaN.
Takano teaches power transistors including a bipolar transistor, MOSFET, and IGBT are formed of Si, SiC, or GaN (¶48).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the semiconductor elements from at least one of Si, SiC, or GaN, as taught by Takano, as these materials are known in the art as having properties suitable for forming a power device such as an IGBT. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2016/0027711) as applied to claim 19 above, and further in view of Arens et al. (US 2015/0092376).
(Re Claim 20) Harada teaches the device according to claim 19, but has not been explicitly shown to teach the device wherein the third base material contains glass fiber.
However, Harada does teach that the third base material is glass epoxy (¶35).
Arens teaches that a common material used for a third base material of a third substrate (10; 1A) is glass fiber (¶20).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the glass fiber of Arens as the third base material of Harada, as glass fiber is a conventional material in the art when a third substrate such as Harada’s is formed from an insulating material (Arens: ¶20). See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ito et al. (US 2023/0145182) teaches placing P and N terminals on opposite sides of a third substrate (511; Fig. 9) to reduce inductance (¶107).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights