DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s reply to restriction/election requirement dated July 6th, 2026, is acknowledged. More specifically, Examiner acknowledges Applicant’s election of Species I without traverse, and that Applicant has amended, canceled, and added claims such that Species II and III are no longer pertinent. Therefore, the restriction/election requirement is made FINAL.
Status of Claims
Pursuant to Applicant’s reply to restriction/election requirement dated July 6th, 2026, Claims 1-13 and 16-22 are pending the within examination. Claims 14-15 are hereby cancelled.
Information Disclosure Statement
No information disclosure statement (IDS) has been provided by Applicant.
Specification
The abstract is objected to for failing to be in narrative form. Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. See MPEP § 608.01(b).
The specification is objected to for failing to provide a Brief Summary of the Invention sub-section in the disclosure. Pursuant to MPEP § 608.01(d) and 37 C.F.R. 1.73, the Specification is to include a Summary of Invention section as cited below. Appropriate correction is required.
“(h) BRIEF SUMMARY OF THE INVENTION: See MPEP § 608.01(d). A brief summary or general statement of the invention as set forth in 37 CFR 1.73. The summary is separate and distinct from the abstract and is directed toward the invention rather than the disclosure as a whole. The summary may point out the advantages of the invention or how it solves problems previously existent in the prior art (and preferably indicated in the Background of the Invention). In chemical cases it should point out in general terms the utility of the invention. If possible, the nature and gist of the invention or the inventive concept should be set forth. Objects of the invention should be treated briefly and only to the extent that they contribute to an understanding of the invention.”
The disclosure is objected to because of the following informalities:
(a) [0001], a period (‘,’) is missing in line 4, after “conductive elements” and before “Therefore”;
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, et al. (US 20190123189 A1; hereinafter referred to as Chen).
Regarding Claim 12, Chen discloses a method for manufacturing a semiconductor structure, comprising:
forming a patterned structure including an interfacial layer (interfacial layer (IL) 316, Fig. 4D) and two dielectric spacers at two opposite sides of the interfacial layer (spacers 322, Fig. 4D), a first surface of the interfacial layer and two second surfaces of the two dielectric spacers being arranged to border a cavity (gate trench 312, Fig. 4D), the first surface being formed with first functional groups ([0036]), the two second surfaces being formed with second functional groups that are different from the first functional groups ([0029]);
selectively forming two metal oxide layers respectively on the two second surfaces of the two dielectric spacers while leaving the first surface of the interfacial layer exposed from the two metal oxide layers, the two metal oxide layers being formed with third functional groups that are different from the first functional groups and the second functional groups (spacer 320, [0029], Fig. 3H);
applying precursor molecules to the cavity, the precursor molecules having an affinity to the third functional groups which is higher than an affinity to the first functional groups so that two self-assembled monolayers are respectively and selectively formed on the two metal oxide layers while leaving the first surface of the interfacial layer exposed from the two self-assembled monolayers (barrier layer 314, [0035], Fig. I); and
after selectively forming the two self-assembled monolayers, selectively forming a gate dielectric layer on the first surface of the interfacial layer while leaving the two self-assembled monolayers exposed from the gate dielectric layer (gate dielectric layer 318, [0037], Fig. 3J).
Regarding Claim 16, Chen discloses the method as claimed in claim 12, wherein
each of the precursor molecules has a head group and a tail group opposite to the head group, the head group having an affinity to the two metal oxide layers which is higher than an affinity to the first functional groups, the tail group being different from the first functional groups ([0035]), and
a dielectric precursor for forming the gate dielectric layer has an affinity to the first functional groups which is higher than an affinity to the tail group of each of the precursor molecules ([0037]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4, 6-11, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, et al. (US 20190123189 A1; hereinafter referred to as Chen) and further in view of Leal Cervantes, et al. (US 20220275501 A1; hereinafter referred to as Leal).
Regarding Claim 1, Chen discloses a method for manufacturing a semiconductor structure, comprising:
forming a patterned structure including an interfacial layer (interfacial layer (IL) 316, [0036], Fig. 4D) and two dielectric spacers respectively disposed at two opposite sides of the interfacial layer (spacer 322, [0029], Fig. 4D), a first surface of the interfacial layer and two second surfaces of the two dielectric spacers being arranged to border a cavity (gate trench 312, Fig. 4D; the interfacial layer has a top surface bordering the gate trench), the first surface being formed with first functional groups ([0036]), the two second surfaces being formed with second functional groups that are different from the first functional groups ([0029]);
selectively forming two second self-assembled monolayers respectively on the two dummy layers while leaving the first surface of the interfacial layer exposed from the two second self-assembled monolayers (barrier layers 314, [0035], Fig. 3I); and
after selectively forming the two second self-assembled monolayers, selectively forming a gate dielectric layer on the first surface of the interfacial layer while leaving the two second self-assembled monolayers exposed from the gate dielectric layer (gate dielectric layer 318, [0037], Fig. 3J).
Chen fails to disclose selectively forming a first self-assembled monolayer on the first surface of the interfacial layer while leaving the two second surfaces of the two dielectric spacers exposed from the first self-assembled monolayer; after selectively forming the first self-assembled monolayer, selectively forming two dummy layers respectively on the two second surfaces of the two dielectric spacers while leaving the first self-assembled monolayer exposed from the two dummy layers, the two dummy layers being made of a material different from a material of the two dielectric spacers; after selectively forming the two dummy layers, removing the first self-assembled monolayer to expose the first surface of the interfacial layer.
However, in analogous art, Leal discloses selectively forming a first self-assembled monolayer on the first surface while leaving the two second surfaces of the two dielectric spacers exposed from the first self-assembled monolayer (Leal: blocking layer 230, [0067], Fig. 2);
after selectively forming the first self-assembled monolayer, selectively forming two dummy layers respectively on the two second surfaces while leaving the first self-assembled monolayer exposed from the two dummy layers (first film 240, [0068], Fig. 2), the two dummy layers being made of a material different from a material of the two dielectric spacers (Leal: [0067-0068]);
after selectively forming the two dummy layers, removing the first self-assembled monolayer to expose the first surface (Leal: operation 280, [0069], Fig. 2);
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method of forming a gate dielectric layer as disclosed by Chen such that a first self-assembled monolayer and subsequent dummy layers are formed prior to the formation the second self-assembled monolayers as disclosed by Leal. One would be motivated to do so in order to inhibit the nucleation and growth of the spacers on the first surface during selective deposition methods (Leal: [0007]).
Regarding Claim 2, Chen/Leal discloses the method as claimed in claim 1, further comprising, after selectively forming the gate dielectric layer, removing the two second self-assembled monolayers and the two dummy layers to expose the two second surfaces of the two dielectric spacers (Chen: [0039], Fig. 3K).
Regarding Claim 4, Chen/Leal discloses the method as claimed in claim 1, wherein the first self-assembled monolayer is formed by applying first precursor molecules into the cavity (Leal: blocking compound, [0038]), each of the first precursor molecules having a first head group and a first tail group opposite to the first head group, the first head group having an affinity to the first functional groups which is higher than an affinity to the second functional groups, the first tail group being different from the second functional groups (Leal: [0038-0043]).
Regarding Claim 6, Chen/Leal discloses the method as claimed in claim 4, wherein the first head group includes ─SiH2NH2, ─Si(CH3)2NH2, ─Si(CH3)2N(CH3)2, or ─SiR3, where R is selected from F, Cl, Br, CH3, OCH3, or OC2H5 (Leal: [0038-0042]).
Regarding Claim 7, Chen/Leal discloses the method as claimed in claim 4, wherein
the first self-assembled monolayer is formed with the first tail group (Leal: [0038]), and
a material precursor for forming the two dummy layers has an affinity to the second functional groups which is higher than an affinity to the first tail group (Leal: [0057]).
Regarding Claim 8, Chen/Leal discloses the method as claimed in claim 7, wherein the first tail group is
a linear alkyl group of CH3(CH2)p─, wherein p is an integer ranging from 0 to 20; or
a linear halo-substituted alkyl group of CA3(CA2)n(CH2)m─, wherein A is selected from F, Cl, or Br, n is an integer ranging from 0 to 10, and m is an integer ranging from 0 to 10 (Leal: [0040]; provides for a linear alkyl group).
Regarding Claim 9, Chen/Leal discloses the method as claimed in claim 1, wherein the two second self-assembled monolayers are formed by applying second precursor molecules into the cavity, each of the second precursor molecules having a second head group and a second tail group opposite to the second head group, the second head group having an affinity to the two dummy layers which is higher than an affinity to the first functional groups, the second tail group being different from the first functional groups (Chen: [0035]).
Regarding Claim 10, Chen/Leal discloses the method as claimed in claim 9, wherein the second head group includes ─PO(OH)2 (Chen: [0035]).
Regarding Claim 11, Chen/Leal discloses the method as claimed in claim 9, wherein the second tail group is
a linear alkyl group of CH3(CH2)q─, wherein q is an integer ranging from 0 to 20;
a linear halo-substituted alkyl group of CE3(CE2)r(CH2)s─, wherein E is selected from F, Cl, or Br, r is an integer ranging from 0 to 10, and s is an integer ranging from 0 to 10; or
a group of G─O─(CH2)t─, where G is an aryl radical or a halo-substituted aryl radical, and t is an integer ranging from 0 to 10 (Leal: [0040]; discloses a linear alkyl group).
Regarding Claim 19, Chen discloses a method for manufacturing a semiconductor structure, comprising:
forming a patterned structure having a first surface formed with first functional groups (interfacial layer (IL) 316, [0036], Fig. 4D) and a second surface formed with second functional groups that are different from the first functional groups (spacer 322, [0029], Fig. 4D);
applying second precursor molecules to the first surface and the dummy layer, the second precursor molecules having an affinity to the third functional groups which is higher than an affinity to the first functional groups so that a second self-assembled monolayer is selectively formed on the dummy layer while leaving the first surface exposed from the second self- assembled monolayer (barrier layers 314, [0035], Fig. 3I); and
after selectively forming the second self-assembled monolayer, selectively forming a dielectric layer on the first surface while leaving the second self-assembled monolayer exposed from the dielectric layer (gate dielectric layer 318, [0037], Fig. 3J).
Chen fails to disclose applying first precursor molecules to the first surface and the second surface, the first precursor molecules having an affinity to the first functional groups which is higher than an affinity to the second functional groups so that a first self-assembled monolayer is selectively formed on the first surface while leaving the second surface exposed from the first self-assembled monolayer; after selectively forming the first self-assembled monolayer, selectively forming a dummy layer on the second surface while leaving the first self-assembled monolayer exposed from the dummy layer, the dummy layer being formed with third functional groups that are different from the first functional groups and the second functional groups; after selectively forming the dummy layer, removing the first self-assembled monolayer to expose the first surface.
However, in analogous art, Leal discloses:
applying first precursor molecules to the first surface and the second surface, the first precursor molecules having an affinity to the first functional groups which is higher than an affinity to the second functional groups so that a first self-assembled monolayer is selectively formed on the first surface while leaving the second surface exposed from the first self-assembled monolayer (Leal: blocking layer 230, [0067], Fig. 2);
after selectively forming the first self-assembled monolayer, selectively forming a dummy layer on the second surface while leaving the first self-assembled monolayer exposed from the dummy layer (Leal: first film 240, [0068], Fig. 2), the dummy layer being formed with third functional groups that are different from the first functional groups and the second functional groups (Leal: [0067-0068);
after selectively forming the dummy layer, removing the first self-assembled monolayer to expose the first surface (Leal: operation 280, [0069], Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method of forming a gate dielectric layer as disclosed by Chen such that a first self-assembled monolayer and subsequent dummy layers are formed prior to the formation the second self-assembled monolayers as disclosed by Leal. One would be motivated to do so in order to inhibit the nucleation and growth of the spacers on the first surface during selective deposition methods (Leal: [0007]).
Claim(s) 5 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Leal as applied to claims 1-2, 4, 6-11, and 19 above, and further in view of Kao, et al. (US 20220246478 A1; hereinafter referred to as Kao).
Regarding Claim 5, Chen/Leal discloses the method as claimed in claim 4.
The combination of Chen/Leal fails to explicitly disclose wherein the first functional groups include Si-OH groups, the second functional groups include Si-NHx, where x is 1 or 2, and the two dummy layers include metal oxide and are formed with M-OH groups, where M is metal.
However, in analogous art, Kao discloses first functional groups including Si-OH groups ([0024], Fig. 12), second functional groups including Si-NHx, where x is 1 or 2 ([0025], Fig. 12), and the two dummy layers include metal oxide and are formed with M-OH groups, where M is metal ([0024]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first and second functional groups and the dummy layers of Chen/Leal with the disclosed arrangements of Kao. One would be motivated to use these materials in order to increase manufacturing efficiency of the self-assembled monolayers which, in turns, leads to increased device performance due to the reduction of parasitic capacitance in the surrounding gate layers.
Regarding Claim 21, Chen/Leal/Kao discloses the method as claimed in claim 5, wherein the two dummy layers include aluminum oxide, titanium oxide, or a combination thereof (Kao: [0024]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claims 12 and 16 above, and further in view of Huang, et al. (US 20210082802 A1; hereinafter referred to as Huang).
Regarding Claim 13, Chen discloses the method as claimed in claim 12.
Chen fails to explicitly disclose wherein the first functional groups include hydroxyl groups, and the second functional groups include amino groups of ─NH2.
However, in analogous art, Huang discloses the first functional groups include hydroxyl groups (Huang: [0063]) and the second functional groups include amino groups of -NH2 (Huang: [0064]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the functional groups as disclosed by Chen with the functional groups of Huang. It would have been obvious as it would have been obvious to try, pursuant to MPEP 2143(I)(E). At the time of the invention, there had been a recognized problem or need in the art, as it is explained in Huang that the technology is pursuing higher device density, which can lead to increased parasitic capacitance. It is further provided in Huang that there is a finite number of identified and predictable potential solutions (said extensive potential materials are listed in [0063] of Huang). As such, one of ordinary skill in the art could have pursued these known materials solutions with a reasonable expectation of success. Therefore, a prima facie case of obviousness can be made.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claims 12 and 16 above, and further in view of Leal Cervantes, et al. (US 20220275501 A1; hereinafter referred to as Leal).
Regarding Claim 17, Chen discloses the method as claimed in claim 16.
Chen fails to explicitly disclose wherein the head group is ─PO(OH)2, and the tail group is a linear alkyl group of CH3(CH2)q─, wherein q is an integer ranging from 0 to 20; a linear halo-substituted alkyl group of CE3(CE2)r(CH2)s─, wherein E is selected from F, Cl, or Br, r is an integer ranging from 0 to 10, and s is an integer ranging from 0 to 10; or a group of G─O─(CH2)t─, where G is an aryl radical or a halo-substituted aryl radical, and t is an integer ranging from 0 to 10.
However, in analogous art, Leal discloses wherein:
the head group is ─PO(OH)2 (Leal: [0040]), and
the tail group is a linear alkyl group of CH3(CH2)q─, wherein q is an integer ranging from 0 to 20; a linear halo-substituted alkyl group of CE3(CE2)r(CH2)s─, wherein E is selected from F, Cl, or Br, r is an integer ranging from 0 to 10, and s is an integer ranging from 0 to 10; or a group of G─O─(CH2)t─, where G is an aryl radical or a halo-substituted aryl radical, and t is an integer ranging from 0 to 10 (Leal: [0040-0042]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the head and tail groups of Chen with the head and tail groups of Leal. One would be motivated to do so because the SAM composition of Leal can inhibit excess growth of along the first surface in order to more efficiently form a gate dielectric layer without parasitic capacitance with the spacers.
Allowable Subject Matter
Claims 3, 18, 20, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding Claim 3, Chen/Leal discloses the method as claimed in claim 1.
Neither Chen/Leal, nor any other prior art of record alone or in combination, discloses the method further comprising, before selectively forming the first self-assembled monolayer, performing a pretreatment process on the two dielectric spacers such that the second functional groups formed on the two second surfaces of the two dielectric spacers are exposed. While Leal does disclose a pretreatment process of the first self-assembled monolayer, Leal, nor any other prior art, explicitly or implicitly states pretreating the two dielectric spacer walls.
Regarding Claim 18, Chen/Leal discloses the method as claimed in claim 17.
Neither Chen/Leal, nor any other prior art of record alone or in combination, discloses wherein G is fluoro-substituted phenyl. It is known in the art to use phenyl as part of the device; however, fluoro-substituted phenyl is not apparent in the prior art of record.
Regarding Claim 20, Chen/Leal discloses the method as claimed in claim 19.
As stated in the rejection for Claim 5 above, Kao discloses wherein first functional groups including Si-OH groups (Kao: [0024], Fig. 12), second functional groups including Si-NHx, where x is 1 or 2 (Kao: [0025], Fig. 12), and the two dummy layers include metal oxide and are formed with M-OH groups, where M is metal (Kao: [0024]).
Additionally, Huang discloses the first precursor molecules include hexamethyldisilazane, (dimethylamino)trimethylsilane, octadecyltrichlorosilane, or combinations thereof (Huang: [0064]), and
the second precursor molecules include dodecylphosphonic acid, octylphosphonic acid, 12-pentafluorophenoxydodecylphosphonic acid, 1H,1H,2H,2H-perfluorododecyl phosphonic acid, octadecylphosphonic acid, or combinations thereof (Huang: [0064]).
However, the combination of Chen/Leal/Kao/Huang fails to explicitly disclose before applying the first precursor molecules, performing a pretreatment process on the second surface such that the second functional groups formed on the second surface are exposed. As stated above, no other prior art of record, alone or in combination, can render obvious the added limitation of applying a pretreatment process on the second surface.
Regarding Claim 22, Chen/Huang discloses the method as claimed in claim 13.
Neither Chen/Huang, nor any other prior art of record alone or in combination, disclose the method further comprising: after forming the patterned structure, performing a pretreatment process on the two dielectric spacers such that the second functional groups formed on the two second surfaces of the two dielectric spacers are exposed; after the pretreatment process and before selectively forming the two metal oxide layers, converting the first functional groups on the first surface of the interfacial layer to a linear alkyl group or a linear halo-substituted alkyl group, such that the first surface of the interfacial layer is passivated by the linear alkyl group or the linear halo-substituted alkyl group during selectively forming the two metal oxide layers; and after selectively forming the two metal oxide layers, performing an ashing process using an oxygen plasma to convert the linear alkyl group or the linear halo-substituted alkyl group on the first surface back to the first functional groups. As stated above, no other prior art of record can render obvious the added limitation of applying a pretreatment process on the second surface.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Huang, et al. (US 20160372565 A1); discloses an analogous SAM method for metal gates
(b) Oh, et al. (US 20220136106 A1); discloses advanced precursors for selective atomic layer deposition using self-assembled monolayers;
(c) Nguyen, et al. (US 11171054 B2); discloses selective deposition with SAM for fully aligned via;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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