Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 13-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/11/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US20240038698A1).
Regarding claim 21, Lin teaches a lead frame, comprising:
a conductive terminal (Figs. 1, 2B seed and transition layer 40/42); and
a nanotwin plated layer on an outer surface of the conductive terminal (Figs. 1, 2B conductive pads 200 disposed on transition layer 42 and par. 49 teaches that “the conductive pad 200 is a [nanotwinned]-Cu pad”).
Regarding claim 22, Lin discloses the lead frame of claim 21,
wherein the conductive terminal includes copper (Lin par. 52 teaches that “the transition layer 42 includes Cu”), and the nanotwin plated layer includes copper (Lin par. 49 teaches that “the conductive pad 200 is a [nanotwinned]-Cu pad”).
Regarding claim 23, Lin discloses the lead frame of claim 21,
wherein the nanotwin plated layer includes a first portion, a second portion, and a twin boundary between the first and second portions in which crystal lattices on each side of the twin boundary are linked by mirrored symmetry (Lin par. 29 teaches that “[t]he term ‘nanotwinned’ refers to two crystals [or two portions of a crystal] are formed mirrored across a common crystallographic plane” and so conductive pad 200 contains a first portion, a second portion, and a twin boundary between the portions in which there is a mirror symmetry as Lin teaches the conductive pad being nanotwinned).
Regarding claim 24, Lin discloses the lead frame of claim 21,
wherein the nanotwin plated layer completely covers an outer surface of the conductive terminal (Lin fig. 2B conductive pad 200 completely covers transition layer 42 within the encapsulant 60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US20240038698A1) in view of Cheah et al. (US6040626A, hereinafter Cheah).
Regarding claim 1, Lin teaches an electronic device, comprising:
a package structure (Fig. 1 encapsulant 60);
a conductive terminal (Figs. 1, 2B seed and transition layer 40/42) having a nanotwin plated layer (Figs. 1, 2B conductive pads 200 disposed on transition layer 42 and par. 49 teaches that “the conductive pad 200 is a [nanotwinned]-Cu pad”);
a semiconductor die in the package structure (Fig. 1 substrate 100 in encapsulant 60); and
a bond wire enclosed by the package structure and having a first end and a second end (Fig. 1 conductive wires 300 enclosed by encapsulant 60), the first end connected to the semiconductor die by a first bond, and the second end connected to the nanotwin plated layer by a second bond (Fig. 1 conductive wires 300 have first ends connected to substrate 100 by a first bond and second ends connected to conductive pad 200 by a second bond).
Lin does not appear to teach
a conductive terminal exposed outside the package structure.
Cheah teaches
a conductive terminal exposed outside the package structure (Fig. 2 terminal 12b electrically connected to semiconductor die 16 through bond wire 24 and has external portion exposed outside housing 22).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Cheah because the extension of the terminal outside the housing allows for external control of the semiconductor device.
Regarding claim 2, the combination of Lin and Cheah teaches the electronic device of claim 1,
wherein the conductive terminal includes copper (Lin par. 52 teaches that “the transition layer 42 includes Cu”), and the nanotwin plated layer includes copper (Lin par. 49 teaches that “the conductive pad 200 is a [nanotwinned]-Cu pad”).
Regarding claim 3, the combination of Lin and Cheah teaches the electronic device of claim 2,
wherein the second bond is a stich bond (While Lin fig. 2B teaches ball bond 310 disposed on conductive pad 200, in par. 33 Lin teaches that “[i]n some arrangements, the stitch bond 320 is electrically connected to the conductive pad” and so it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a stitch bond in the combination of Lin and Cheah because as Lin explicitly teaches it as an alternative).
Regarding claim 4, the combination of Lin and Cheah teaches the electronic device of claim 3,
wherein the nanotwin plated layer includes a first portion, a second portion, and a twin boundary between the first and second portions in which crystal lattices on each side of the twin boundary are linked by mirrored symmetry (Lin par. 29 teaches that “[t]he term ‘nanotwinned’ refers to two crystals [or two portions of a crystal] are formed mirrored across a common crystallographic plane” and so conductive pad 200 contains a first portion, a second portion, and a twin boundary between the portions in which there is a mirror symmetry as Lin teaches the conductive pad being nanotwinned).
Regarding claim 5, the combination of Lin and Cheah teaches the electronic device of claim 1,
wherein the second bond is a stich bond (While Lin fig. 2B teaches ball bond 310 disposed on conductive pad 200, in par. 33 Lin teaches that “[i]n some arrangements, the stitch bond 320 is electrically connected to the conductive pad” and so it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a stitch bond in the combination of Lin and Cheah because as Lin explicitly teaches it as an alternative).
Regarding claim 6, the combination of Lin and Cheah teaches the electronic device of claim 1,
wherein the nanotwin plated layer includes a first portion, a second portion, and a twin boundary between the first and second portions in which crystal lattices on each side of the twin boundary are linked by mirrored symmetry (Lin par. 29 teaches that “[t]he term ‘nanotwinned’ refers to two crystals [or two portions of a crystal] are formed mirrored across a common crystallographic plane” and so conductive pad 200 contains a first portion, a second portion, and a twin boundary between the portions in which there is a mirror symmetry as Lin teaches the conductive pad being nanotwinned).
Regarding claim 7, the combination of Lin and Cheah teaches the electronic device of claim 1,
wherein the nanotwin plated layer completely covers an outer surface of the conductive terminal inside the package structure (Lin fig. 2B conductive pad 200 completely covers transition layer 42 within the encapsulant 60).
Regarding claim 8, Lin teaches a system, comprising
a circuit board and an electronic device attached to the circuit board (Fig. 1 substrate 10 and substrate 100), the electronic device comprising:
a package structure (Fig. 1 encapsulant 60);
a conductive terminal (Figs. 1, 2B seed and transition layer 40/42) having a nanotwin plated layer (Figs. 1, 2B conductive pads 200 disposed on transition layer 42 and par. 49 teaches that “the conductive pad 200 is a [nanotwinned]-Cu pad”), the conductive terminal soldered to a conductive feature of the circuit board (Fig. 2B conductive pad 200 is soldered to substrate 100 which par. 28 teaches “may include an interconnection structure, such as a plurality of conductive traces and/or a plurality of conductive through vias” and so the conductive pad would be coupled to a conductive feature on substrate 100);
a semiconductor die in the package structure (Fig. 1 substrate 100 in encapsulant 60); and
a bond wire enclosed by the package structure (Fig. 1 conductive wires 300 enclosed by encapsulant 60) and having a first end and a second end, the first end connected to the semiconductor die by a first bond, and the second end connected to the nanotwin plated layer by a second bond (Fig. 1 conductive wires 300 have first ends connected to substrate 100 by a first bond and second ends connected to conductive pad 200 by a second bond).
Lin does not appear to teach
a conductive terminal exposed outside the package structure.
Cheah teaches
a conductive terminal exposed outside the package structure (Fig. 2 terminal 12b electrically connected to semiconductor die 16 through bond wire 24 and has external portion exposed outside housing 22).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Cheah because the extension of the terminal outside the housing allows for external control of the semiconductor device.
Regarding claim 9, the combination of Lin and Cheah teaches the system of claim 8,
wherein the conductive terminal includes copper (Lin par. 52 teaches that “the transition layer 42 includes Cu”), and the nanotwin plated layer includes copper (Lin par. 49 teaches that “the conductive pad 200 is a [nanotwinned]-Cu pad”).
Regarding claim 10, the combination of Lin and Cheah teaches the system of claim 8,
wherein the second bond is a stich bond (While Lin fig. 2B teaches ball bond 310 disposed on conductive pad 200, in par. 33 Lin teaches that “[i]n some arrangements, the stitch bond 320 is electrically connected to the conductive pad” and so it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a stitch bond in the combination of Lin and Cheah because as Lin explicitly teaches it as an alternative).
Regarding claim 11, the combination of Lin and Cheah teaches the system of claim 8,
wherein the nanotwin plated layer includes a first portion, a second portion, and a twin boundary between the first and second portions in which crystal lattices on each side of the twin boundary are linked by mirrored symmetry (Lin par. 29 teaches that “[t]he term ‘nanotwinned’ refers to two crystals [or two portions of a crystal] are formed mirrored across a common crystallographic plane” and so conductive pad 200 contains a first portion, a second portion, and a twin boundary between the portions in which there is a mirror symmetry as Lin teaches the conductive pad being nanotwinned).
Regarding claim 12, the combination of Lin and Cheah teaches the system of claim 8,
wherein the nanotwin plated layer completely covers an outer surface of the conductive terminal inside the package structure (Lin fig. 2B conductive pad 200 completely covers transition layer 42 within the encapsulant 60).
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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