DETAILED ACTION
This action is responsive to the following communication: the response filed 12/23/25. The changes and remarks disclosed therein have been considered.
Claim(s) status:1-2 and 4-20 pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 14: it appears that “sending and alert” in line(s) 10 was meant to be -- sending an alert --.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 7-9, 14-15, 17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dayacap et al. (US 2020/0135284 ‒hereinafter Dayacap) in view of Iwasaki et al. (US 2015/0055419 ‒hereinafter Iwasaki).
Regarding claim 1, Dayacap discloses a memory device comprising:
a memory array (NAND flash memory 902; fig. 9) comprising memory cells (storage memory cells; para 0015); and
control logic (903; fig. 9) operatively coupled with the memory array (902), the control logic (903) to perform operations comprising:
causing, as part of a true erase sub-operation (erase iterations; fig. 3, 8), an erase pulse (401/402; fig. 4, further 801; fig. 8) to be applied to one or more sub-blocks (i.e. a block that is being erased) of the memory array (902);
tracking (via a counter at 804; fig. 8, para 0051) a number of suspend commands (a value of erase suspend commands, i.e. erase suspend commands 304; fig. 3, further 802; fig. 8) received from a processing device (901; fig. 9), including suspend commands (304) received while memory cells of the one or more sub-blocks are being erased (i.e. during an erase iteration);
causing, in response to receiving each suspend command (304/802), the true erase sub-operation to be suspended (805; fig. 8) to enable performing a non-erase memory operation (303; fig. 3, further 811; fig. 8); and
in response to the number of suspend commands satisfying a threshold criterion (YES at 804; fig. 8), the processing device (901) to terminate sending suspend commands (806; fig. 8).
Dayacap does not expressly disclose sending an alert to the processing device.
Iwasaki discloses sending an alert (Erase interrupt command completion notification S19; fig. 3) to the processing device (16; fig. 1) to terminate sending suspend commands (issuance of erase interrupt command S18, i.e. suspend command, is terminated when completed; para 0038).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is modifiable as taught by Iwasaki for the purpose of facilitating data access by varying timing schemes of particular operations (para 0048-0050, 0054 of Iwasaki), which is common and well known in the art to improve the overall performance of the device and secure integrity of data storage.
Regarding claim 2, Dayacap discloses the memory device, wherein the processing device comprises one of: a value corresponding to the number of suspend commands (fig. 8).
Dayacap does not expressly disclose sending the alert to the processing device.
Iwasaki discloses sending the alert to the processing device (fig. 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is modifiable as taught by Iwasaki for the purpose of facilitating data access by varying timing schemes of particular operations (para 0048-0050, 0054 of Iwasaki), which is common and well known in the art to improve the overall performance of the device and secure integrity of data storage.
Regarding claim 4, Dayacap discloses the memory device, wherein the operations further comprise detecting the number of suspend commands satisfying the threshold criterion (804; fig. 8) after the memory cells begin to be erased (after beginning of being erased at 801; fig. 8).
Regarding claim 7, Dayacap discloses the memory device, further comprising a counter coupled with the control logic, the counter to track the number of suspend commands received from the processing device (para 0046).
Regarding claim 8, Dayacap discloses a memory device comprising:
a memory array (NAND flash memory 902; fig. 9) comprising memory cells (storage memory cells; para 0015); and
control logic (903; fig. 9) operatively coupled with the memory array (902), the control logic (903) to perform operations comprising:
causing, as part of a true erase sub-operation (erase iterations; fig. 3, 8), an erase pulse (401/402; fig. 4, further 801; fig. 8) to be applied to one or more sub-blocks (i.e. a block that is being erased) of the memory array (902);
tracking (via a counter at 804; fig. 8, para 0051) a number of suspend commands (a value of erase suspend commands, i.e. erase suspend commands 304; fig. 3, further 802; fig. 8) received from a processing device (901; fig. 9) during time periods (i.e. iteration periods; fig. 3) that a memory line (memory line of erase pulse 401/402; fig. 3, further fig. 4) of the memory array is caused to ramp towards (i.e. ramp increases; fig. 3, further 401; fig. 4) an erase voltage (VEV; fig. 4) of the erase pulse (401/402);
causing, in response to receiving each suspend command (304/802), the true erase sub-operation to be suspended (805; fig. 8) to enable performing a non-erase memory operation (303; fig. 3, further 811; fig. 8); and
in response to the number of suspend commands satisfying a threshold criterion (YES at 804; fig. 8), the processing device (901) to terminate sending suspend commands (806; fig. 8).
Dayacap does not expressly disclose sending an alert to the processing device.
Iwasaki discloses sending an alert (Erase interrupt command completely notification S19; fig. 3) to the processing device (16; fig. 1) to terminate sending suspend commands (issuance of erase interrupt command S18, i.e. suspend command, is terminated when completed; para 0038).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is modifiable as taught by Iwasaki for the purpose of facilitating data access by varying timing schemes of particular operations (para 0048-0050, 0054 of Iwasaki), which is common and well known in the art to improve the overall performance of the device and secure integrity of data storage.
Regarding claim 9, Dayacap discloses the memory device, further comprising a counter coupled with the control logic, the counter to track the number of suspend commands received from the processing device (para 0046).
Regarding claim 14, Dayacap discloses a method comprising:
causing, by control logic (903; fig. 9) of a memory device (902; fig. 9), as part of a true erase sub-operation (erase iterations; fig. 3, 8), an erase pulse (401/402; fig. 4, further 801; fig. 8) to be applied to one or more sub-blocks (i.e. a block that is being erased) of the memory array (902);
tracking (via a counter at 804; fig. 8, para 0051) a number of suspend commands (a value of erase suspend commands, i.e. erase suspend commands 304; fig. 3, further 802; fig. 8) received from a processing device (901; fig. 9), including suspend commands (304) received while memory cells of the one or more sub-blocks are being erased (i.e. during an erase iteration);
causing, in response to receiving each suspend command (304/802), the true erase sub-operation to be suspended (805; fig. 8) to enable performing a non-erase memory operation (303; fig. 3, further 811; fig. 8); and
in response to the number of suspend commands satisfying a threshold criterion (YES at 804; fig. 8), by the control logic (903), the processing device (901) to terminate sending suspend commands (806; fig. 8).
Dayacap does not expressly disclose sending an alert.
Iwasaki discloses sending an alert (Erase interrupt command completion notification S19; fig. 3) to the processing device (16; fig. 1) to terminate sending suspend commands (issuance of erase interrupt command S18, i.e. suspend command, is terminated when completed; para 0038).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is modifiable as taught by Iwasaki for the purpose of facilitating data access by varying timing schemes of particular operations (para 0048-0050, 0054 of Iwasaki), which is common and well known in the art to improve the overall performance of the device and secure integrity of data storage.
Regarding claim 15, Dayacap discloses the method, wherein the processing device comprises one of: a value corresponding to the number of suspend commands (fig. 8).
Dayacap does not expressly disclose sending an alert to the processing device.
Iwasaki discloses sending an alert (Erase interrupt command completion notification S19; fig. 3) to the processing device (16; fig. 1) to terminate sending suspend commands (issuance of erase interrupt command S18, i.e. suspend command, is terminated when completed; para 0038).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is modifiable as taught by Iwasaki for the purpose of facilitating data access by varying timing schemes of particular operations (para 0048-0050, 0054 of Iwasaki), which is common and well known in the art to improve the overall performance of the device and secure integrity of data storage.
Regarding claim 17, Dayacap discloses the method, further comprising detecting the number of suspend commands satisfying the threshold criterion (804; fig. 8) after the memory cells begin to be erased (after beginning of being erased at 801; fig. 8).
Regarding claim 20, Dayacap discloses the method, further comprising tracking, using a counter coupled to the control logic, the number of suspend commands received from the processing device (para 0046).
Claim(s) 5, 10, 13, 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dayacap et al. (US 2020/0135284 ‒hereinafter Dayacap) in view of Iwasaki et al. (US 2015/0055419 ‒hereinafter Iwasaki), and further in view of Madraswala et al. (US 2017/0285969 ‒hereinafter Madraswala).
Regarding claim 5, Dayacap does not expressly disclose the memory device, wherein the operations further comprise stopping a timer in response to each suspend command, the timer tracking a time duration of the true erase sub-operation, wherein sending the alert to the processing device comprises sending, to the processing device, at least one of a total cumulative number of suspend commands received from the processing device or a total cumulative amount of time tracked by the timer.
Iwasaki discloses wherein sending the alert to the processing device (fig. 3) comprises sending, to the processing device (16; fig. 1), at least one of a total cumulative number of suspend commands received from the processing device or a total cumulative amount of time (an elapsed time is considered a total cumulative amount of time from start of erase corresponding to a count value; para 0026) tracked (counter 17 tracks the elapsed time after a start of erase operation to when a threshold is exceeded; fig. 1 para 0026) by the timer (counter 17).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is modifiable as taught by Iwasaki for the purpose of facilitating data access by varying timing schemes of particular operations (para 0048-0050, 0054 of Iwasaki), which is common and well known in the art to improve the overall performance of the device and secure integrity of data storage.
Madraswala discloses wherein the operations further comprise stopping a timer in response to each suspend command (i.e. maintaining a timer when erase operation is suspended; para 0062, 0064), the timer tracking a time duration of the true erase sub-operation (track an amount of time expected, i.e. for suspend erase operations; para 0062, 0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Madraswala for the purpose of facilitating data accessing schemes by improving erase operation time to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (para 0017-0018 of Madraswala).
Regarding claim 10, Dayacap, as modified, does not expressly disclose the memory device, wherein the operations further comprise stopping a timer in response to each suspend command, the timer tracking a time duration of the time periods.
Madraswala discloses wherein the operations further comprise stopping a timer in response to each suspend command (i.e. maintaining a timer when erase operation is suspended; para 0062, 0064), the timer tracking a time duration of the time periods (track an amount of time expected, i.e. for suspend erase operations; para 0062, 0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Madraswala for the purpose of facilitating data accessing schemes by improving erase operation time to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (para 0017-0018 of Madraswala).
Regarding claim 13, Dayacap does not expressly disclose the memory device, wherein the operations further comprise stopping a timer in response to each suspend command, the timer tracking a time duration of the true erase sub-operation, and wherein sending the alert to the processing device comprises sending, to the processing device, at least one of a total cumulative number of suspend commands received from the processing device or a total cumulative amount of time tracked by the timer.
Iwasaki discloses wherein sending the alert to the processing device (fig. 3) comprises sending, to the processing device (16; fig. 1), at least one of a total cumulative number of suspend commands received from the processing device or a total cumulative amount of time (an elapsed time is considered a total cumulative amount of time from start of erase corresponding to a count value; para 0026) tracked (counter 17 tracks the elapsed time after a start of erase operation to when a threshold is exceeded; fig. 1 para 0026) by the timer (counter 17).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is modifiable as taught by Iwasaki for the purpose of facilitating data access by varying timing schemes of particular operations (para 0048-0050, 0054 of Iwasaki), which is common and well known in the art to improve the overall performance of the device and secure integrity of data storage.
Madraswala discloses wherein the operations further comprise stopping a timer in response to each suspend command (i.e. maintaining a timer when erase operation is suspended; para 0062, 0064), the timer tracking a time duration of the true erase sub-operation (track an amount of time expected, i.e. for suspend erase operations; para 0062, 0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Madraswala for the purpose of facilitating data accessing schemes by improving erase operation time to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (para 0017-0018 of Madraswala).
Regarding claim 16, Dayacap does not expressly disclose the method, further comprising stopping a timer in response to each suspend command, the timer tracking a time duration of the true erase sub-operation, and wherein sending the alert to the processing device comprises sending, to the processing device, at least one of a total cumulative number of suspend commands received from the processing device or a total cumulative amount of time tracked by the timer.
Iwasaki discloses wherein sending the alert to the processing device (fig. 3) comprises sending, to the processing device (16; fig. 1), at least one of a total cumulative number of suspend commands received from the processing device or a total cumulative amount of time (an elapsed time is considered a total cumulative amount of time from start of erase corresponding to a count value; para 0026) tracked (counter 17 tracks the elapsed time after a start of erase operation to when a threshold is exceeded; fig. 1 para 0026) by the timer (counter 17).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is modifiable as taught by Iwasaki for the purpose of facilitating data access by varying timing schemes of particular operations (para 0048-0050, 0054 of Iwasaki), which is common and well known in the art to improve the overall performance of the device and secure integrity of data storage.
Madraswala discloses wherein the operations further comprise stopping a timer in response to each suspend command (i.e. maintaining a timer when erase operation is suspended; para 0062, 0064), the timer tracking a time duration of the true erase sub-operation (track an amount of time expected, i.e. for suspend erase operations; para 0062, 0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Madraswala for the purpose of facilitating data accessing schemes by improving erase operation time to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (para 0017-0018 of Madraswala).
Regarding claim 18, Dayacap does not expressly disclose the method, further comprising stopping a timer in response to each suspend command, the timer tracking a time duration of the true erase sub-operation.
Madraswala discloses wherein the operations further comprise stopping a timer in response to each suspend command (i.e. maintaining a timer when erase operation is suspended; para 0062, 0064), the timer tracking a time duration of the true erase sub-operation (track an amount of time expected, i.e. for suspend erase operations; para 0062, 0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Madraswala for the purpose of facilitating data accessing schemes by improving erase operation time to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (para 0017-0018 of Madraswala).
Claim(s) 6, 11, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dayacap et al. (US 2020/0135284 ‒hereinafter Dayacap) in view of Iwasaki et al. (US 2015/0055419 ‒hereinafter Iwasaki), in view of Madraswala et al. (US 2017/0285969 ‒hereinafter Madraswala), and further in view of Yi et al. (US 2015/0287468 ‒hereinafter Yi).
Regarding claim 6, Dayacap discloses the memory device, wherein the operations further comprise, after each suspend command is received: causing re-ramping of a memory line to resume the true erase sub-operation (fig. 3).
Dayacap, as modified, does not expressly disclose performing an erase recovery of the one or more sub-blocks; restarting the timer in response to receipt of a resume command.
Madraswala discloses restarting the timer in response to receipt of a resume command (i.e. maintaining a timer when erase operation is suspended; para 0062, 0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Madraswala for the purpose of facilitating data accessing schemes by improving erase operation time to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (para 0017-0018 of Madraswala).
Yi discloses performing an erase recovery of the one or more sub-blocks (para 0096).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Yi for the purpose of facilitating data accessing schemes by reducing latencies in erase operations (para 0097 of Yi), which is common and well known in the art for increasing throughput of memory operations in a shorter amount of time while consuming fewer resources overall as compared to lengthy operations.
Regarding claim 11, Dayacap discloses the memory device, wherein the operations further comprise, after each suspend command is received: causing re-ramping of the memory line to resume the true erase sub-operation (fig. 3).
Dayacap, as modified, does not expressly disclose performing an erase recovery of the one or more sub-blocks; restarting the timer in response to receipt of a resume command.
Madraswala discloses restarting the timer in response to receipt of a resume command (i.e. maintaining a timer when erase operation is suspended; para 0062, 0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Madraswala for the purpose of facilitating data accessing schemes by improving erase operation time to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (para 0017-0018 of Madraswala).
Yi discloses performing an erase recovery of the one or more sub-blocks (para 0096).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Yi for the purpose of facilitating data accessing schemes by reducing latencies in erase operations (para 0097 of Yi), which is common and well known in the art for increasing throughput of memory operations in a shorter amount of time while consuming fewer resources overall as compared to lengthy operations.
Regarding claim 19, Dayacap discloses the method, further comprising, after each suspend command is received: causing re-ramping of a memory line to resume the true erase sub-operation (fig. 3).
Dayacap, as modified, does not expressly disclose performing an erase recovery of the one or more sub-blocks; restarting the timer in response to receipt of a resume command.
Madraswala discloses restarting the timer in response to receipt of a resume command (i.e. maintaining a timer when erase operation is suspended; para 0062, 0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Madraswala for the purpose of facilitating data accessing schemes by improving erase operation time to increase throughput of memory operations in a shorter amount of time, which is common and well known in the art for consuming fewer resources overall as compared to lengthy operations (para 0017-0018 of Madraswala).
Yi discloses performing an erase recovery of the one or more sub-blocks (para 0096).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dayacap is further modifiable as taught by Yi for the purpose of facilitating data accessing schemes by reducing latencies in erase operations (para 0097 of Yi), which is common and well known in the art for increasing throughput of memory operations in a shorter amount of time while consuming fewer resources overall as compared to lengthy operations.
Allowable Subject Matter
Claim(s) 12 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 12, the prior art fails to teach or suggest the claimed limitations, namely the voltage offset corresponding to the number of suspend commands tracked and the time duration and being dependent on a type of multi-level memory cells of the memory array; changing the erase voltage by the voltage offset; and causing the memory line of the one or more sub-blocks to ramp to the changed erase voltage.
The allowable claims are supported in at least fig. 6 of the instant application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-20 of U.S. Patent No. 11,942,159. Although the claims at issue are not identical, they are not patentably distinct from each other because the only differences are nominal and would have been obvious to one of ordinary skill in the art.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______