DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7 and 11 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by SHIRAKI (US 20090127605).
Regarding claim 1, SHIRAKI discloses a semiconductor device, comprising:
a major element (the transistor 510 on the right, see fig 11, 12 and 13, para 97 and 106 and figure I below) including a first semiconductor region (fig 13B, 511, para 107), a first electrode (the electrode connected to the left 513 which functions as a source, see fig 11 and 13B, para 107), a second electrode (the electrode connected to the right 513 which functions as a drain, see fig 11 and 13B, para 107), a first gate electrode (gate electrode 516, see fig 11 and 13B, para 107), and a first insulating member (the insulator 515, see fig 11 and 13B, para 107), the first insulating member being positioned between the first gate electrode and the first semiconductor region (see fig 13B), a gate voltage of the first gate electrode controlling a current flowing between the first electrode and the second electrode via the first semiconductor region (516 is a gate, and 513 are a source and a drain, see fig 13B, 516, para 107);
a gate driver (the pad 520 connected to the gate, see fig 11, para 97 and figure I below) supplying the gate voltage to the first gate electrode; and
a recording element (the portion of the device including 550, 560, 570 and the middle 510, see fig 11 and figure I below) electrically connected with the gate driver (see fig 11 and figure I below), the recording element recording, as continuously changing analog data, a number of times that the gate voltage is supplied to the first gate electrode while being enough to switch the major element on.
Regarding the claimed feature(s) "… a gate voltage of the first gate electrode controlling a current flowing between the first electrode and the second electrode via the first semiconductor region … supplying the gate voltage to the first gate electrode … the recording element recording, as continuously changing analog data, a number of times that the gate voltage is supplied to the first gate electrode while being enough to switch the major element on", when the structure recited in the reference is substantially similar to that of the claims, the structure of the reference is capable of performing the same function as the claimed structure. See MPEP 2114.II: A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 2, SHIRAKI discloses the device according to claim 1, wherein
the recording element includes a capacitor (fig 14, 570, para 99, and see figure I below), and
the capacitor is charged with a charge supplied from the gate driver each time the major element is switched on (570 is connected to 520, see fig 14).
Regarding the claimed feature(s) "the capacitor is charged with a charge supplied from the gate driver each time the major element is switched on", when the structure recited in the reference is substantially similar to that of the claims, the structure of the reference is capable of performing the same function as the claimed structure. See MPEP 2114.II: A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 3, SHIRAKI discloses the device according to claim 1, wherein
the recording element includes a second semiconductor region (the channel of the transistor 510, see fig 13B, 511, para 107), a third electrode (the electrode connected to the left 513 which functions as a source, see fig 11 and 13B, para 107), a fourth electrode (the electrode connected to the right 513 which functions as a drain, see fig 11 and 13B, para 107), a second gate electrode (gate electrodes 516, see fig 11 and 13B, para 107), and a second insulating member (the insulator 515, see fig 11 and 13B, para 107), and
the second insulating member is positioned between the second gate electrode and the second semiconductor region (see fig 13B).
Regarding claim 7, SHIRAKI discloses the device according to claim 1, wherein
the recording element includes a variable resistance layer (the channel region of the transistor 510 beneath the gate 516 whose resistance can be changed by a gate voltage, see fig 13B, para 107), and
a resistance of the variable resistance layer changes according to a charge supplied from the gate driver each time the major element is switched on (the channel region of the transistor 510 beneath the gate 516 has a resistance which can be changed by a gate voltage, see fig 13B, para 107).
Regarding claim 11, SHIRAKI discloses a semiconductor device, comprising:
a major element (the transistor 510 on the right, see fig 11, 12 and 13, para 97 and 106 and figure I below) including a first semiconductor region (fig 13B, 511, para 107), a first electrode (the electrode connected to the left 513 which functions as a source, see fig 11 and 13B, para 107), a second electrode (the electrode connected to the right 513 which functions as a drain, see fig 11 and 13B, para 107), a first gate electrode (gate electrode 516, see fig 11 and 13B, para 107), and a first insulating member (the insulator 515, see fig 11 and 13B, para 107), the first insulating member being positioned between the first gate electrode and the first semiconductor region (see fig 13B);
a gate driver (the pad 520 connected to the gate, see fig 11, para 97 and figure I below) connected to the first gate electrode;
a recording element (the portion of the device including 550, 560, 570 and the middle 510, see fig 11 and figure I below) including a second semiconductor region (the channel of the transistor 510, see fig 13B, 511, para 107), a third electrode (the electrode connected to the left 513 which functions as a source, see fig 11 and 13B, para 107), a fourth electrode (the electrode connected to the right 513 which functions as a drain, see fig 11 and 13B, para 107), at least a pair of second gate electrodes (gate electrodes 516, see fig 11 and 13B, para 107), and a second insulating member (the insulator 515, see fig 11 and 13B, para 107), the second insulating member being positioned between the second gate electrode and the second semiconductor region (see fig 11);
a capacitor (the capacitor 570, see fig 11, para 99 and figure I below);
a diode (the diode 560, see fig 11, para 99 and figure I below);
a first resistance (a resistor 550, see fig 11, para 99 and figure I below); and
a second resistance (another resistor 550, see fig 11, para 99 and figure I below),
the capacitor, the diode, and the first resistance being connected in series between the gate driver and the second gate electrode (570, 550 and 560 are connected in series between 520 and the gate electrode of the middle transistor 510, see fig 11 and figure I below),
one end portion of the second resistance being connected to one end of the capacitor (one end of the second resistor 550 is connected to the capacitor 570).
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Figure I: SHIRAKI figure 11 with added annotations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHIRAKI (US 20090127605) in view of TORIYAMA (US 20220415884).
Regarding claim 4, SHIRAKI discloses the device according to claim 3, further comprising:
a support body including a first surface (the substrate 580 including its top surface, see fig 13B, para 103),
the support body supporting the major element and the recording element (580 supports and underlies the elements 550 and 560 in the major and recording elements, see fig 13B),
the first and second electrodes of the major element being positioned to be separated from each other in a first direction (the source and drain regions 513 are separated in the horizontal direction in fig 13B),
the first direction being along the first surface (the top surface of 580 is a horizontal surface, see fig 13B),
the first semiconductor region of the major element being located between the first electrode and the second electrode in the first direction (semiconductor region 511 is between 513 in the horizontal direction, see fig 13B),
the third and fourth electrodes of the recording element being positioned to be separated from each other in a fourth direction (the source and drain regions 513 are separated in the horizontal direction in fig 13B),
the fourth direction being along the first surface (the top surface of 580 is a horizontal surface, see fig 13B),
the second semiconductor region of the recording element being located between the third electrode and the fourth electrode in the fourth direction (semiconductor region 511 is between 513 in the horizontal direction, see fig 13B).
SHIRAKI fails to explicitly disclose a device further comprising the first semiconductor region of the major element forming a first Schottky junction with the second electrode,
the first gate electrode of the major element facing the first Schottky junction in a second direction,
the second direction being along the first surface and crossing the first direction,
the second semiconductor region of the recording element forming a second Schottky junction with the fourth electrode,
the second gate electrode of the recording element facing the second Schottky junction in a fifth direction,
the fifth direction being along the first surface and crossing the fourth direction.
TORIYAMA teaches a device further comprising the first semiconductor region of the major element (a region 19, see fig 1, 19, para 49) forming a first Schottky junction (19 and 21 form a Schottky junction, see fig 1, para 49) with the second electrode (an upper electrode 21, see fig 1, para 49),
the first gate electrode (gate electrode 16, see fig 1, para 40) of the major element facing the first Schottky junction in a second direction (16 faces the junction between 19 and 20 in the horizontal direction in fig 1),
the second direction being along the first surface (the horizontal direction in fig 1 extends in the front surface of the device in fig 1) and crossing the first direction (the vertical direction in fig 1 which separates the source and drain electrodes 21 and 25, see fig 1),
the second semiconductor region (another region 19, see fig 1, 19, para 49) of the recording element forming a second Schottky junction (19 and 21 form a Schottky junction, see fig 1, para 49) with the fourth electrode (another upper electrode 21, see fig 1, para 49)e,
the second gate electrode (gate electrode 16, see fig 1, para 40) of the recording element facing the second Schottky junction in a fifth direction (16 faces the junction between 19 and 20 in the horizontal direction in fig 1),
the fifth direction being along the first surface (the horizontal direction in fig 1 extends in the front surface of the device in fig 1) and crossing the fourth direction (the vertical direction in fig 1 which separates the source and drain electrodes 21 and 25, see fig 1).
SHIRAKI and TORIYAMA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SHIRAKI with the Schottky junctions of TORIYAMA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SHIRAKI with the Schottky junctions of TORIYAMA in order to suppress a decrease in the latch-up resistance (see TORIYAMA para 96).
Regarding claim 5, SHIRAKI and TORIYAMA disclose the device according to claim 4.
SHIRAKI further discloses a device, wherein the support body includes
a substrate (580 is a substrate, see fig 13B, para 103), and
the first semiconductor region and the second semiconductor region each are located on the substrate (the regions 511 are located at least indirectly on 580, see fig 13B).
Regarding claim 6, SHIRAKI and TORIYAMA disclose the device according to claim 5.
SHIRAKI further discloses a device, wherein
the substrate includes a second surface positioned at a side opposite to the first surface in a third direction crossing the first and second directions (580 has a bottom surface which is opposite its top surface in the vertical direction, see fig 13B), and
the third and fourth electrodes of the recording element are positioned on the first surface (the source and drain regions 513 of the recording transistor and their electrodes are at least indirectly on 580 and thus all of its surfaces, see fig 13B).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHIRAKI (US 20090127605) in view of TORIYAMA (US 20220415884) and further in view of SHIRAHAMA (US 20120146156).
Regarding claim 8, SHIRAKI and TORIYAMA disclose the device according to claim 6.
SHIRAKI and TORIYAMA fails to explicitly disclose a device, further comprising:
a differential circuit connected between the gate driver and the second gate electrode.
SHIRAHAMA teaches a device, further comprising:
a differential circuit (fig 2, 205, para 42) connected between the gate driver and the second gate electrode (205 is connected to VDD, 203 and 204, see fig 2).
SHIRAKI, TORIYAMA and SHIRAHAMA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SHIRAKI and TORIYAMA with the differential circuit of SHIRAHAMA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SHIRAKI and TORIYAMA with the differential circuit of SHIRAHAMA in order to increase accuracy (see SHIRAHAMA para 8(.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHIRAKI (US 20090127605) in view of TORIYAMA (US 20220415884) and SHIRAHAMA (US 20120146156) and further in view of BRAMANTI (US 20200321456).
Regarding claim 9, SHIRAKI, BRAMANTI and TORIYAMA disclose the device according to claim 8.
SHIRAKI fails to explicitly disclose a device, further comprising:
an integration circuit connected between the gate driver and the second gate electrode.
BRAMANTI teaches a device, further comprising:
an integration circuit (integrator 204, see fig 4, para 6%) connected between the gate driver and the second gate electrode (204 is connected between transistors, see fig 4).
SHIRAKI, TORIYAMA, SHIRAHAMA and BRAMANTI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SHIRAKI, TORIYAMA and SHIRAHAMA with the integration circuit of BRAMANTI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SHIRAKI, TORIYAMA and SHIRAHAMA with the integration circuit of BRAMANTI in order to increase the speed of the device (see BRAMANTI para 34).
Regarding claim 10, SHIRAKI, BRAMANTI and TORIYAMA disclose the device according to claim 9.
SHIRAKI further discloses a device, further comprising:
a diode (the diode 560, see fig 11, para 99 and figure I below) connected in series between the gate driver and the second gate electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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