Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of Species 1 in the reply filed on 6/24/2026 is acknowledged.
Claim 10 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/24/2026.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application JP 2023150173 filed on 09/15/2023. The foreign application is not in English. The certified copy of the foreign priority application has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application JP 2023150173 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda (US . Pub 20210376760), hereinafter referred to as Ikeda, and Inokuchi et al. (US Pub. 20220029012), hereinafter referred to as Inokuchi.
Regarding claim 1, Ikeda teaches a semiconductor device, comprising: a major element (3, Fig. 12, para. 25) ;and a recording element (Ikeda, 1’, 1a, 1b, Fig. 1, para. 25) electrically connected with the first electrode, the recording element recording, as analog data, a maximum value of a change amount dV/dt of a voltage of the first electrode over time (Ikeda, C2, C5, Fig. 11, 12, paras. 55, 58). Because Ikeda detects the dV/dt during the transient state where the voltage change is steepest and almost constant (Ikeda, para. 37, Fig. 2), the recorded charge represents the maximum value of the change amount dV/dt.
Ikeda does not teach wherein the major element includes a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member, the first insulating member being positioned between the first gate electrode and the first semiconductor region, a gate voltage of the first gate electrode controlling a current flowing between the first electrode and the second electrode via the first semiconductor region, but does teach wherein the major element includes transistors (Ikeda, Q1, Q2, Fig. 12, paras 27, 32).
Inokuchi teaches a semiconductor device (Inokuchi, 110, Figs. 1-3), which may be a transistor. Inokuchi teaches that the semiconductor device may include a first semiconductor region (Inokuchi, 11, Figs.1, 3, para. 68), a first electrode (Inokuchi, 51, Figs. 1-3, para. 67), a second electrode (Inokuchi, SE, 52, 55, Figs. 1, 3, para. 73), a first gate electrode (Inokuchi, 53, Figs. 1-3, para. 40), and a first insulating member (Inokuchi, 41, Figs. 1, 3, para. 40), the first insulating member being positioned between the first gate electrode and the first semiconductor region, a gate voltage of the first gate electrode controlling a current flowing between the first electrode and the second electrode via the first semiconductor region (Inokuchi, para. 53).
Therefore it would have been obvious to one having ordinary skill in the art to have utilized the semiconductor device of Inokuchi as the transistor in the major element of Ikeda in order to provide high speed switching with suppressed turn-on and turn-off loss (Inokuchi, para. 58) and allow for the switching of large currents (Inokuchi Fig. 68).
Regarding claim 2, modified Ikeda teaches the device according to claim 1, wherein the recording element includes a capacitor (Ikeda, C2, Figs. 11, 12, paras. 55, 58), and the capacitor stores the maximum value of dV/dt as a charge.
Regarding claim 3, modified Ikeda teaches the device according to claim 2, wherein the recording element includes a second semiconductor region (Inokuchi, 11, Figs.1, 3, para. 68), a third electrode a first electrode (Inokuchi, 51, Figs. 1-3, para. 67), a fourth electrode (Inokuchi, SE, 52, 55, Figs. 1, 3, para. 73), a second gate electrode (Inokuchi, 53, Figs. 1-3, para. 40), and a second insulating member (Inokuchi, 41, Figs. 1, 3, para. 40), and the second insulating member is positioned between the second gate electrode and the second semiconductor region . These features are included in transistors Q1 and Q2 which are shown as parts of both the major element (Ikeda, 3, Fig. 12) and part of the recording element (Ikeda, 1a, Fig. 12).
Regarding claim 4, modified Ikeda teaches the device according to claim 1, wherein the recording element records the maximum value of dV/dt at turn-off of the major element (Ikeda, 1b, C5, Fig. 12, para. 59).
Regarding claim 5, modified Ikeda teaches the device according to claim 1, wherein the recording element records the maximum value of dV/dt at turn-off of the major element (Ikeda, 1a, C2, Fig. 12, para. 58).
Regarding claim 6, modified Ikeda teaches the device according to claim 1, comprising: a plurality of the recording elements (Ikeda, 1’, 1a, 1b, Fig. 2, 1’ is a voltage change rate detection circuit with two voltage change rate detection circuits 1a and 1b), the plurality of recording elements each having an electrical connection with the first electrode (Ikeda, Fig. 12 shows both 1a and 1b electrically connected to the major element 3),the electrical connections being configured to be switched in order (Ikeda, paras 58. 59, 1b records the dv/dt when the output rises (turns on) and 1a records the dv/dt when the output falls (turns off) which will happen sequentially).
Regarding claim 7, modified Ikeda taches the device according to claim 3, further comprising: a support body including a first surface (Inokuchi, 50S, 5F, Fig. 1, para. 67), the support body supporting the major element and the recording element (Inokuchi, Fig. 2), the first and second electrodes of the major element being positioned to be separated from each other in a first direction (Inokuchi, Fig. 1, first direction is Y), the first direction being along the first surface (Inokuchi, Fig. 1), the first semiconductor region of the major element being located between the first electrode and the second electrode in the first direction (Inokuchi, Fig. 1), the first semiconductor region of the major element forming a first Schottky junction with the second electrode (Inokuchi para. 54), the first gate electrode of the major element facing the first Schottky junction in a second direction, the second direction being along the first surface and crossing the first direction (Inokuchi, para. 61, second direction is X), the third and fourth electrodes of the recording element being positioned to be separated from each other in a fourth direction (Inokuchi, Fig. 2, fourth direction is Y), the fourth direction being along the first surface, the second semiconductor region of the recording element being located between the third electrode and the fourth electrode in the fourth direction (Inokuchi, Fig. 1), the second semiconductor region of the recording element forming a second Schottky junction with the fourth electrode (Inokuchi, para. 54), the second gate electrode of the recording element facing the second Schottky junction in a fifth direction, the fifth direction being along the first surface and crossing the fourth direction (Inokuchi, para. 61, fifth direction is X).
Regarding claim 8, modified Ikeda teaches the device according to claim 7, wherein the support body includes a substrate (Inokuchi, 50u, Fig. 1, para. 41), and the first semiconductor region and the second semiconductor region each are located on the substrate.
Regarding claim 9, modified Ikeda teaches the device according to claim 8, wherein the substrate includes a second surface positioned at a side opposite to the first surface in a third direction (Inokuchi, Fig. 1, third direction is Z) crossing the first and second directions, and the third and fourth electrodes (Inokuchi, 51, SE, 52, 55) of the recording element are positioned on the first surface (Inokuchi, 50F, Fig. 1) but are not positioned at the second surface.
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nishimura et al. (US Pub. 20130277640) teaches using a Schottky diode as a current rectifying element.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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