Prosecution Insights
Last updated: August 17, 2026
Application No. 18/589,820

SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRAL HEAT SLUG AND ISOLATION

Non-Final OA §102§103§112
Filed
Feb 28, 2024
Examiner
WIEGAND, TYLER J
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
74 granted / 99 resolved
+6.7% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
37 currently pending
Career history
131
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
41.5%
+1.5% vs TC avg
§102
32.2%
-7.8% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 99 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This action is responsive to the election received on 07/07/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention II in the reply filed on 07/07/2026 is acknowledged. Claim(s) 1-13 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant's election with traverse of Species B in the reply filed on 07/07/2026 is acknowledged. The traversal is at least partially on the ground(s) that there is no serious search burden on the examiner. This argument has been found persuasive. The restriction requirement between species has been withdrawn. Claim Objections Claim(s) 27 is/are objected to because of the following informalities: Claim 27, lines 2-3, “bond pads facing towards the board side surface” where the word ‘from’ makes it unclear which way the bond pads are facing. Appropriate correction is required. Claim Rejections - 35 USC § 112(b) The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 14-27 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim(s) 14 and 25 both recite the limitation "the high voltage section of the leadframe having an output portion connected to the output portion of the leadframe at an interior end by another mount portion" in lines 11-12 of claims 14 and 25. This limitation is unclear in view of the specification and drawings and lacks proper antecedent basis. There has been no previous recitation of an output portion of the leadframe in either of the claims such that there is no antecedent basis. If it is applicant’s intent to refer to the output portion of the high voltage section of the leadframe introduced in the same limitation (i.e. “the high voltage section of the leadframe having an output portion connected to the output portion of the high voltage section of the leadframe at an interior end by another mount portion”), then it is unclear how an element may be considered connected to itself. Alternatively, it is the examiner’s interpretation that this may be a typo and that the claim limitation is intended to refer to the output portion of the heat slug. This is supported by [0040] of the instant application which states “The output portion 3076 of the high voltage section 3071 of the leadframe 307 overlies and is coupled to an output portion 3211 of the heat slug 321”. Due to the multiple possible unclear interpretations, claims 14 and 25 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. The balance of claims are rejected under 35 U.S.C. 112(b) at least for their dependencies. For the purposes of this examination, the interpretation supported by the specification will be considered and the claims will be interpreted to read as “the high voltage section of the leadframe having an output portion connected to the output portion of the heat slug at an interior end by another mount portion”. Regarding claims 14, 15, 16, and 18, the term "proximate" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Proximate” is defined as “very near” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how close the two elements indicated as proximate to one another need to be in order to be considered proximate or very near. The term “proximate” implicitly requires boundaries at some maximum value above the target distance beyond which one is not “proximate” to the other element any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one element must be within some small percentage of the total device size from the other element or within a certain number of distance units from the other element (such as several nm, µm, or mm), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, claims 14, 15, 16, and 18 are rejected as being indefinite under 35 U.S.C. 112(b), and claim(s) 17 and 19-24 is/are rejected at least for their dependencies, for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. For the purposes of this examination, it will be interpreted that any two elements located within the same device are proximate to one another. Claim 20 recites the limitation "high voltage output terminals formed by leads extending through the mold compound from another interior lead portion of the output portion of the high voltage section of the leadframe" in lines 4-5 of the claim. There is unclear antecedent basis for this limitation in the claim. Claim 14, which claim 20 depends on, has previously recited “the output portion of the high voltage section of the leadframe further comprising another interior lead portion” in lines 13-14 of the claim. Because of this former limitation, it is unclear if the “another interior lead portion” of claim 20 is the same element or is a different element from claim 14. Due to the multiple possible unclear interpretations, claim 20 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Claims 21-24 are rejected under 35 U.S.C. 112(b) at least for their dependencies. For the purposes of this examination, the claim will be interpreted to read as “high voltage output terminals formed by leads extending through the mold compound from the another interior lead portion of the output portion of the high voltage section of the leadframe”. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 14-22 and 25-27 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0138054 A1; Yan et al.; 05/2025; (“Yan”). The applied reference has a common applicant and inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). Regarding Claim 14. Yan discloses An apparatus (#300, Figure 5, semiconductor device package where Figures 4A-4F represent various cross sectional views of the device), comprising: a leadframe (#307, Figure 5, leadframe) having a board side surface (Figure 4F, upward facing surface of #307) and an opposite top surface (Figure 4F, downward facing surface of #307), the leadframe having a high voltage section (#3071, Figure 5) and a low voltage section (#3072, Figure 5) spaced from and electrically isolated from the high voltage section ([0008] and Figure 4F, #3071 and #3072 are spaced apart and electrically isolated from one another); a heat slug (#321, Figure 5, heat slug) mounted to the high voltage section (Figure 5, #321 is mounted to the #3071 section of #307), the heat slug having an input portion (Figure 5, portion of #321 connected to input terminal IN+) and an output portion (Figure 5, portion of #321 connected to output terminal IN-) spaced from the input portion and coupled to the input portion by a heat slug connect portion (Figure 5, the input and output portions are spaced apart and coupled to one another by the portion of #321 underneath #315), the high voltage section of the leadframe (#3071) having an input portion connected to the input portion of the heat slug at an interior end by a mount portion (Figures 4B and 5, input portion IN+ of #307 is mounted to the input portion of #321 at an interior bottom end by a rectangular mount portion shown in Figure 4B), the input portion of the leadframe further comprising an interior lead portion that is connected to the mount portion by a flexible connect portion (Figures 4B and 5, IN+ includes an interior lead portion within #323 which is connected to the rectangular mount portion by a flexible Z-shaped connect portion), the high voltage section of the leadframe (#3071) having an output portion connected to the output portion of the heat slug at an interior end by another mount portion (Figures 4B and 5, output portion IN- of #307 is mounted to the output portion of #321 at an interior bottom end by a another rectangular mount portion shown in Figure 4B), the output portion of the high voltage section of the leadframe further comprising another interior lead portion that is connected to the another mount portion by another flexible connect portion (Figures 4B and 5, IN- includes an interior lead portion within #323 which is connected to the other rectangular mount portion by another flexible Z-shaped connect portion); an insulating material (#317, Figure 4CC, insulating layer) mounted to the heat slug and providing a die mount area for a semiconductor die (Figure 4CC, #317 is mounted indirectly to #321 by #313 and provides an area to mount semiconductor die #305); a semiconductor die (#305, Figure 4CC) having a Hall element (#308, Figure 4CC) mounted to the die mount area and positioned so that the Hall element is proximate to the heat slug (Figure 4CC, #308 is mounted to #305 so that it is proximate to #321); electrical connections of wire bonds or ribbon bonds (#325, Figure 5, bond wires) between bond pads of the semiconductor die and leads of an interior lead portion of the low voltage section of the leadframe ([0037], “bond wires 325 or ribbon bonds, connect bond pads (not shown but see, for example bond pads 102 in FIG. 1B) on the semiconductor die 305 to leads of the low voltage section 3072 of the leadframe 307”); and mold compound (#323, Figure 5) covering the semiconductor die, portions of the leadframe, and portions of the heat slug (Figures 4A-4F and 5, #323 at least partially covers #305, portions of #307, and portions of #321) while a board side surface of the heat slug is exposed forming a thermal pad for a semiconductor device package (#322, Figures 4F and 5, external thermal pad of #321 which is exposed from the mold compound according to [0035]). Regarding Claim 15. Yan discloses The apparatus of claim 14, wherein the input portion of the high voltage section of the leadframe, the output portion of the high voltage section of the leadframe, and the heat slug are configured to carry a current to the heat slug connect portion that is proximate to the semiconductor die ([0035], “heat slug 321 is electrically coupled to the high voltage section 3071 of the leadframe 307 and forms a low resistance current path to carry the current I from an input portion to an output portion (see input and output signals IN+ and IN-, and current I in FIG. 1C) of the high voltage section 3071 of the leadframe 307, and is the heat slug 321 shaped to carry the current I to a position proximate to the semiconductor die 305”, i.e. the heat slug carriers current between IN+ and IN- to be proximate to the semiconductor die). Regarding Claim 16. Yan discloses The apparatus of claim 15 wherein the heat slug connect portion is proximate to the Hall element on the semiconductor die (Figure 5, the portion of #321 underneath #315 functioning as the connect portion is proximate to #308 on #305). Regarding Claim 17. Yan discloses The apparatus of claim 14, wherein the flexible connect portion of the leadframe has an “S”, “Z”, “C”, “V”, “L” or “U” shape when viewed in a plan view from a top side surface (Figure 4B, the flexible connect portions have a Z-shape in the plan view). Regarding Claim 18. Yan discloses The apparatus of claim 14, wherein the Hall element on the semiconductor die is a first Hall element, and further comprising a second Hall element on the semiconductor die spaced from the first Hall element, the first Hall element and the second Hall element positioned proximate to the heat slug connect portion ([0036], the semiconductor die #305 may include a plurality of Hall elements #308 proximate to the heat slug #321). Regarding Claim 19. Yan discloses The apparatus of claim 18, wherein the first Hall element and the second Hall element are configured to output a voltage corresponding to magnetic field caused by a current flowing in the heat slug ([0036], “a magnetic field corresponding to the current I flowing through the heat slug 321 can be sensed by the Hall element within the semicustom die 305” and [0002], “voltage proportional to a magnetic field is output by the Hall sensor while a current is applied to the Hall sensor”, i.e. #308s output a voltage proportional to a magnetic field induced by current in #321). Regarding Claim 20. Yan discloses The apparatus of claim 14, and further comprising: high voltage input terminals (#322, Figure 5, misnumbered element that is equivalent to terminals #310 in the high voltage region) formed by leads extending through the mold compound from the interior lead portion of the input portion of the high voltage section of the leadframe (Figure 5, #322s are formed as leads extending through #323 from the interior portions of IN+ of #307); high voltage output terminals (#324, Figure 5, element that is equivalent to terminals #310 in the high voltage region) formed by leads extending through the mold compound from the another interior lead portion of the output portion of the high voltage section of the leadframe (Figure 5, #324s are formed as leads extending through #323 from the interior portions of IN- of #307); and low voltage terminals (#310, Figure 5, terminals) formed by leads extending through the mold compound from the interior lead portion of the low voltage section of the leadframe (Figure 5, #310s are formed as leads extending through #323 from the interior portions of #3072 of #307). Regarding Claim 21. Yan discloses The apparatus of claim 20, wherein the high voltage input terminals, the high voltage output terminals, and the low voltage terminals have gull wing shapes (Figure 5, #310s, #322s, and #324s all have gull wing shapes, see [0024]). Regarding Claim 22. Yan discloses The apparatus of claim 20, wherein the semiconductor device package is a small outline integrated circuit (“SOIC”) package or a wide SOIC package ([0052], the device is part of a wide SOIC package). Regarding Claim 25. Yan discloses A Hall current sensor device (#300, Figure 5, semiconductor device package where Figures 4A-4F represent various cross sectional views of the device which may be a Hall current sensor according to [0005]), comprising: a leadframe (#307, Figure 5, leadframe) having a board side surface (Figure 4F, upward facing surface of #307) and an opposite top surface (Figure 4F, downward facing surface of #307), the leadframe having a high voltage section (#3071, Figure 5) and a low voltage section (#3072, Figure 5) spaced from and electrically isolated from the high voltage section ([0008] and Figure 4F, #3071 and #3072 are spaced apart and electrically isolated from one another); a heat slug (#321, Figure 5, heat slug) mounted to the high voltage section (Figure 5, #321 is mounted to the #3071 section of #307), the heat slug having an input portion (Figure 5, portion of #321 connected to input terminal IN+) and an output portion (Figure 5, portion of #321 connected to output terminal IN-) spaced from the input portion and coupled to the input portion by a heat slug connect portion (Figure 5, the input and output portions are spaced apart and coupled to one another by the portion of #321 underneath #315), the high voltage section of the leadframe (#3071) having an input portion connected to the input portion of the heat slug at an interior end by a mount portion (Figures 4B and 5, input portion IN+ of #307 is mounted to the input portion of #321 at an interior bottom end by a rectangular mount portion shown in Figure 4B), the input portion of the leadframe further comprising an interior lead portion that is connected to the mount portion by a flexible connect portion (Figures 4B and 5, IN+ includes an interior lead portion within #323 which is connected to the rectangular mount portion by a flexible Z-shaped connect portion), the high voltage section of the leadframe (#3071) having an output portion connected to the output portion of the heat slug at an interior end by another mount portion (Figures 4B and 5, output portion IN- of #307 is mounted to the output portion of #321 at an interior bottom end by a another rectangular mount portion shown in Figure 4B), the output portion of the high voltage section of the leadframe further comprising another interior lead portion that is connected to the another mount portion by another flexible connect portion (Figures 4B and 5, IN- includes an interior lead portion within #323 which is connected to the other rectangular mount portion by another flexible Z-shaped connect portion); an insulating material (#317, Figure 4CC, insulating layer) over the heat slug (Figure 4CC, #317 is over a side surface of #321 where “over” does not require direct contact) and forming a die mount area for a semiconductor die (Figure 4CC, #317 is mounted indirectly to #321 by #313 and provides an area to mount semiconductor die #305); a semiconductor die (#305, Figure 4CC) having a Hall element (#308, Figure 4CC) mounted to the die mount area (Figure 4CC, #305 is mounted to an area of #317), the semiconductor die having bond pads on a device side surface ([0037], “bond wires 325 or ribbon bonds, connect bond pads (not shown but see, for example bond pads 102 in FIG. 1B) on the semiconductor die 305 to leads of the low voltage section 3072 of the leadframe 307”, i.e. there are bond pads on a surface of #305); electrical connections comprising wire bonds or ribbon bonds (#325, Figure 5, bond wires) between the bond pads of the semiconductor die and an interior portion of a set of leads of the low voltage section of the leadframe ([0037], “bond wires 325 or ribbon bonds, connect bond pads (not shown but see, for example bond pads 102 in FIG. 1B) on the semiconductor die 305 to leads of the low voltage section 3072 of the leadframe 307”, i.e. #025s connect the bond pads to the leads of the low voltage section); and mold compound (#323, Figure 5) covering the electrical connections, the semiconductor die, portions of the leadframe, and a portion of the heat slug to form a semiconductor device package (Figures 4A-4F and 5, #323 at least partially covers #325s, #305, portions of #307, and portions of #321 to form a package), while a portion of the heat slug is exposed from the mold compound forming a thermal pad for a semiconductor device package (#322, Figures 4F and 5, external thermal pad of #321 which is exposed from the mold compound according to [0035]). Regarding Claim 26. Yan discloses The Hall current sensor device of claim 25, wherein the semiconductor die is mounted on the insulating material with the bond pads facing away from the board side surface of the leadframe (Figures 4F and 5, #305 is mounted on #317 with the top surface of the bond pads of #305, which are connected to #325s, facing away from the top surface of #307). Regarding Claim 27. Yan discloses The Hall current sensor device of claim 25, wherein the semiconductor die is mounted with the bond pads facing towards the board side surface of the leadframe (Figures 4F and 5, #305 is mounted on #317 with the bottom surface of the bond pads of #305, which are connected to #325s, facing towards from the top surface of #307). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Claim(s) 14-17, 20-22, and 25-27 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0096767 A1; Sung et al.; 03/2024; (“Sung”). The applied reference has a common applicant and inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). Regarding Claim 14. Sung discloses An apparatus (#100, Figures 1-1C, electronic device), comprising: a leadframe (#110, #113, and #114, Figure 1, lead frames) having a board side surface (Figure 1A, downward facing surface of leads) and an opposite top surface (Figure 1A, upward facing surface of leads), the leadframe having a high voltage section (left side of device in Figure 1) and a low voltage section (right side of device in Figure 1) spaced from and electrically isolated from the high voltage section (Figures 1-1C, the left and right sides of the device are spaced apart and electrically isolated from one another by mold compound #108 and insulator #121); a heat slug (#116, Figure 1, heat slug) mounted to the high voltage section (Figure 1, #116 is mounted to the left side of the device), the heat slug having an input portion (#117, Figure 1, portion of #116 current flows into based on the arrow ‘I’) and an output portion (#118, Figure 1, portion of #116 current flows out of based on the arrow ‘I’) spaced from the input portion and coupled to the input portion by a heat slug connect portion (Figure 1, #117 and #118 are spaced apart and coupled to one another by the portion #119 of #116), the high voltage section of the leadframe having an input portion connected to the input portion of the heat slug at an interior end by a mount portion (Figure 1, the left section of the device lead frames includes an input portion #110 connected to #117 by a mount portion #115), the input portion of the leadframe further comprising an interior lead portion that is connected to the mount portion by a flexible connect portion (Figure 1, #110 includes an interior portion of #111s connected to #115 through a z-shaped flexible connect portion), the high voltage section of the leadframe having an output portion connected to the output portion of the heat slug at an interior end by another mount portion (Figure 1, the left section of the device lead frames includes an output portion #113 connected to #118 by another mount portion #115), the output portion of the high voltage section of the leadframe further comprising another interior lead portion that is connected to the another mount portion by another flexible connect portion (Figure 1, #113 includes an interior portion of #112s connected to #115 through a z-shaped flexible connect portion), an insulating material (#121, Figures 1 and 1C, adhesive which may be an insulator according to [0032]) mounted to the heat slug and providing a die mount area for a semiconductor die (Figures 1 and 1C, #121 is mounted directly to #116 and provides an area to mount semiconductor die #120); a semiconductor die (#120, Figures 1 and 1C) having a Hall element ([0032], “the semiconductor die 120 includes a Hall-effect sensor”) mounted to the die mount area and positioned so that the Hall element is proximate to the heat slug (Figures 1 and 1C, [0032], #120 is mounted to #121 so that the Hall-effect sensor can measure the current flowing though the heat slug, i.e. the two elements are proximate to one another); electrical connections of wire bonds or ribbon bonds (#122, Figure 1, bond wires) between bond pads of the semiconductor die and leads of an interior lead portion of the low voltage section of the leadframe ([0033], “second leads 114 are electrically coupled to respective conductive features (e.g., copper or other metal bond pads) of the semiconductor die 120 by bond wires 122”); and mold compound (#108, Figures 1-1C, package structure which may be a mold compound according to [0030]) covering the semiconductor die, portions of the leadframe, and portions of the heat slug (1-1C, #108 at least partially covers #120, portions of the leads of the lead frame, and portions of #116) while a board side surface of the heat slug is exposed forming a thermal pad for a semiconductor device package (Figures 1A and 1B, a bottom facing side surface of #116 is exposed from #108 as a thermal pad according to [0035]). Regarding Claim 15. Sung discloses The apparatus of claim 14, wherein the input portion of the high voltage section of the leadframe, the output portion of the high voltage section of the leadframe, and the heat slug are configured to carry a current to the heat slug connect portion that is proximate to the semiconductor die ([0035] and Figure 1, the current ‘I’ is carried to the section of #116 near #120 via the portions #110 and #113 of the lead frame and the heat slug #116 itself). Regarding Claim 16. Sung discloses The apparatus of claim 15 wherein the heat slug connect portion is proximate to the Hall element on the semiconductor die (Figures 1 and 1C, [0032], #120 is mounted to #121 so that the Hall-effect sensor can measure the current flowing though the heat slug portion #119, i.e. the two elements are proximate to one another). Regarding Claim 17. Sung discloses The apparatus of claim 14, wherein the flexible connect portion of the leadframe has an “S”, “Z”, “C”, “V”, “L” or “U” shape when viewed in a plan view from a top side surface (Figure 1, #115s have a Z-shape in the plan view). Regarding Claim 20. Sung discloses The apparatus of claim 14, and further comprising: high voltage input terminals (#111, Figure 1, first set of first leads) formed by leads extending through the mold compound from the interior lead portion of the input portion of the high voltage section of the leadframe (Figure 1, #111s are formed by leads extending through #108 from the interior portion of #110); high voltage output terminals (#112, Figure 1, second set of first leads) formed by leads extending through the mold compound from the another interior lead portion of the output portion of the high voltage section of the leadframe (Figure 1, #112s are formed by leads extending through #108 from the interior portion of #113); and low voltage terminals (#114, Figure 1, set of second leads) formed by leads extending through the mold compound from the interior lead portion of the low voltage section of the leadframe (Figure 1, #114s are formed by leads extending through #108 from the interior portion of the low voltage lead frame on the right side). Regarding Claim 21. Sung discloses The apparatus of claim 20, wherein the high voltage input terminals, the high voltage output terminals, and the low voltage terminals have gull wing shapes (Figures 1B-1C, #111s, #112s, and #114s all have gull wing shapes, see [0033]). Regarding Claim 22. Sung discloses The apparatus of claim 20, wherein the semiconductor device package is a small outline integrated circuit (“SOIC”) package or a wide SOIC package ([0030], the device a small form factor integrated circuit). Regarding Claim 25. Sung discloses A Hall current sensor device (#100, Figures 1-1C, electronic device which may be a Hall current sensor according to [0030]), comprising: a leadframe (#110, #113, and #114, Figure 1, lead frames) having a board side surface (Figure 1A, downward facing surface of leads) and an opposite top surface (Figure 1A, upward facing surface of leads), the leadframe having a high voltage section (left side of device in Figure 1) and a low voltage section (right side of device in Figure 1) spaced from and electrically isolated from the high voltage section (Figures 1-1C, the left and right sides of the device are spaced apart and electrically isolated from one another by mold compound #108 and insulator #121); a heat slug (#116, Figure 1, heat slug) mounted to the high voltage section (Figure 1, #116 is mounted to the left side of the device), the heat slug having an input portion (#117, Figure 1, portion of #116 current flows into based on the arrow ‘I’) and an output portion (#118, Figure 1, portion of #116 current flows out of based on the arrow ‘I’) spaced from the input portion and coupled to the input portion by a heat slug connect portion (Figure 1, #117 and #118 are spaced apart and coupled to one another by the portion #119 of #116), the high voltage section of the leadframe having an input portion connected to the input portion of the heat slug at an interior end by a mount portion (Figure 1, the left section of the device lead frames includes an input portion #110 connected to #117 by a mount portion #115), the input portion of the leadframe further comprising an interior lead portion that is connected to the mount portion by a flexible connect portion (Figure 1, #110 includes an interior portion of #111s connected to #115 through a z-shaped flexible connect portion), the high voltage section of the leadframe having an output portion connected to the output portion of the heat slug at an interior end by another mount portion (Figure 1, the left section of the device lead frames includes an output portion #113 connected to #118 by another mount portion #115), the output portion of the high voltage section of the leadframe further comprising another interior lead portion that is connected to the another mount portion by another flexible connect portion (Figure 1, #113 includes an interior portion of #112s connected to #115 through a z-shaped flexible connect portion), an insulating material (#121, Figures 1 and 1C, adhesive which may be an insulator according to [0032]) over the heat slug (Figure 1C, #121 is over a portion of #116) and forming a die mount area for a semiconductor die (Figures 1 and 1C, #121 provides an area to mount semiconductor die #120); a semiconductor die (#120, Figures 1 and 1C) having a Hall element ([0032], “the semiconductor die 120 includes a Hall-effect sensor”) mounted to the die mount area (Figures 1 and 1C, [0032], #120 is mounted to #121), the semiconductor die having bond pads on a device side surface ([0033], “second leads 114 are electrically coupled to respective conductive features (e.g., copper or other metal bond pads) of the semiconductor die 120 by bond wires 122”); electrical connections comprising wire bonds or ribbon bonds (#122, Figure 1, bond wires) between the bond pads of the semiconductor die and an interior portion of a set of leads of the low voltage section of the leadframe ([0033], “second leads 114 are electrically coupled to respective conductive features (e.g., copper or other metal bond pads) of the semiconductor die 120 by bond wires 122”); and mold compound (#108, Figures 1-1C, package structure which may be a mold compound according to [0030]) covering the electrical connections, the semiconductor die, portions of the leadframe, and a portion of the heat slug to form a semiconductor device package (1-1C, #108 at least partially covers #122, #120, portions of the leads of the lead frame, and portions of #116 to form a package), while a portion of the heat slug is exposed from the mold compound forming a thermal pad for a semiconductor device package (Figures 1A and 1B, a bottom facing side surface of #116 is exposed from #108 as a thermal pad according to [0035]). Regarding Claim 26. Sung discloses The Hall current sensor device of claim 25, wherein the semiconductor die is mounted on the insulating material with the bond pads facing away from the board side surface of the leadframe (Figures 1 and 1C, #120 is mounted on #121 with the top surface of the bond pads facing away from the bottom surface of the leads). Regarding Claim 27. Sung discloses The Hall current sensor device of claim 25, wherein the semiconductor die is mounted with the bond pads facing towards the board side surface of the leadframe (Figures 1 and 1C, #120 is mounted on #121 with the bottom surface of the bond pads facing towards the bottom surface of the leads). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 23-24 is/are rejected under 35 U.S.C. 103 as being obvious over US 2025/0138054 A1; Yan et al.; 05/2025; (“Yan”) as applied to claim 20 above, and further in view of US 2024/0170359 A1; Kim et al.; 05/2024; (“Kim”). The applied reference Kim also has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). Regarding Claim 23. Yan discloses The apparatus of claim 20. Yan does not disclose the apparatus further comprising: struts extending from support bars and extending over the heat slug, the struts on opposite sides of the heat slug. However, Kim discloses an apparatus (#100, Figures 1A-1E, electronic device) comprising a heat slug (#110) mounted on a lead frame (#107, conductive metal leads) wherein the apparatus further comprises struts (portions of #109 inside of #110, support leads) extending from support bars (portions of #109 outside of #110) and extending over the heat slug (Figure 1B, #109s extend at least partially over #110), the struts on opposite sides of the heat slug (Figure 1B, #109s are located on opposite sides of #110) It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming support bars and struts as part of the lead frame in Yan as was done by Kim in order to provide a further path for heat removal from the heat slug (see [0034] of Kim) and improve device integrity (see [0023] of Kim) Regarding Claim 24. Yan in view of Kim discloses The apparatus of claim 23, and further comprising slots in the heat slug configured to receive the struts and to contact the struts ([0023], Figures 1B and 1C, the heat slug provides slotted access for the structurally supporting lead frame leads). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2021/0313258 A1; Tuncer et al.; 10/2021 – Figures 3A-3D disclose an apparatus including a conductive pathway (#316) crossing between portions of a lead frame (#304) to provide a current in proximity to a semiconductor die (#308) including a hall sensor ([0028]). However, no portion of the conductive pathway is exposed by the mold compound (#303) to allow for heat dissipation such that the conductive pathway is not interpreted to function as a heat slug. US 11,614,482 B1; Tuncer, Enis; 03/2023 – Figure 2A discloses an apparatus including a conductive pathway (#239) crossing between portions of a lead frame (#227 and #229) to provide a current in proximity to a semiconductor die (#203) including a hall sensor (column 7, lines 32-34). However, no portion of the conductive pathway is exposed by the mold compound (#221) to allow for heat dissipation such that the conductive pathway is not interpreted to function as a heat slug. US 2021/0202269 A1; Baello et al.; 07/2021 – Figures 1A-1D disclose an apparatus including a conductive pathway (#50) crossing between portions of a lead frame (#32) to provide a current in proximity to a semiconductor die (#40) including a hall sensor ([0018]). However, no portion of the conductive pathway is exposed by the mold compound (#70) to allow for heat dissipation such that the conductive pathway is not interpreted to function as a heat slug. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TYLER J WIEGAND/Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Feb 28, 2024
Application Filed
Jul 27, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707803
Light-Emitting Device
2y 8m to grant Granted Aug 11, 2026
Patent 12672280
VERTICAL TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
3y 2m to grant Granted Jun 30, 2026
Patent 12666764
DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE WITH REDUCED SURFACE ADSORPTION DURING SELF-ASSEMBLY
3y 11m to grant Granted Jun 23, 2026
Patent 12666820
DISPLAY PANEL AND DISPLAY DEVICE
3y 3m to grant Granted Jun 23, 2026
Patent 12660179
SEMICONDUCTOR DEVICE AND IMPROVED DICING REGION FOR REDUCED PEELING DEFECTS
4y 3m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
84%
With Interview (+9.8%)
3y 5m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 99 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month