Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings objection noted in the Non-Final Rejection mailed 5/15/2026 is overcome by the amendments to claim 1 in the instant set of claims, filed 8/12/2026. Accordingly, the drawings filed 2/28/2024 are accepted.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 8-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang (US 20250040187 A1).
Regarding claim 1, Chang discloses a forksheet transistor (Fig. 27) comprising:
an isolation pillar (124 with 126/132), wherein the isolation pillar corresponds to a single layer structure (Note: “corresponds to” may reasonably establish a relation between one structure to another, and the claim as written reasonably includes relations beyond the relation of Applicant’s disclosure. The pillar corresponds to a transistor and there is only one tier/layer of transistors, i.e., this device is not stacked/multi-level CMOS. Thus, the pillar corresponds to “a single layer structure”);
a transistor (100) comprising a source region (175; one of S/D in [0056]: “S/D”) in direct contact with the isolation pillar (The source is formed in the method step of Fig. 10 as 146. Fig. 27 shows an alternative view of the source 175, and this source has a shape directly contacting isolation pillar 124. Note: direct contact would occur when the source is exposed by trench 151 in the method step of Fig. 12 and then directly covered by the pillar 124 in the method step of Fig. 14) and a drain region (175; the other of S/D in [0056]: “S/D”)-in direct contact with the isolation pillar (The drain is formed in the method step of Fig. 10 as 146. Fig. 27 shows an alternative view of the drain 175, and this drain has a shape directly contacting isolation pillar 124. Note: direct contact would occur when the drain is exposed by trench 151 in the method step of Fig. 10 and then directly covered by the pillar 124 in the method step of Fig. 14); and
a channel (106) that is in direct contact with the source region (Note: “direct contact” is a fundamental requirement for a functional transistor.) and that is in direct contact with the drain region (Note: “direct contact” is a fundamental requirement for a functional transistor.),
the channel comprising a top surface (See annotated figure for surface designation), a bottom surface (See annotated figure for surface designation), and an isolation-interface surface (See annotated figure for surface designation) that is in direct contact with the isolation pillar (106 is directly contacting 132),
wherein a vertical dimension (Z dimension) of the isolation-interface surface is smaller than a vertical dimension (Z dimension) between the top surface and the bottom surface.
Illustrated below is a marked and annotated figure of Chang, Fig. 27.
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Regarding claim 2, Chang discloses the forksheet transistor of claim 1 (Fig. 27), wherein the channel further comprises: a frontside facing surface (See annotated figure for surface designation) that connects the top surface and the isolation-interface surface (directly connects); and a backside facing surface (See annotated figure for surface designation) that connects the bottom surface and the isolation-interface surface (directly connects).
Regarding claim 3, Chang discloses the forksheet transistor of claim 2 (Fig. 27), wherein the frontside facing surface is obtusely angled with respect to the top surface (an obtuse angle is illustrated) and wherein the backside facing surface is obtusely angled with respect to the bottom surface (an obtuse angle is illustrated).
Regarding claim 4, Chang discloses the forksheet transistor of claim 3 (Fig. 27), wherein the isolation-interface surface is in direct contact with a sidewall of the isolation pillar (106 is directly contacting a sidewall of 132).
Regarding claim 5, Chang discloses the forksheet transistor of claim 4 (Fig. 27), wherein the frontside facing surface is acutely angled with respect to the sidewall of the isolation pillar (an acute angle is illustrated) and wherein the backside facing surface is acutely angled with respect to the sidewall of the isolation pillar (an acute angle is illustrated).
Regarding claim 6, Chang discloses the forksheet transistor of claim 5 (Fig. 27), wherein the frontside facing surface is linear between the top surface and the isolation-interface surface (a straight line is illustrated) and wherein the backside facing surface is linear between the bottom surface and the isolation-interface surface (a straight line is illustrated).
Regarding independent claim 8, Chang discloses a forksheet transistor (Fig. 27: transistor 100) comprising:
an isolation pillar (124 with 126/132), wherein the isolation pillar corresponds to a single layer structure (Note: “corresponds to” may reasonably establish a relation between one structure to another, and the claim as written reasonably includes relations beyond the relation of Applicant’s disclosure. The pillar corresponds to a transistor and there is only one tier/layer of transistors, i.e., this device is not stacked/multi-level CMOS. Thus, the pillar corresponds to “a single layer structure”); and
a channel (106) comprising a main body region (See annotated figure for region designation) and an interfacial tapered region (See annotated figure for region designation),
the interfacial tapered region comprising an isolation-interface surface (See annotated figure for surface designation) that is in direct contact with the isolation pillar (106 is directly contacting 132),
wherein a vertical dimension (Z dimension) of the isolation-interface surface is smaller than a vertical dimension (Z dimension) of the main body region.
Regarding claim 9, Chang discloses the forksheet transistor of claim 8 (Fig. 27), wherein the interfacial tapered region further comprises: a frontside facing surface (See annotated figure for surface designation) that connects a top surface of the main body region and the isolation-interface surface (directly connects); and a backside facing surface (See annotated figure for surface designation) that connects a bottom surface of the main body region and the isolation-interface surface (directly connects).
Regarding claim 10, Chang discloses the forksheet transistor of claim 9 (Fig. 27), wherein the frontside facing surface is obtusely angled with respect to the top surface of the main body region (an obtuse angle is illustrated) and wherein the backside facing surface is obtusely angled with respect to the bottom surface of the main body region (an obtuse angle is illustrated).
Regarding claim 11, Chang discloses the forksheet transistor of claim 10 (Fig. 27), wherein the isolation-interface surface is in direct contact with a sidewall of the isolation pillar (106 is directly contacting a sidewall of 132).
Regarding claim 12, Chang discloses the forksheet transistor of claim 11 (Fig. 27), wherein the frontside facing surface is acutely angled with respect to the sidewall of the isolation pillar (an acute angle is illustrated) and wherein the backside facing surface is acutely angled with respect to the sidewall of the isolation pillar (an acute angle is illustrated).
Regarding claim 13, Chang discloses the forksheet transistor of claim 12 (Fig. 27), wherein the frontside facing surface is linear between the top surface of the main body region and the isolation-interface surface (a straight line is illustrated) and wherein the backside facing surface is linear between the bottom surface of the main body region and the isolation-interface surface (a straight line is illustrated).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 5 above, and further in view of Pan (US 20240429278 A1).
Regarding claim 7, Chang discloses the forksheet transistor of claim 5, but fails to teach the claimed shape of the frontside and backside facing surfaces. Thus, Chang fails to teach “wherein the frontside facing surface is nonlinear between the top surface and the isolation-interface surface and wherein the backside facing surface is nonlinear between the bottom surface and the isolation-interface surface”.
Pan discloses wherein the frontside facing surface (Fig. 25: See annotated figure for surface designation) is nonlinear (a curved shape is shown) between the top surface (See annotated figure for surface designation) and the isolation-interface surface (See annotated figure for surface designation) and wherein the backside facing surface (See annotated figure for surface designation) is nonlinear (a curved shape is shown) between the bottom surface (See annotated figure for surface designation) and the isolation-interface surface.
Modifying the channel shape (of Chang) by incorporating the channel shape of Pan would arrive at the claimed nonlinear shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation: 1) the channel shape is formed by the same method (Chang: linear tapering is formed in Fig. 18; Pan: nonlinear tapering is formed in Fig. 20A); and 2) because the channel shape is formed for the same purpose to adjust electrical properties of the resultant transistor (Chang: [0038]: “a threshold voltage (Vt) of a FET device to be formed can be adjusted to meet requirements”; Pan: [0057]: “electrical characteristics”). Therefore, it would have been obvious to have the claimed nonlinear surfaces because they are differences in shape for a channel that is otherwise formed in the same way to adjust electrical properties of the transistor. MPEP 2144.04 (IV)(B).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 12 above, and further in view of Pan (US 20240429278 A1).
Regarding claim 14, Chang discloses the forksheet transistor of claim 12, but fails to teach the claimed shape of the frontside and backside facing surfaces. Thus, Chang fails to teach “wherein the frontside facing surface is nonlinear between the top surface of the main body region and the isolation-interface surface and wherein the backside facing surface is nonlinear between the bottom surface of the main body region and the isolation-interface surface”.
Pan discloses wherein the frontside facing surface (Fig. 25: See annotated figure for surface designation) is nonlinear (a curved shape is shown) between the top surface (See annotated figure for surface designation) of the main body region (See annotated figure for region designation) and the isolation-interface surface (See annotated figure for surface designation) and wherein the backside facing surface (See annotated figure for surface designation) is nonlinear (a curved shape is shown) between the bottom surface (See annotated figure for surface designation) of the main body region (See annotated figure for region designation) and the isolation-interface surface.
Modifying the channel shape (of Chang) by incorporating the channel shape of Pan would arrive at the claimed nonlinear shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation: 1) the channel shape is formed by the same method (Chang: linear tapering is formed in Fig. 18; Pan: nonlinear tapering is formed in Fig. 20A); and 2) because the channel shape is formed for the same purpose to adjust electrical properties of the resultant transistor (Chang: [0038]: “a threshold voltage (Vt) of a FET device to be formed can be adjusted to meet requirements”; Pan: [0057]: “electrical characteristics”). Therefore, it would have been obvious to have the claimed nonlinear surfaces because they are differences in shape for a channel that is otherwise formed in the same way to adjust electrical properties of the transistor. MPEP 2144.04 (IV)(B).
Response to Arguments
Applicant's arguments filed 8/12/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 8 that “Chang cannot possibly disclose that the first dielectric wall 124 is a single layer structure. Therefore, this reference also does not disclose that the dielectric layer 128 is in direct contact with an isolation-interface surface of the first semiconductor layers 106…Applicant respectfully submits that the arguments presented for independent Claim 1 are equally applicable for independent claim 8 by reciting analogous features as recited by independent claim 1”. Remarks at pg. .
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner finds differences Applicant has cited between the prior art and the disclosure. However, the claim as written reasonably includes meanings beyond the explicitly contended meaning. Furthermore, the chosen language in Applicant’s remarks differs from the language chosen in the instant claim. Accordingly, the rejection is maintained in substantially the same way as before, with adjusted citations and remarks, as necessitated by claim amendment and to promote clarity of the record. MPEP 2111.
Allowable Subject Matter
Claims 15 and 17-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 15 and 17-20 is the inclusion of the limitation “wherein the tapering of the respective end surfaces of the active nanosheets exposed by the isolation pillar opening comprises: from within the isolation pillar opening, laterally etching the sacrificial nanosheets with imperfect selectivity to the active nanosheets” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “tapering” and “from within the isolation pillar opening” in combination with all other limitations in claim 15. The prior art of record teaches tapering; however, the claimed method sequence is not disclosed by the prior art and is not found or rendered obvious by teachings elsewhere in the prior art.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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