DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-9, and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yokoyama (U.S. Publication No. 2024/0164083).
Regarding claim 1, Yokoyama teaches a semiconductor device comprising:
a substrate (Fig. 1B, substrate 110) including a memory cell array region (102), a contact region (104), and a connection region between the memory cell array region and the contact region (interface of 102/104 can be called a “connection region”, which is not defined or limited by the claim);
gate electrodes (120), on the memory cell array region and the connection region (Fig. 1B), the gate electrodes being stacked and spaced apart from each other in a vertical direction on the memory cell array region (Fig. 1B, spaced apart by insulating layers 124);
active layers (active layers 118) on the memory cell array region, the active layers being stacked and spaced apart from each other in the vertical direction on the memory cell array region (Fig. 1B); and
conductive connection patterns (Fig. 1C, connection patterns 140) on the connection region and the contact region (Fig. 1B-1C), the conductive connection patterns being stacked and spaced apart from each other in the vertical direction on the connection region (Fig. 1C),
wherein each of the active layers includes a channel region vertically overlapping the gate electrodes (Fig. 1B),
wherein the gate electrodes are electrically connected to the conductive connection patterns on the connection region (Fig. 1B-1C),
wherein the conductive connection patterns have a step structure including a plurality of step regions spaced apart from each other on the contact region (Fig. 1C), and
wherein the step structure has a first step portion stepping down along a first direction and a second step portion facing the first step portion and stepping up along the first direction (see Fig. 1C).
Regarding claim 2, Yokoyama teaches the semiconductor device of claim 1, wherein each of the active layers has a bar shape extending in a second direction perpendicular to the first direction (Fig. 1A),
wherein the first direction and the second direction are directions parallel to an upper surface of the substrate (X and Y directions in Fig. 1A-B),
wherein each of the active layers further includes a first source/drain region and a second source/drain region (see paragraph [0059] and known functionality of FET transistors which require a source and drain to function), and
wherein the channel region is between the first source/drain region and the second source/drain region in each of the active layers (see known functionality and configuration of FETs which require a channel between a source and drain to function).
Regarding claim 8, Yokoyama teaches the semiconductor device of claim 1, wherein, in the first direction, side surfaces of the gate electrodes are mis-aligned with side surfaces of the conductive connection patterns (see 1B, there are side surfaces of the gate electrodes at the interface of the gate and channel, which are internal to the gate structure and not present in the conductive connection portion; they are misaligned with the only side surfaces of the conductive connection portion which are the outermost surfaces only).
Regarding claim 9, Yokoyama teaches the semiconductor device of claim 1,
wherein each of the gate electrodes includes:
a lower electrode layer (see Fig. 1B, lower gate layer is the portion of the gate electrode below the channel layer); and
an upper electrode layer on the lower electrode layer and spaced apart from the lower electrode layer (Fig. 1B, portion of the gate electrode above the channel layer),
wherein the gate electrodes include a first gate electrode (Fig. 1B),
wherein the conductive connection patterns include a first conductive connection pattern connected to the first gate electrode (Fig. 1B-1C), and
wherein on the connection region of the substrate, the lower electrode layer and the upper electrode layer are in contact with the first conductive connection pattern (Fig. 1B).
Regarding claim 16, Yokoyama teaches a semiconductor device comprising:
a substrate (Fig. 1B, substrate 110) including a memory cell array region 102), a connection region (interface of 102/104), and a contact region (104) sequentially arranged in a first direction (X direction);
gate electrodes (120) on the memory cell array region and the connection region (Fig. 1B), and the gate electrodes being stacked and spaced apart from each other in a vertical direction (Fig. 1B); and
conductive connection patterns (140, Fig. 1C) on the contact region and the connection region, and the conductive connection patterns being stacked and spaced apart from each other in the vertical direction (Fig. 1B),
wherein the gate electrodes are electrically connected to the conductive connection patterns on the connection region (Fig. 1B-1C, connection region encompasses region where 102/104 interface, and therefore where the gate electrodes 120 become the conductive connection patterns 140),
wherein the conductive connection patterns have a step structure including a plurality of step regions spaced apart from each other in the first direction on the contact region (Fig. 1C and 2B), and
wherein the step structure has a first step portion stepping down along the first direction and a second step portion facing the first step portion and stepping up along the first direction (Fig. 1C).
Regarding claim 17, Yokoyama teaches the semiconductor device of claim 16, further comprising active layers (118) on the memory cell array region, the active layers being stacked and spaced apart from each other in the vertical direction (Fig. 1B),
wherein each of the active layers includes a channel region vertically overlapping the gate electrodes (Fig. 1B).
Regarding claim 18, Yokoyama teaches the semiconductor device of claim 16, wherein the conductive connection patterns include gate pad regions arranged in a step shape at the first step portion of the step structure (gate pad region is where vias 142 contact the conductive patterns 140, Fig. 1C).
Regarding claim 19, Yokoyama teaches the semiconductor device of claim 18, wherein the plurality of step regions have a first step region and a second step region sequentially arranged in the first direction (Fig. 2B), and
wherein among the gate pad regions of the conductive connection patterns, the gate pad regions in the second step region are at a level lower than the gate pad regions in the first step region (see Fig. 2F, each step region is further into the stack than the one before).
Regarding claim 20, Yokoyama teaches the semiconductor device of claim 16, further comprising:
a first gap-fill insulating pattern (Fig. 2I, 158);
a second gap-fill insulating pattern (159); and
interlayer insulating layers (Fig. 1C, 124) alternately stacked with the conductive connection patterns in the vertical direction (Fig. 1C),
wherein the conductive connection patterns and the interlayer insulating layers are between the first gap-fill insulating pattern and the second gap-fill insulating pattern (Fig. 2I), and
wherein the interlayer insulating layers extend from the first gap-fill insulating pattern (Fig. 2I).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama in view of Sharma et al. (U.S. Publication No. 2024/0008259).
Regarding claim 3, Yokoyama teaches the semiconductor device of claim 2, further comprising:
gate dielectric layers (128) between the channel region of each of the active layers and the gate electrodes (Fig. 1B); and
a data storage structure (Fig. 1A, storage structure 114) electrically connected to the second source/drain region of each of the active layers on the memory cell array region of the substrate (see Fig. 1A).
Yokoyama does not specifically teach a bit line electrically connected to the first source/drain region of each of the active layers on the memory cell array region of the substrate. However, Sharma teaches a similar device in which a bit line is connected to the opposite S/D contact of the storage structure (see Sharma Fig. 2A, storage structures 102 connected to one side and bit line 206 connected to the other). It would have been obvious to a person of skill in the art at the time of the effective filing date that a bit line would have been connected to the opposite side of the other side of the transistor from the storage structures because this is a basic structure for all 1T-1C DRAM devices to provide power to the transistors.
Regarding claim 4, Yokoyama in view of Sharma teaches the semiconductor device of claim 3, wherein the data storage structure includes:
first electrodes (see Yokoyama paragraph [0061] and Sharma Fig. 2A, capacitor storage structures contain a first electrode), each of the first electrodes being electrically connected to the second source/drain region of a corresponding one of the active layers, and the first electrodes being spaced apart from each other in the vertical direction (see Sharma Fig. 2A);
a second electrode covering the first electrodes (Sharma Fig. 2A); and
a dielectric layer between the first electrodes and the second electrode (Sharma Fig. 2A and known structure of a capacitor).
Allowable Subject Matter
Claims 5-7 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 5-6, the prior art, alone or in combination, fails to teach or suggest the second step portion includes second conductive patterns of the conductive connection patterns, the second conductive patterns being spaced apart from the first conductive patterns and electrically isolated in the first direction.
Regarding claim 7, the prior art, alone or in combination, fails to teach or suggest wherein in the second direction, each of the conductive connection patterns has a second maximum width greater than the first maximum width.
Regarding claim 10, the prior art, alone or in combination, fails to teach or suggest wherein on the connection region of the substrate, the first conductive connection pattern vertically overlaps the lower electrode layer and the upper electrode layer of the first gate electrode,
Claims 11-15 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 11-15, the prior art, alone or in combination, fails to teach or suggest a second conductive pattern at a vertical level the same as a vertical level of the first conductive pattern, spaced apart from the first conductive pattern in the first direction, and electrically isolated; in combination with the other limitations of the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/ Primary Examiner, Art Unit 2899
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