DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species B of Group I directed to Fig. 22A-22C (claims 1-17) in the reply filed on June 2nd, 2026 is acknowledged. The traversal is on the ground(s) that Figs. 9A-9C is in-process device to form final device in Figs. 22A-22C and not mutually exclusive from Species B. This is not found persuasive because there is no subsequence step showing that the contact opening fill structures 138 in Figs. 9C being removed to form openings 39 in Fig. 10C for making final device in Figs. 22A-22C. Therefore, Figs. 9A-9C is an alternative device from Figs. 22A-22C.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 12 recites “a vertical stack of second-tier annular insulating plates” in lines 2-3 without reciting a vertical stack of first-tier annular. It is unclear to the examiner how can the second-tier annular insulating plates being introduced into structure without having the first-tier annular insulating plates before.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 8, 10 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iino et al. (Pub. No.: US 2022/0262811 A1), hereinafter as Iino.
Regarding claim 1, Iino discloses a memory device in Fig. 22, comprising: a first-tier alternating stack (lower stack under the boundary BD) of first insulating layers (insulator layers 30 in lower stack) and first electrically conductive layers (conductor layers 40 in lower stack), wherein the first-tier alternating stack comprises a first staircase region (lower stepped section 220) having first stepped surfaces (see [0053], [0066-0067] and [0123-0124]); a first-tier retro-stepped dielectric material portion (lower insulator 80 under the boundary DB) overlying the first stepped surfaces (see [0067]); a second-tier alternating stack (upper stack over the boundary BD) of second insulating layers (insulator layers 30 in upper stack) and second electrically conductive layers (conductor layers 40 in upper stack) located over the first-tier alternating stack and the first-tier retro-stepped dielectric material portion, wherein the second-tier alternating stack comprises a second staircase region (upper stepped section 210) having second stepped surfaces (see [0053], [0069-0070] and [0123-0124]); a second-tier retro-stepped dielectric material portion (upper insulator 80 over the boundary DB) overlying the second stepped surfaces (see [0070]); memory stack structures (memory pillars 50) vertically extending through each layer within the first-tier alternating stack and through each layer within the second-tier alternating stack in a memory array region (stacked section 100) (see [0048]); and first-type layer contact via structures (some contacts 70) vertically extending through each layer within the second-tier alternating stack and through the first-tier retro-stepped dielectric material portion, wherein each of the first-type layer contact via structures contacts a respective one of the first electrically conductive layers (contacts 70 contacts conductor layers 40 in lower stack) (see [0050] and [0123-0126]).
Regarding claim 2, Iino discloses the memory device of claim 1, further comprising second-type layer contact via structures (some other contacts 70 in upper stack) vertically extending through the second-tier retro-stepped dielectric material portion, wherein each of the second-type layer contact via structures contacts a respective one of the second electrically conductive layers (see Fig. 22, [0050] and [0123-0126]).
Regarding claim 5, Iino discloses the memory device of claim 2, wherein each of the second-type layer contact via structures (contacts 70 has circular cross section) contact an annular top surface of the respective one of the second electrically conductive layers (see Figs. 4 and 22).
Regarding claim 8, Iino discloses the memory device of claim 2, wherein: each of the second-type layer contact via structures (contacts 70 in upper stack) is in contact with the second-tier retro-stepped dielectric material portion and does not contact the first-tier retro-stepped dielectric material portion; and each of the first-type layer contact via structures (some contacts 70 through upper stack and connecting to conductor layers 70) is in contact with the first-tier retro-stepped dielectric material portion and does not contact the second-tier retro-stepped dielectric material portion (see Fig. 22).
Regarding claim 10, Iino discloses the memory device of claim 1, wherein each of the first-type layer contact via structures (contacts 70 has circular cross section) contact an annular top surface of the respective one of the first electrically conductive layers (see Figs. 4 and 22).
Regarding claim 13, Iino discloses the memory device of claim 1, wherein: first vertical surface segments of the first stepped surfaces are laterally spaced apart along a first horizontal direction (y-direction) and are interconnected to each other by first horizontally-extending surface segments of the first stepped surfaces (in lower stepped section 220) (see Fig. 22); and second vertical surface segments of the second stepped surfaces are laterally spaced apart along the first horizontal direction and are interconnected to each other by second horizontally-extending surface segments of the second stepped surfaces (see Fig. 22).
Allowable Subject Matter
Claims 3-4, 6-7, 9, 11, and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: the cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Wherein the second-type layer contact via structures vertically extend through each layer within the first-tier alternating stack as recited in claim 3. Claim 4 depend on claim 3, and therefore also include said claimed limitation.
Wherein one of the second-type layer contact via structures contacts one of second electrically conductive layers and vertically extends through and is electrically isolated from each second electrically conductive layer that underlies said one of the second electrically conductive layers as recited in claim 6. Claim 7 depend on claim 6, and therefore also include said claimed limitation.
Wherein each of the first-type layer contact via structures vertically extend through an horizontal plane including a bottom surface of a bottommost layer within the first-tier alternating stack as recited in claim 9.
wherein: one of the first-type layer contact via structures contacts one of first electrically conductive layers and vertically extends through and is electrically isolation from each first electrically conductive layer that underlies said one of the first electrically conductive layers; and said each first electrically conductive layer that underlies said one of the first electrically conductive layers is contacted by an outer sidewall of a respective annular insulating plate that laterally surrounds and contacts said one of the first-type layer contact via structures as recited in claim 11.
Further comprising: a first lateral isolation trench fill structure that laterally extends along the first horizontal direction and comprises a first lengthwise sidewall that contacts a lengthwise sidewall of the first-tier retro-stepped dielectric material portion, wherein each layer within the first-tier alternating stack and within the second-tier alternating stack comprises a respective first sidewall that contacts the first lengthwise sidewall of the first lateral isolation trench fill structure; and a second lateral isolation trench fill structure that laterally extends along the first horizontal direction and comprises a second lengthwise sidewall that contacts a lengthwise sidewall of the second-tier retro-stepped dielectric material portion, wherein each layer within the second-tier alternating stack and within the second-tier alternating stack comprises a respective second sidewall that contacts the second lengthwise sidewall of the second lateral isolation trench fill structure as recited in claim 14. Claims 15-17 depend on claim 14, and therefore also include said claimed limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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