Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on March 25, 2024, September 05, 2024, and October 22, 2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 6, 8, 14, & 16 are objected to because of the following informalities:
In claim 6, “determining that the shared bus is short,” in ll. 4, should read “determining that the shared bus is shorted.”
In claim 8, “summing a plurality of threshold codes the vector over time,” in ll. 2-3, should read “summing a plurality of threshold codes of the vector over time.”
In claim 14, “determining that the shared bus is short,” in ll. 7, should read “determining that the shared bus is shorted.”
In claim 16, “summing a plurality of threshold codes the vector over time,” in ll. 2-3, should read “summing a plurality of threshold codes of the vector over time.”
Appropriate correction is required.
.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-8, & 11 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Zang et al (US 2021/0058168 A1, Pub. Date Feb. 25, 2021, hereinafter Zang).
Regarding Claim 1, Zang, teaches:
A method ([Abstract] & [0026]) comprising:
transmitting a pulse signal over a shared bus (Fig. 7; [0026], [0030], & [0078]-[0079]: block 704);
capturing an observed signal (Fig. 3A: 306), wherein the observed signal (Fig. 3A: 306) is a superimposition of the pulse signal (Fig. 3A: 302) and a reflection signal (Figs. 3A & 3B; [0041][-0042] & [0046]: 304 reflection signal);
comparing an amplitude of the observed signal to a plurality of threshold values (Figs. 4A & 7; [0051], [0053], [0055], [0076], [0082]-[0083], & [0086]: blocks 702, 710, & 712);
creating a vector indicating a given threshold at which the amplitude of the observed signal first exceeds one of the plurality of threshold values at a plurality of sampling times (Figs. 4A, 4B, & 5; [0049]-[0057], [0055], [0063]-[0064], & [0071]);
applying an indicator to the vector (Figs. 4A & 4B; [0050], [0053], [0057]-[0058], [0065], & [0071]);
and diagnosing the shared bus based on the indicator (Fig. 7; [0027], [0029], [0058], [0065], [0071], & [0085]: block 714).
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Regarding Claim 2, Zang, teaches:
The method of claim 1 ([Abstract] & [0026]), comprising:
measuring a time duration (Fig. 3A; 310) on the observed signal (Fig. 3A; 306) between the pulse signal (Fig. 3A; 302) and a transition of the observed signal (Fig. 3A; [0043]-[0044], [0046], & [0066]: 304 reflection signal interpreted as observed signal); and
determining a location of a shared bus fault based on the time duration (Fig. 3A; [0043]-[0044], [0046], [0066], & [0108]: 310 time duration).
Regarding Claim 3, Zang, teaches:
The method of claim 1 ([Abstract] & [0026]), wherein the indicator is a settled state indicator ([0044],[0057]-[0058], [0060], [0065]-[0066], & [0071]: “reflection array” r[n] is the computed indicator, its values (0, +1, -1) represent the final, processed stated of the signal after analysis, which is the settled state and diagnosis); and
diagnosing the shared bus includes comparing a predetermined sample of the vector to a pre-defined amplitude range ([0057]-[0058], [0061], [0065]-[0066], [0071], & [0076]: teaches diagnosis the bus (determining an ‘open’ or ‘short’ fault) by comparing the values (samples) of the vector r[n] to a pre-defined amplitude range, and specifies a predetermined sample for fault location, such as the “first non-zero element” in the vector).
Regarding Claim 4, Zang, teaches:
The method of claim 3 ([Abstract] & [0026]), wherein diagnosing the shared bus includes ([0002] & [0028]):
determining that the shared bus is terminated ([0028]-[0029], [0047], [0065]) when the predetermined sample of the vector ([0050]-[0058] & [0061]-[0066]) is within the pre-defined amplitude range ([0029], [0051]-[0056] & [0062]-[0064]);
determining that the shared bus is shorted ([0029], [0046], [0058], [0065]) when the predetermined sample of the vector ([0050]-[0058] & [0061]-[0066]) is below the pre-defined amplitude range ([0029], [0033], [0051]-[0056], [0058], & [0062]- [0065]); and
determining that the shared bus is open ([0029], [0042], [0058]) when the predetermined sample of the vector ([0050]-[0058] & [0061]-[0066]) is above the pre-defined amplitude range ([0030], [0051]-0056], [0058], & [0062]-[0065]).
Regarding Claim 7, Zang, teaches:
The method of claim 1 ([Abstract] & [0026]), wherein the indicator is a maximum amplitude indicator (Fig. 6; [0030], [0051], [0070]-[0071], & [0076]); and diagnosing the shared bus includes determining whether a plurality of consecutive samples of the vector are beyond a predetermined maximum amplitude (Figs. 4A & 4B; [Abstract], [0028], [0030], [0042], [0051]-[0058], [0065], & [0070]-[0071]: discloses diagnosing the bus by analyzing a vector (r[n]) and determining that a fault condition exists where there are a plurality of consecutive samples in that vector that are non-zero (+1 or -1), which is the result of the observed signal samples being “beyond a predetermined maximum amplitude”).
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Regarding Claim 8, Zang, teaches:
The method of claim 1 ([Abstract] & [0026]), wherein the indicator is a voltage sum indicator (Figs. 4A & 4B; [0049], [0057]-[0058], [0065], [0071],& [0097]: fault detection logic 510 interpreted as a “voltage sum indicator”); and
diagnosing the shared bus includes summing a plurality of threshold codes the vector over time (Figs. 4A & 4B; [0042], [0049]-[0058], [0062]-[0065], & [0071]: matrix 420 in the figures further illustrate the vectors a[n], b[n], c[n] as rows of data across the sampling times T1-T8) and comparing the sum to a predetermined threshold ([0058], [0065]-[0066], & [0071]).
Regarding Claim 11, Zang, teaches:
The method of claim 1 ([Abstract] & [0026]), comprising determining a fault type (Fig. 7; [0028]-[0029], [0058], [0065], & [0071]: Block 714).
Claims 12-13 & 15-16 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Zang et al (US 2021/0058168 A1, Pub. Date Feb. 25, 2021, hereinafter Zang).
Regarding Claim 12, Zang, teaches:
An apparatus (Fig. 5; [0040], [0068]-[0071]: PHY 500 (apparatus)) comprising:
a control circuit to (Fig. 5; [0068]-[0071]: controller 506 and more specifically Fault Detection Logic 510):
receive a plurality of sequences of bits (Fig. 4A; [0071]: a[n], b[n], c[n], etc. are the sequences of bits), wherein a given one of the plurality of sequences of bits is indicative of an amplitude of the observed signal (Fig. 3A: 306) compared to a given one of a plurality of threshold values at a plurality of sampling times (Figs. 4A, 4B, & 5; [0051]-[0058], [0062]-[0066], & [0071]: control circuit receives multiple sequences of bits, each sequence corresponds to the observed signal’s amplitude compared to a specific threshold at multiple sampling times);
creating a vector based on the plurality of sequences of bits ([0057]-[0058]: matrix 420), wherein the vector indicates (Fig. 4A; [0057]-[0058] & [0071]), for a given one of the plurality of sampling times ([0049]-[0058]), a first threshold of the plurality of threshold values at which the amplitude of the observed signal (Fig. 3A: 306) exceeds one of the plurality of threshold values (Figs. 4A & 4B; [0049]-[0058] & [0071]: control circuit creates a vector that indicates, for each sampling time, which threshold exceeded);
apply an indicator to the vector (Figs. 4A & 4B; [0058], [0065], & [0071]: fault detection logic 510 generates a signal FS (the indicator) based on array r[n]); and
diagnose a shared bus based on the indicator ([0028], [0058], [0065], & [0071]: Block Figs. 4A, 4B, & 7; Block 714).
Regarding Claim 13, Zang, teaches:
The apparatus of claim 12 (Fig. 5; [0040], [0068]-[0071]), wherein the indicator is a settled state indicator ([0044],[0057]-[0058], [0060], [0065]-[0066], & [0071]: “reflection array” r[n] is the computed indicator, its values (0, +1, -1) represent the final, processed stated of the signal after analysis, which is the settled state and diagnosis); and the control circuit diagnoses the shared bus by ([0002], [0028], [0057-[0058] & [0071]):
comparing a predetermined sample of the vector to a pre-defined amplitude range ([0057]-[0058], [0061], [0065]-[0066], & [0076]: teaches diagnosing the bus (determining an ‘open’ or ‘short’ fault) by comparing the values (samples) of the vector r[n] to a pre-defined amplitude range, and specifies a predetermined sample for fault location, such as the “first non-zero element” in the vector);
determining that the shared bus is terminated ([0028]-[0029], [0047], [0065]) when the predetermined sample of the vector ([0050]-[0058] & [0061]-[0066]) is within the pre-defined amplitude range ([0029], [0051]-[0056], & [0062]-[0065]);
determining that the shared bus is shorted ([0029], [0046], [0058], [0065]) when the predetermined sample of the vector ([0050]-[0058] & [0061]-[0066]) is below the pre-defined amplitude range ([0029], [0033], [0051]-[0056], [0058], & [0062]- [0065]); and
determining that the shared bus is open ([0029], [0042], [0058]) when the predetermined sample of the vector ([0050]-[0058] & [0061]-[0066]) is above the pre-defined amplitude range ([0030], [0051]-0056], [0058], & [0062]-[0065]).
Regarding Claim 15, Zang, teaches:
The apparatus of claim 12 (Fig. 5; [0040], [0068]-[0071]), wherein the indicator is a maximum amplitude indicator (Fig. 6; [0030], [0051], [0070]-[0071], & [0076]); and the control circuit ([0051] & [0071]: fault detection logic 510) diagnoses the shared bus by determining whether a plurality of consecutive samples of the vector are beyond a predetermined maximum amplitude (Figs. 4A & 4B; [Abstract], [0028], [0030], [0042], [0051]-[0058], [0065], & [0070]-[0071]: discloses diagnosing the bus by analyzing a vector (r[n]) and determining that a fault condition exists where there are a plurality of consecutive samples in that vector that are non-zero (+1 or -1), which is the result of the observed signal samples being “beyond a predetermined maximum amplitude”).
Regarding Claim 16, Zang, teaches:
The apparatus of claim 12 (Fig. 5; [0040], [0068]-[0071]), wherein the indicator is a voltage sum indicator (Figs. 4A & 4B; [0049], [0057]-[0058], [0065], [0071],& [0097]: fault detection logic 510 interpreted as a “voltage sum indicator”); and the control circuit diagnoses the shared bus by summing a plurality of threshold codes the vector over time (Figs. 4A & 4B; [0042], [0049]-[0058], [0062]-[0065], & [0071]: matrix 420 in the figures further illustrate the vectors a[n], b[n], c[n] as rows of data across the sampling times T1-T8) and comparing the sum to a predetermined threshold ([0058], [0065]-[0066], & [0071]).
Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Zang et al (US 2021/0058168 A1, Pub. Date Feb. 25, 2021, hereinafter Zang).
Regarding Claim 19, Zang, teaches:
A system comprising (Fig. 1; [0037]-[0040] & [0068]: network 100 (a system)):
a shared bus (Figs. 1, 2, & 5; [0037]-[0040] & [0068]: bus 104/504 );
a transceiver coupled to the shared bus (Figs. 1 & 2; [0040] & [0068]: transmit circuitry 502 (transceiver), communication bus 104/504), the transceiver ([0040] & [0068]) to:
transmit a pulse signal over a shared bus (Figs. 1, 2, & 7; [0030], ][0040], [0051], [0068], & [0071]: transmit circuitry 502 (“transceiver”), Block 704);
capture an observed signal, wherein the observed signal is a superimposition of the pulse signal and a reflection signal (Figs. 3A & 7; [0041]-[0042], [0046]: observed signal 306, transmit pulse signal 302, reflection signal 304, Block 706);
compare an amplitude of the observed signal to a plurality of threshold values ([0030], [0051], [0053], [0055], & [0070]); and output a sequence of bits indicative of an amplitude of an observed signal compared to a plurality of threshold values at a given sampling time (Fig. 4A; [0052], [0054], [0056], [0070]: comparator conveys a signal det_out, which is a logic value indicative of the amplitude comparison for each sampling time); and
a control circuit coupled to the transceiver (Figs. 4A, 4B, & 5; [0069] & [0071]: controller 506 (control circuit), transmit circuitry 502 (transceiver) ), the control circuit to (Fig. 5: controller 506):
receive a plurality of sequences of bits, wherein a given one of the plurality of sequences of bits is indicative of an amplitude of the observed signal compared to a given one of a plurality of threshold values at a plurality of sampling times (Figs. 4A & 4B; [0069]-[0071]);
creating a vector based on the plurality of sequences of bits, wherein the vector indicates, for a given one of the plurality of sampling times, a first threshold of the plurality of threshold values at which the amplitude of the observed signal exceeds one of the plurality of threshold values (Figs. 4A & 4B; [0057]-[0058] & [0071]);
apply an indicator to the vector (Figs. 4A & 4B; [0058], [0065]-[0066], [0071]: indicator is the presence and sign (positive/negative) of the non-zero values and signal FS in r[n]); and diagnose a shared bus based on the indicator (Figs. 4A, 4B, & 7; [0058], [0065]-[0066], [0071]: determine the fault condition (open, short, normal) and its locations based on the analysis vector, Block 714).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 & 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al (US 2021/0058168 A1, Pub. Date Feb. 25, 2021, hereinafter Zang), in view of Spillane et al. (US 5420512, Pat. Date. May 30, 1995, hereinafter Spillane).
Regarding Claim 5, Zang, teaches:
The method of claim 1 ([Abstract] & [0026]),
Zang, is silent in regard to:
wherein the indicator is a significant slope indicator; and diagnosing the shared bus includes determining whether a slope of the vector has multiple portions above a predetermined threshold.
However, Spillane, further teaches:
wherein the indicator is a significant slope indicator (Figs. 2 & 3; [Abstract], [Col. 1, ll. 15-17], [Col. 3, ll. 54-62], [Col. 5, ll. 57-60], [Col. 7, ll.54-67], [Col. 8, ll. 1-2], & [Col. 9, ll. 31-35]: The “SLOPE” signal (UI3-4 in Fig. 3) is a direct “slope indicator”); and diagnosing the shared bus includes determining whether a slope of the vector has multiple portions above a predetermined threshold (Figs. 2 & 3; [Col. 3, ll. 45-62], [Col. 5, ll. 57-60], [Col. 6, ll. 1-8], [Col. 7, ll.54-67], [Col. 10, ll. 22-35]: system uses a slope detector circuit (90) to measure slop for identifying wires, slope detector means (90) provides signals (CHK SLP and SLOPE) to indicate slope polarity, where the component itself is a slope detector means (90)).
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It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the indicator as a significant slope indicator and diagnosing the shared bus to determine whether a slope of the vector has multiple portions above a predetermined threshold, of Spillane to Zang, in order to attain and improve, by integrating the slope detector means (90) of Spillane into the TDR sampling system of Zang, that would involve replacing Zang’s amplitude comparison-derived fault indicator with Spillane’s slope indicator to determine whether the slope indicator is active for multiple consecutive sampling times defined by the length of the vector (r[n]), providing an explicit pulse-shape characterization in Spillane, achieving to the claimed invention with predictable results (KSR).
Regarding Claim 6, Zang, teaches:
The method of claim 5 ([Abstract] & [0026]), wherein diagnosing the shared bus includes ([0002] & [0028]):
determining that the shared bus is terminated (Fig. 3C; [0029, [0047], & [0065])
determining that the shared bus is short (Fig. 4B; [0029, [0046], &[0065])
determining that the shared bus is open (Fig. 4A; [0029], [0042], [0058], & [0065])
Zang, is silent in regard to:
when the slope of the vector has one portion above the predetermined threshold;
when the slope of the vector has two portions above the predetermined threshold, a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is negative; and
when the slope of the vector has two portions above the predetermined threshold, a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is positive.
However, Spillane, further teaches:
when the slope of the vector has one portion above the predetermined threshold ([Col. 3, 54-62],[Col. 1, ll. 15-17], [Col. 7, ll. 50-68], & [Col. 8, ll. 1-2]);
when the slope of the vector has two portions above the predetermined threshold (Figs. 2 & 3; [Col. 7, ll. 45-68], & [Col. 8, ll. 1-2]), a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is negative (Figs. 2 & 3; [Col. 7, ll. 45-68], & [Col. 8, ll. 1-2]); and
when the slope of the vector has two portions above the predetermined threshold (Figs. 2 & 3; [Col. 7, ll. 45-68], & [Col. 8, ll. 1-2]), a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is positive (Figs. 2 & 3; [Col. 7, ll. 45-68], & [Col. 8, ll. 1-2]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the slope of the vector has one portion above the predetermined threshold (terminated bus); when the slope of the vector has two portions above the predetermined threshold, a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is negative (bus is shorted), and a slope of the vector has two portions above the predetermined threshold, a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is positive (bus is open), of Spillane to Zang, in order to attain and improve, by integrating the slope-based discrimination technique of Spillane into the fault detection logic (TDR fault classification method) of Zang, enhancing Zang’s system by programing it to not only note the polarity of the reflection vector, but to further analyze its slope characteristics and enhance its fault discrimination (fault detection logic 510), a known parameter from Spillane, to determine an “open” fault when the slope is positive where there are two slope portions of the same polarity, and a “short” fault when the slope is negative, identifying a short when there are two slope portions of opposite polarity, the “terminated” condition is disclosed by Zang as the absence of a reflection (a vector with no significant portions), where one of skill in the art would understand corresponds to a signal lacking the slop transitions indicative of a fault, therefore achieving to the claimed invention and purpose, with predictable results (KSR).
Regarding Claim 9, Zang, teaches:
The method of claim 1 ([Abstract] & [0026]),
Zang, is silent in regard to:
wherein the indicator is a gradient indicator; and
diagnosing the shared bus includes analyzing a slope of a droop of the vector to determine whether the slope of the droop exceeds a predetermined threshold.
However, Spillane, further teaches:
wherein the indicator is a gradient indicator (Fig. 8; [Abstract], [Col. 3, ll. 54-62], [Col. 4, ll. 56-60], [Col. 5, ll. 57-60], & [Col. 7, ll. 50-68]: a slope is the mathematical definition of a gradient); and
diagnosing the shared bus includes analyzing a slope of a droop of the vector to determine whether the slope of the droop exceeds a predetermined threshold (Figs. 2 & 3; [Col. 3, ll. 54-62], [Col. 4, ll. 55-60], [Col. 5, ll. 57-68]: slope is a measured value used for identification).
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It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the indicator is a gradient indicator; and diagnosing the shared bus includes analyzing a slope of a droop of the vector to determine whether the slope of the droop exceeds a predetermined threshold, of Spillane to Zang, in order to attain and improve, by integrating Zang’s diagnosing cable faults within a network (e.g., a 10SPE network) using time-domain reflectometry, providing the method of transmitting a pulse, observing a signal, sampling it, and determining a fault condition based on the amplitude of the samples and a derived vector, to improve the system, would incorporate Spillane’s electronic cable testing that provides a robust method for identifying faults and crossovers, teaching the slope of a signal is a valuable and effective diagnostic parameter for cable faults, Spillane’s system using a differential amplifier and a slope detector means to determine the slop at signal transition points (“droops”) as one of three key variables (pulse width, cycle length and slope) to identify wire conditions, replacing Zang’s analysis of the reflection vector’s r[n] positive/negative state with Spillane’s slope analysis technique would be and obvious design choice to configure the fault detection logic (Zang 510) to calculate or detect (acting as a gradient indicator) the slope of the signal droop/transition (taught by Spillane) and compare it to a predetermined threshold for an improved diagnostic decision, therefore achieving to the claimed invention and purpose, with predictable results (KSR).
Regarding Claim 10, Zang, teaches:
The method of claim 1 ([Abstract] & [0026]),
Zang, is silent in regard to:
wherein the indicator is a localized slope indicator; and
diagnosing the shared bus includes analyzing a slope of the vector at a predetermined location to determine whether the slope exceeds a predetermined threshold.
However, Spillane, further teaches:
wherein the indicator is a localized slope indicator (Figs. 3 & 9; [Abstract], [Col. 3, ll. 45-62], [Col. 5, ll. 57-60], [Col. 7, ll. 50-68], & [Col. 8, ll. 1-2]: Fig. 3 further illustrates slope detection, Fig. 9 illustrates “Slope Detector Means 90” as a distinct component in the system); and
diagnosing the shared bus includes analyzing a slope of the vector at a predetermined location to determine whether the slope exceeds a predetermined threshold (Figs. 2 & 3; [Col. 3, ll. 45-62], [Col. 5, ll. 51-68], [Col. 7, ll. 50-68], & [Col. 8, ll. 1-2]).
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It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the indicator is a localized slope indicator; and diagnosing the shared bus includes analyzing a slope of the vector at a predetermined location to determine whether the slope exceeds a predetermined threshold, of Spillane to Zang, in order to attain and improve, by integrating Spillane’s slope detection technology into Zang’s TDR system, to include a ”slope indicator” and to “analyze a slope of the vector at a predetermined location”, the combined methods would analyze the slop of the signal (the vector) at the exact time determined by Zang’s fault location analysis to confirm whether the slope exceeds the threshold set by the slope detector (Spillane), therefore achieving to the claimed invention, with expected predictable results (KSR).
Claims 14 & 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al (US 2021/0058168 A1, Pub. Date Feb. 25, 2021, hereinafter Zang), in view of Spillane et al. (US 5420512, Pat. Date. May 30, 1995, hereinafter Spillane).
Regarding Claim 14, Zang, teaches:
The apparatus of claim 12 (Fig. 5; [0040]-[0041], [0068]-[0071]),
and the control circuit diagnoses the shared bus by (Figs. 4A & 4B; [0057]):
determining that the shared bus is terminated (Fig. 3C; [0029, [0047], & [0065])
determining that the shared bus is short (Fig. 4B; [0029, [0046], &[0065])
determining that the shared bus is open (Fig. 4A; [0029], [0042], [0058], & [0065])
Zang, is silent in regard to:
wherein the indicator is a significant slope indicator;
determining whether a slope of the vector has multiple portions above a predetermined threshold;
when the slope of the vector has one portion above the predetermined threshold;
when the slope of the vector has two portions above the predetermined threshold, a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is negative; and
when the slope of the vector has two portions above the predetermined threshold, a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is positive.
However, Spillane, further teaches:
wherein the indicator is a significant slope indicator (Figs. 2 & 3; [Abstract], [Col. 1, ll. 15-17], [Col. 3, ll. 54-62], [Col. 5, ll. 57-60], [Col. 7, ll.54-67], [Col. 8, ll. 1-2], & [Col. 9, ll. 31-35]: The “SLOPE” signal (UI3-4 in Fig. 3) is a direct “slope indicator”);
determining whether a slope of the vector has multiple portions above a predetermined threshold (Figs. 2 & 3; [Col. 3, ll. 45-62], [Col. 5, ll. 57-60], [Col. 6, ll. 1-8], [Col. 7, ll.54-67], [Col. 10, ll. 22-35]: system uses a slope detector circuit (90) to measure slop for identifying wires, slope detector means (90) provides signals (CHK SLP and SLOPE) to indicate slope polarity, where the component itself is a slope detector means (90));
when the slope of the vector has one portion above the predetermined threshold ([Col. 3, 54-62],[Col. 1, ll. 15-17], [Col. 7, ll. 50-68], & [Col. 8, ll. 1-2]);
when the slope of the vector has two portions above the predetermined threshold (Figs. 2 & 3; [Col. 7, ll. 45-68], & [Col. 8, ll. 1-2]), a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is negative (Figs. 2 & 3; [Col. 7, ll. 45-68], & [Col. 8, ll. 1-2]); and
when the slope of the vector has two portions above the predetermined threshold (Figs. 2 & 3; [Col. 7, ll. 45-68], & [Col. 8, ll. 1-2]), a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is positive (Figs. 2 & 3; [Col. 7, ll. 45-68], & [Col. 8, ll. 1-2]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the indicator is a significant slope indicator, the slope of the vector has one portion above the predetermined threshold (terminated bus); when the slope of the vector has two portions above the predetermined threshold, a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is negative (bus is shorted), and a slope of the vector has two portions above the predetermined threshold, a slope of a first portion above the predetermined threshold is positive and a slope of a second portion above the predetermined threshold is positive (bus is open), of Spillane to Zang, in order to attain and improve, by integrating the slope-based discrimination technique of Spillane into the fault detection logic (TDR fault classification method) of Zang, enhancing Zang’s system by programing it to not only note the polarity of the reflection vector, but to further analyze its slope characteristics and enhance its fault discrimination (fault detection logic 510), a known parameter from Spillane, to determine an “open” fault when the slope is positive where there are two slope portions of the same polarity, and a “short” fault when the slope is negative, identifying a short when there are two slope portions of opposite polarity, the “terminated” condition is disclosed by Zang as the absence of a reflection (a vector with no significant portions), where one of skill in the art would understand corresponds to a signal lacking the slop transitions indicative of a fault, therefore achieving to the claimed invention and purpose, with predictable results (KSR).
Regarding Claim 17, Zang, teaches:
The apparatus of claim 12 (Fig. 5; [0030]-[0035], [0050]-[0059], & [0071]),
Zang, is silent in regard to:
wherein the indicator is a gradient indicator; and
the control circuit diagnoses the shared bus by analyzing a slope of a droop of the vector to determine whether the slope of the droop exceeds a predetermined threshold.
However, Spillane, further teaches:
wherein the indicator is a gradient indicator (Fig. 8; [Abstract], [Col. 3, ll. 54-62], [Col. 4, ll. 56-60], [Col. 5, ll. 57-60], & [Col. 7, ll. 50-68]): a slope is the mathematical definition of a gradient); and
the control circuit diagnoses the shared bus by analyzing a slope of a droop of the vector to determine whether the slope of the droop exceeds a predetermined threshold (Figs. 2 & 3; [Col. 3, ll. 45-62], [Col. 4, ll. 55-60], [Col. 5, ll. 51-68]: slope is a measured value used for identification).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the indicator is a gradient indicator; and the control circuit diagnosing the shared bus by analyzing a slope of a droop of the vector to determine whether the slope of the droop exceeds a predetermined threshold, of Spillane to Zang, in order to attain and improve, by integrating Zang’s diagnosing cable faults within a network (e.g., a 10SPE network) using time-domain reflectometry, providing the method of transmitting a pulse, observing a signal, sampling it, and determining a fault condition based on the amplitude of the samples and a derived vector, to improve the system, would incorporate Spillane’s electronic cable testing that provides a robust method for identifying faults and crossovers, teaching the slope of a signal is a valuable and effective diagnostic parameter for cable faults, Spillane’s system using a differential amplifier and a slope detector means to determine the slop at signal transition points (“droops”) as one of three key variables (pulse width, cycle length and slope) to identify wire conditions, replacing Zang’s analysis of the reflection vector’s r[n] positive/negative state with Spillane’s slope analysis technique would be and obvious design choice to configure the fault detection logic (Zang 510) to calculate or detect the slope (acting as a gradient indicator) of the signal droop/transition (taught by Spillane) and compare it to a predetermined threshold for an improved diagnostic decision, therefore achieving to the claimed invention and purpose, with predictable results (KSR).
Regarding Claim 18, Zang, teaches:
The apparatus of claim 12 (Fig. 5; [Abstract], [0030]-[0035], [0050]-[0059], & [0071]),
Zang, is silent in regard to:
wherein the indicator is a localized slope indicator; and
the control circuit diagnoses the shared bus by analyzing a slope of the vector at a predetermined location to determine whether the slope exceeds a predetermined threshold.
However, Spillane, further teaches:
wherein the indicator is a localized slope indicator (Figs. 3 & 9; [Abstract], [Col. 3, ll. 45-62], [Col. 5, ll. 57-60], [Col. 7, ll. 50-68], & [Col. 8, ll. 1-2]: Fig. 3 further illustrates slope detection, Fig. 9 illustrates “Slope Detector Means 90” as a distinct component in the system); and
the control circuit diagnoses the shared bus ([Col. 5, ll. 50-68]) by analyzing a slope of the vector at a predetermined location to determine whether the slope exceeds a predetermined threshold (Figs. 2 & 3; [Col. 3, ll. 45-62], [Col. 5, ll. 51-68], [Col. 7, ll. 50-68], & [Col. 8, ll. 1-2]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the indicator is a localized slope indicator and the control circuit diagnosing the shared bus by analyzing a slope of the vector at a predetermined location to determine whether the slope exceeds a predetermined threshold, of Spillane to Zang, in order to attain and improve, by integrating Spillane’s slope detection technology into Zang’s TDR system, to include a ”slope indicator” and to “analyze a slope of the vector at a predetermined location”, the combined methods would analyze the slope of the signal (the vector) at the exact time determined by Zang’s fault location analysis to confirm whether the slope exceeds the threshold set by the slope detector (Spillane), therefore achieving to the claimed invention, with expected predictable results (KSR).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zang et al (US 2021/0058168 A1, Pub. Date Feb. 25, 2021, hereinafter Zang), in view of Spillane et al. (US 5420512, Pat. Date. May 30, 1995, hereinafter Spillane).
Regarding Claim 20, Zang, teaches:
The system of claim 19 (Fig. 1; [0037]-[0040] & [0068]), wherein the indicator is a settled state indicator ([0044],[0057]-[0058], [0060], [0065]-[0066], & [0071]: “reflection array” r[n] is the computed indicator, its values (0, +1, -1) represent the final, processed stated of the signal after analysis, which is the settled state and diagnosis), a maximum amplitude indicator (Fig. 6; [0030], [0051], [0070]-[0071], & [0076]), a voltage sum indicator (Figs. 4A & 4B; [0049], [0057]-[0058], [0065], [0071],& [0097]: fault detection logic 510 interpreted as a “voltage sum indicator”),
Zang, is silent in regard to:
a significant slope indicator, a gradient indicator, or a localized slope indicator.
However, Spillane, further teaches:
a significant slope indicator (Figs. 2 & 3; [Abstract], [Col. 1, ll. 15-17], [Col. 3, ll. 54-62], [Col. 5, ll. 57-60], [Col. 7, ll.54-67], [Col. 8, ll. 1-2], & [Col. 9, ll. 31-35]: The “SLOPE” signal (UI3-4 in Fig. 3) is a direct “slope indicator”), a gradient indicator (Fig. 8; [Abstract], [Col. 3, ll. 54-62], [Col. 4, ll. 56-60], [Col. 5, ll. 57-60], & [Col. 7, ll. 50-68]: a slope is the mathematical definition of a gradient), or a localized slope indicator (Figs. 3 & 9; [Abstract], [Col. 3, ll. 45-62], [Col. 5, ll. 57-60], [Col. 7, ll. 50-68], & [Col. 8, ll. 1-2]: Fig. 3 further illustrates slope detection, Fig. 9 illustrates “Slope Detector Means 90” as a distinct component in the system).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the indicator is a significant slope indicator, a gradient indicator, or a localized slope indicator, of Spillane to Zang, in order to attain and improve, by integrating Zang’s system that provides the complete TDR architecture capable of time-locked diagnosis using sampled amplitude data, addressing the settled state, maximum amplitude, and voltage sum indicators, where Spillane teaches the utility and structure of a slope detector means (90) to characterize signals in a cable testing environment, integrating Spillane’s slope detection capability into Zang’s TDR system, to provide a slope (significant or localized)/gradient indicator for the time-domain vector analysis, therefore rendering all claimed indicators obvious (KSR).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Biham et al. (US2020/0403825A1) discloses message authentication based on a physical location on a bus. Graube (US4739276) discloses a method and apparatus for digital time domain reflectometry. Leuer et al. (W)2017005697A) discloses a separating device and method for detecting a material accumulation in such a separating device.
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/HUGO NAVARRO/ Examiner, Art Unit 2858 10/17/2025
/PARESH PATEL/Primary Examiner, Art Unit 2858 October 20, 2025