DETAILED ACTION
This application, 18/590,242, attorney docket 2104048C1/1173-727C, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to QUALCOMM Incorporated, is a continuation of 17478539, filed 09/17/2021, now U.S. Patent # 11942414. Applicant’s election of group I, claims 1-15 in the response filed 5/27/2026 is acknowledged. Applicant traverses the restriction on the grounds that the restriction did not distinguish a different method from claim 16 because the order of formation of the layers is not claimed. Examiner disagrees. Claim 16 recites, “…forming an overlying interconnect layer on the underlying interconnect layer…” which defines the order of formation because the underlying layer must exist before the overlying layer can be formed on it. Therefore, restriction is proper and is made final. Claims 16-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-15 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 2 is rejected under 35 U.S.C. 112(a) because the specification, while being enabling for a thin layer that acts as a via between orthogonal lines, does not reasonably provide enablement for every possible configuration of connection between lines beside a via. Claims 3 recites, “not comprising a via layer disposed between the overlying interconnect layer and the underlying interconnect layer.” The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims. One skilled is a device design engineer, and the disclosure does not give him fair notice of what structures are comprehended by the claims so he can avoid infringement.
Claim Objections
Claims 1 and 5 recite, “extending in a second horizontal direction parallel to the first horizontal direction” If the directions are parallel, they are the same so a second direction is unnecessary and creates confusion.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 8-11 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Kohyama (U.S. 5,616,961).
As for claim 1,
Kohyama teaches in figure 4 and 9B integrated circuit (IC), comprising:
an underlying interconnect layer, comprising:
a first underlying metal line (12-1) extending in a first horizontal direction; and
a second underlying metal line (12-2) extending in a second horizontal direction parallel to the first horizontal direction;
an overlying interconnect layer disposed adjacent to the underlying interconnect layer in a vertical direction orthogonal to the first horizontal direction and the second horizontal direction, the overlying interconnect layer comprising a first overlying metal line (16-1) extending in a third horizontal direction orthogonal to the first horizontal direction;
the first overlying metal line intersects the first underlying metal line in the vertical direction in a first connection region (overlaps shown in figure 4);
the first overlying metal line intersects the second underlying metal line in the vertical direction in a second connection region (overlaps shown in figure 4);
and the first overlying metal line directly coupled to the first underlying metal line in the first connection region (at 14); and
a first insulating layer (13) disposed between the first overlying metal line and the second underlying metal line in the second connection region.
As for claim 2,
Kohyama teaches the IC of claim 1, ant teaches a first surface of the overlying interconnect layer adjacent to the underlying interconnect layer is disposed directly in contact with a first surface of the underlying interconnect layer adjacent to the overlying interconnect layer. (shown in figure 9B).
As for claim 3,
Kohyama teaches the IC of claim 1, not comprising a via layer disposed between the overlying interconnect layer and the underlying interconnect layer. (the metal lines 12 and 16 are directly connected without an intervening metal layer, as defined in paragraph [0049] of the instant application.
As for claim 4,
Kohyama teaches the IC of claim 1, and teaches in figure 10 that the first overlying metal line further extends horizontally from the first connection region in the first horizontal direction of the first underlying metal line.
As for claim 8,
Kohyama teaches the IC of claim 1, and teaches
the first overlying metal line comprises a first recess adjacent to the second connection region; and the first insulating layer is disposed in the first recess of the first overlying metal line to insulate the first overlying metal line from the second underlying metal line. (the line has a portion that is above an insulation layer adjacent to the connection point, so meets the requirements of the product by process limitation).
As for claim 9,
Kohyama teaches the IC of claim 1, wherein the first overlying metal line comprises a first recess adjacent to the second connection region and the first insulating layer is disposed in the first recess of the first overlying metal line to insulate the first overlying metal line from the second underlying metal line (line 16-1 has a portion that is above an insulation layer adjacent to the connection point and above the second line, so meets the requirements of the product by process limitation).
the second overlying metal line comprises a second recess adjacent to the fourth connection region and the second insulating layer is disposed in the second recess of the second overlying metal line to insulate the second overlying metal line from the first underlying metal line. (line 16-2 has a portion that is above an insulation layer adjacent to the connection point and above the second line, so meets the requirements of the product by process limitation).
As for claim 10,
Kohyama teaches the IC of claim 1, wherein the first overlying metal line comprises a first recess outside of the first connection region and the first insulating layer is disposed in the first recess of the first overlying metal line to insulate the first overlying metal line from the second underlying metal line. (line 16-1 has a portion that is above an insulation layer adjacent to the connection point and above the second line, so meets the requirements of the product by process limitation).
As for claim 11,
Kohyama teaches the IC of claim 1 wherein the first overlying metal line comprises a first recess outside of the first connection region the first insulating layer is disposed in the first recess of the first overlying metal line to insulate the first overlying metal line from the second underlying metal line. (line 16-1 has a portion that is above an insulation layer adjacent to the connection point and above the second line, so meets the requirements of the product by process limitation).,
the second overlying metal line comprises a second recess outside the third connection region; and the second insulating layer is disposed in the second recess of the second overlying metal line to insulate the second overlying metal line from the first underlying metal line. (line 16-2 has a portion that is above an insulation layer adjacent to the connection point and above the second line, so meets the requirements of the product by process limitation).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kohyama.
As for claim 5,
Kohyama teaches the IC of claim 1, wherein the overlying interconnect layer further comprises a second overlying metal line (106.2) extending a fourth horizontal direction parallel to the third horizontal direction,
the second overlying metal line intersects the second underlying metal line in the vertical direction in a third connection region;
the second overlying metal line intersects the first underlying metal line in the vertical direction in a fourth connection region (shown in figure 4).
and a second insulating layer (13) is disposed between the second overlying metal line and the first/ underlying metal line in the fourth connection region.
Kohyama does not teach that he second overlying metal line is directly coupled to the second underlying metal line in the third connection region,
However, adding an add Kohyama teaches the additional connection is a duplication of parts and would have been obvious to one skilled to provide connection to a bigger circuit.
The court has held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. In re Harza establishes "a mere duplication of parts has no patentable significance unless a new and unexpected result is produced." 274 F.2d 669, 124 USPQ 378 (CCPA 1960); See, MPEP 2144.04 (VI)(C).Here, the applicant has not disclosed any unexpected results, and the additional regions merely expand the capacity of the device. Therefore, it would have been obvious to one skilled in the art at the invention was made to add the additional subregions.
As for claim 6,
Kohyama makes obvious the IC of claim 5, and makes obvious
the first overlying metal line further extends horizontally from the first connection region in the first horizontal direction of the first underlying metal line; and
the second overlying metal line further extends horizontally from the third connection region in the second horizontal direction of the second underlying metal line. (figure 9B shows the first lines extending in the same direction adding additional lines extending in the same directions is obvious because it is a duplication of parts, see claim 5.
As for claim 12,
Kohyama teaches the IC of claim 1, but does not teach a power distribution network (PDN), comprising the first underlying metal line comprising a first power rail of the PDN; and the second underlying metal line comprising a second power rail of the PDN, wherein a supply voltage of the PDN comprises a voltage differential between the first power rail and the second power rail.
However, using the lines to provide separate voltages to the circuit is an intended use and would have been obvious to one skilled because the reason to build a multi-conductor interconnect is solely to provide different voltages or signals.
As for claim 15,
Kohyama teaches IC of claim 1 and makes obvious that integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.
The devices are a wide selection of electronic devices that require an IC that minimizes IC size and weight, and it would have been obvious to one skilled to use the device on Kohyama in one of the group of devices listed above.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kohyama in view of Yang et al (U.S. 2019/0237366).
As for claim 7,
Kohyama teaches the IC of claim 1, but does not teach a metal barrier layer disposed between the first underlying metal line and the first overlying metal line in the first connection region, the metal barrier layer electrically coupling the first underlying metal line to the first overlying metal line in the first connection region.
However, Yang teaches in figure 2 forming a barrier layer (24) between metal lines 16 and 26.
It would have been obvious to one skilled in the art at the effective filing date of this application to add the barrier of Yang to Kohyama to prevent metal diffusion into the semiconductor or insulation layers. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kohyama in view of Chen et al. (U.S. 2022/0384344).
As for claim 13,
Koyama teaches the IC of claim 1, and teaches in figure 16a-16c, a front-end-of-line (FEOL) structure (DRAM with buried strap), comprising:
a substrate 30 ; and an active semiconductor layer (n-well 32) disposed on the substrate on a front side of the FEOL structure;
But does not teach a back side interconnect structure on a back side of the FEOL structure and adjacent to the active semiconductor layer, the back side interconnect structure comprising the underlying interconnect layer; and the overlying metallization layer disposed adjacent to the underlying interconnect layer.
However, Chen teaches in figure 2 a back side interconnect structure (204) on a back side of the FEOL structure (102) and adjacent to the active semiconductor layer (200), the back side interconnect structure comprising the underlying interconnect layer; and the overlying metallization layer disposed adjacent to the underlying interconnect layer.
It would have been obvious to one skilled in the art at the effective filing date of this application use the interconnect structure of Koyama on the backside of the device to improve device density and reduce backside metal thickness. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 14,
Kohyama in view of Chen makes obvious the IC of claim 13, and in the combination, Chen teaches the underlying interconnect layer comprises:
an insulating layer (110); and the substrate is disposed between the active semiconductor layer and the insulating layer;
and Kohyama makes obvious that the first underlying metal line comprises a first buried metal line disposed in a semiconductor substrate and the insulating layer in the vertical direction;
and the second underlying metal line comprises a second buried metal line disposed in the semiconductor substrate and the insulating layer in the vertical direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893
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