Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made with and without traverse in the reply filed on 7/15/2026. Applicant has elected Group II without traverse and Species Ai with traverse, corresponding to claims 1-3 and 6-10.
The applicant’s traversal of the species requirement: claims 1-2 and 6-10 are generic with regard to the species described by the examiner. The examiner agrees with the applicant that those claims are generic. Those claims are examined below.
Invention Group II and Species Aii-Aiii, corresponding to claims 4-5 and 11-20, are withdrawn from further consideration.
Specification
The disclosure is objected to because of the following informalities:
There are several instances where the embodiments have numbering that is inconsistent with the drawings, for example see paragraphs [0042, 0046, 0048, 0049, 0052, 0053, 0054] where the numbering is incorrect for the package 100, substrate 204, substrate 204, interconnects 342, interconnects 242, cavity 248, plurality of vias 112, respectively.
Appropriate correction is required.
Drawings
The drawings submitted on 2/28/2024 have been accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted up to this point have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ho (US # 20170047308).
Regarding Claim 1, Ho teaches a package (see Fig. 6) comprising:
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193
361
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Greyscale
a first substrate (120);
a first integrated device (104) coupled to the first substrate through at least a first plurality of solder interconnects (210), wherein the first integrated device comprises a plurality of through substrate vias (184);
an interconnection device (154) coupled to a back side (108) of the first integrated device through a second plurality of solder interconnects (214);
a second substrate (142) coupled to the first substrate through at least a third plurality of solder interconnects ([0046, 0059] describe solder); and
a second integrated device (194) coupled to the second substrate and the interconnection device (shown coupled, e.g. 202, 216).
Regarding Claim 2, Ho teaches the package of claim 1
wherein the second integrated device (194) is coupled to the second substrate (142) through a first set of solder interconnects (216 that land on layer 146) from a fourth plurality of solder interconnects (the columns 216 that are formed in contact with pads 202), and
wherein the second integrated device (194) is coupled to the interconnection device (154) through a second set of solder interconnects (216 that land on TSV 212) from the fourth plurality of solder interconnects (the columns 216 that are formed in contact with pads 202).
Regarding Claim 3, Ho teaches the package of claim 1, wherein the interconnection device (154) is at least partially embedded in the second substrate (142; shown in Fig. 6).
Regarding Claim 6, Ho teaches the package of claim 1, wherein the interconnection device (154) includes an interconnection substrate or an interposer ([0030, 53] disclose a substrate singulated from a wafer).
Regarding Claim 7, Ho teaches the package of claim 1, wherein the interconnection device (154) comprises: a silicon substrate ([0030, 53]); and a plurality of interconnection interconnects located at least in the silicon substrate (see TSV 212; see [0079]).
Regarding Claim 8, Ho teaches the package of claim 1, wherein the interconnection device (154) comprises: at least one dielectric layer ([0053] describes dielectric layers interconnected with active/passive devices); and a plurality of interconnection interconnects located in the at least one dielectric layer (these interconnects would interconnect the active, passive devices with other hardware).
Regarding Claim 9, Ho teaches the package of claim 8, wherein the plurality of interconnection interconnects comprises a plurality of metallization interconnects ([0054, 79]).
Regarding Claim 10, Ho teaches the package of claim 1, wherein an electrical path between the second integrated device (194) and the first integrated device (104) comprises at least one interconnection interconnect from the plurality of interconnection interconnects (a TSV 212 in die 154; see [0079]), at least one solder interconnect from the second plurality of solder interconnects (214) and at least one through substrate via (184) from the plurality of through substrate vias.
Conclusion
Certification of pertinent prior art:
US 20230369261
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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