Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of Claims
Applicant's amendment of claims 1-4, 8, 10-11, 15-17, 19 in “Claims - 07/02/2026” have been acknowledged.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments “Remarks - 07/02/2026 - Applicant Arguments/Remarks Made in an Amendment”, have been fully considered, but they are not persuasive.
Applicant’s amendments of claims 1-4, 8, 10-11, 15-17, 19 have changed scope of the invention significantly, and necessitated the shift in new grounds of rejection detailed above. The shift in grounds of rejection renders applicant’s arguments moot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-2, 6-7, 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., of record (US 20190148351 A1 – hereinafter Chen) in view of Schmenn et al. (US 20220165646 A1 – hereinafter Schmenn).
Regarding Claim 1, Chen teaches a package (see the entire document; Figs. 1-14; specifically, [0012]-[0046], and as cited below), comprising:
a base portion (2 – Fig. 14 – [0012]) comprising a plurality of base interconnects (Fig. 1 - {34, 36} – [0018]);
a first integrated device (42A – [0024]) coupled to the base portion (2);
a second integrated device (42B – [0024]) coupled to the base portion (2);
a fill material (54 – Fig. 3 – [0032]) coupled to the base portion (2), the first integrated device (42A) and the second integrated device (42B),
wherein the fill material (54) is coupled to and touches (i) the base portion (2 – as shown in Fig. 14), (ii) the first integrated device (42A) and (iii) the second integrated device (42B); and
a metallization portion (72 – Fig. 10 – [0046]) coupled to the first integrated device (42A) and the second integrated device (42B).
But Chen as applied above does not expressly disclose wherein the fill material includes silicon oxide.
However, in a related art, Schmenn teaches a fill material 16 that touches device 12A, device 13A and a carrier 19 and is formed of silicon dioxide (Schmenn – Fig. 1B – [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the fill material formed of silicon dioxide as taught by Schmenn into Chen.
An ordinary artisan would have been motivated to integrate Schmenn structure into Chen structure in the manner set forth above for, for the obvious benefit of silicon dioxide protecting the integrated circuit devices from being shorted.
Regarding claim 2, the combination of Chen and Schmenn teaches the package of claim 1,
wherein the first integrated device (42A) comprises:
a first front side (bottom side) that is coupled to and touches the base portion; and a first back side (top side), and
wherein the second integrated device (42B) comprises:
a second front side (bottom side) that is coupled to and touches the base portion; and a second back side (top side).
Regarding claim 6, the combination of Chen and Schmenn teaches the package of claim 1, further comprising a plurality of pillar interconnects coupled to the metallization portion (Chen - 90 in [0052]).
Regarding claim 7, the combination of Chen and Schmenn teaches the package of claim 1, wherein the metallization portion comprises:
at least one dielectric layer (Chen 60 – [0030]); and
a plurality of metallization interconnects (Chen 46A – [0025]).
Regarding claim 12, the combination of Chen and Schmenn teaches the package of claim 1, wherein the metallization portion (Chen 72 – Fig. 10 – [0046]) is coupled to a first back side of the first integrated device (42A) and a second back side of the second integrated device (42B).
Regarding claim 13, the combination of Chen and Schmenn teaches the package of claim 1, wherein the first integrated device (Chen 42A) and the second integrated device (42B) are configured to be electrically coupled through the plurality of base interconnects of the base portion (Fig. 10).
Regarding claim 14, the combination of Chen and Schmenn teaches the package of claim 1, wherein the base portion further comprises a plurality of logic cells and/or transistors (Chen - transistors in [0012]).
Regarding Claim 15, Chen teaches a method for fabricating a package (see the entire document; Fig.17; specifically, [0012]-[0046], and as cited below), comprising:
providing a base portion (2 – Fig. 17) comprising a plurality of base interconnects ({34, 36} as shown in Fig. 1);
coupling a first integrated device (42A – [0024]) to the base portion (2);
coupling a second integrated device (42B) to the base portion (2);
coupling a fill material (54 - [0032]) to the base portion (2), the first integrated device (42A) and the second integrated device (42B),
wherein the fill material (54) is coupled to and touches (i) the base portion (2), (ii) the first integrated device (42A) and (iii) the second integrated device (42B); and
coupling a metallization portion (40 – [0021]) to the first integrated device (42A) and the second integrated device (42B).
But Chen as applied above does not expressly disclose wherein the fill material includes silicon oxide.
However, in a related art, Schmenn teaches a fill material 16 that touches device 12A, device 13A and a carrier 19 and is formed of silicon dioxide (Schmenn – Fig. 1B – [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the fill material formed of silicon dioxide as taught by Schmenn into Chen.
An ordinary artisan would have been motivated to integrate Schmenn structure into Chen structure in the manner set forth above for, for the obvious benefit of silicon dioxide protecting the integrated circuit devices from being shorted.
Regarding claim 16, the combination of Chen and Schmenn teaches the method of claim 15,
wherein the first integrated device (42A) comprises:
a first front side (bottom side) that is coupled to and touches the base portion (2); and a first back side (top side), and
wherein the second integrated device (42B) comprises:
a second front side (bottom side) that is coupled to and touches the base portion (2); and a second back side (top side).
Regarding claim 17, the combination of Chen and Schmenn teaches the method of claim 15, wherein the silicon oxide of the fill material (54) is further coupled to and touches the metallization portion (40).
Regarding claim 18, the combination of Chen and Schmenn teaches the method of claim 15, wherein the base portion comprises at least one passive device (Chen - “passive devices such as capacitors, inductors, resistors, or the like” – [0012]).
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Schmenn and in further view of Chen et al. (US 20210125933 A1 - hereinafter ChenW).
Regarding Claim 9, the combination of Chen and Schmenn teaches claim 7 from which claim 9 depends. But the combination does not expressly disclose wherein the plurality of metallization interconnects comprises interconnects with width and spacing that are less than 1 micron.
However, it is well known in the art to form metallization interconnects whose spacing between them is less than 1 micron as is also taught by ChenW (ChenW – [0015]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming metallization interconnects whose widths and spacing between them is less than 1 micron as taught by ChenW into the combination of Chen and Schmenn.
An ordinary artisan would have been motivated to integrate ChenW structure into the combination of Chen and Schmenn structure in the manner set forth above for, at least, for the obvious benefit of reliable interconnects for a sub-micron processing technology as is well known.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suthram et al. (US 20240222326 A1 – hereinafter Suthram).
Regarding Claim 3, Chen teaches a package (see the entire document; Figs. 1-14; specifically, [0012]-[0046], and as cited below), comprising:
a base portion (2 – Fig. 14 – [0012]) comprising a plurality of base interconnects (Fig. 1 - {34, 36} – [0018]);
a first integrated device (42A – [0024] coupled to the base portion (2);
a second integrated device (42B – [0024]) coupled to the base portion (2);
a fill material (54 – Fig. 3 – [0032]) coupled to the base portion (2), the first integrated device (42A) and the second integrated device (42B),
wherein the fill material (54) is coupled to and touches (i) the first integrated device (42A), (ii) the second integrated device (42B) and (iii) the base portion (2); and
a metallization portion (72 – Fig. 10 – [0046]) coupled to the first integrated device (42A) and the second integrated device (42B).
But Chen applied as above does not expressly disclose the fill material includes an organic material.
In a related art, Suthram teaches a fill material 506 enclosing IC devices 100 and touching substrate 512 (Suthram - Fig. 5 – [0152]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the fill material formed of an organic material as taught by Suthram into Chen.
An ordinary artisan would have been motivated to integrate Suthram structure into Chen structure in the manner set forth above for, for the obvious benefit of silicon dioxide protecting the integrated circuit devices from being shorted and protecting the integrated circuit devices from damage.
Regarding claim 4, the combination of Chen and Suthram teaches the package of claim 3, wherein the base portion (2) comprises at least one passive device (“passive devices such as capacitors, inductors, resistors, or the like” – Chen [0012]).
Regarding claim 5, the combination of Chen and Suthram teaches the package of claim 4, wherein the at least one passive device comprises a capacitor and/or an inductor (Chen [0012]).
Allowable Subject Matter
Claims 8, 10-11, 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 8: The package of claim 7, further comprising one or more barrier layers coupled to the plurality of metallization interconnects,
wherein the one or more barrier layers comprise tantalum (Ta) and/or tantalum nitride (TaN), and
wherein the one or more barrier layers are coupled to the side surface of at least some metallization interconnects from the plurality of metallization interconnects.
Regarding claim 10: The package of claim 7,
wherein the metallization portion comprises:
one or more dielectric layers; and
one or more coating layers that are different from the one or more dielectric layers,
wherein the one or more coating layers include silicon carbon nitride, and
wherein the one or more coating layers are coupled to and touch at least some of the metallization interconnects from the plurality of metallization interconnects.
Regarding claim 11: The package of claim 1,
wherein the base portion comprises:
one or more dielectric layers; and
one or more coating layers that are different from the one or more dielectric layers,
wherein the one or more coating layers include silicon carbon nitride, and
wherein the one or more coating layers are coupled to and touch at least some of the base interconnects from the plurality of base interconnects.
Regarding claim 19: The method of claim 15,
wherein the base portion comprises:
one or more dielectric layers; and
one or more coating layers that are different from the one or more dielectric layers, wherein the one or more coating layers include silicon carbon nitride, and wherein the one or more coating layers are coupled to and touch at least some of the base interconnects from the plurality of base interconnects.
Regarding claim 20: The method of claim 15, wherein the metallization portion is coupled to a first back side of the first integrated device and a second back side of the second integrated device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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