DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-8, 11-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (2021/0098380, hereafter Chen) in view of Uzoh (2024/0038702, hereafter Uzoh).
Regarding claim 1, Chen discloses a package comprising: a base substrate (202, par. 0048); a first integrated device (100) coupled to the base substrate through a bonding material (218); a second integrated device (50) coupled to the base substrate through the bonding material; a fill material (220) coupled to the base substrate, the first integrated device and the second integrated device; and a metallization portion (222) coupled to the first integrated device and the second integrated device (Fig. 18).
Chen fails to disclose the bonding material touches the base substrate and the first integrated device.
However, Uzoh teaches the bonding material (115, Fig. 1A) touches the base substrate (103) and the first integrated device (101) (Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen with Uzoh by including a bonding material touching a substrate and integrated device in order to form direct, continuous structural and electrical interface, securing the device while including conductive pathways.
Regarding claim 2, Chen discloses a package wherein the bonding material comprises a first bonding material (218 left) and a second bonding material (218 right), wherein the first integrated device (100) comprises a first back side that is coupled to and touching the first bonding material, and wherein the second integrated device (50) comprises a second back side that is coupled to and touching the second bonding material (Fig. 18, par. 0058).
Chen fails to disclose the first bonding material touches the base substrate, and wherein the second bonding material touches the base substrate.
However, Uzoh teaches the first and second bonding material (115) touches the base substrate (103) (Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen with Uzoh by including a bonding material touching a substrate and integrated device in order to form direct, continuous structural and electrical interface, securing the device while including conductive pathways.
Regarding claim 4, Chen discloses a package wherein the metallization portion (222) comprises at least one passive device (242, par. 0071) (Fig. 18).
Regarding claim 5, Chen discloses a package wherein the at least one passive device comprises a capacitor and/or an inductor (242, par. 0071, Fig. 18).
Regarding claim 6, Chen disclose a package further comprising a plurality of pillar interconnects (238) coupled to the metallization portion (222) (Fig. 18).
Regarding claim 7, Chen discloses a package wherein the metallization portion comprises: at least one dielectric layer (224, 228, 232, 236); and a plurality of metallization interconnects (226, 230, 234) (Fig. 18 par. 0061).
Regarding claim 8, Chen discloses a package wherein the plurality of metallization interconnects comprise a plurality of damascene interconnects (par 0091).
Regarding claim 11, Chen fails to specifically disclose a package of wherein the base substrate comprises silicon, wherein the fill material comprises silicon oxide, and wherein the bonding material comprises oxide or silicon.
However, Chen teaches a package wherein the base substrate comprises silicon (par. 0078), wherein the fill material comprises silicon oxide (par. 0082), and wherein the bonding material comprises oxide or silicon (par. 0028).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen by providing a substrate, fill material, and bonding material with silicon/oxide because of thermal expansion coefficients, dielectric insulation, and ability to prevent stress and short circuiting.
Regarding claim 12, Chen discloses a method for fabricating a package, comprising: providing a base substrate (202, par. 0048); coupling a first integrated device (100) to the base substrate through a bonding material (218); coupling a second integrated device (50) to the base substrate through the bonding material; coupling a fill material (220) to the base substrate, the first integrated device and the second integrated device; and coupling a metallization portion (222) to the first integrated device and the second integrated device (Fig. 18).
Chen fails to disclose the bonding material touches the first integrated device and the base substrate.
However, Uzoh teaches the bonding material (115) touches the first integrated device (101) and the base substrate (103) (Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen with Uzoh by including a bonding material touching a substrate and integrated device in order to form direct, continuous structural and electrical interface, securing the device while including conductive pathways.
Regarding claim 13, Chen discloses a method wherein the bonding material comprises a first bonding material (218 left) and a second bonding material (218 right), wherein the first integrated device (100) comprises a first back side that is coupled to and touching the first bonding material, and wherein the second integrated device (50) comprises a second back side that is coupled to and touching the second bonding material (Fig. 18, par. 0058).
Chen fails to disclose wherein the second bonding material touches the base substrate.
However, Uzoh teaches wherein the second bonding material (115) touches the base substrate (103) (Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen with Uzoh by providing a bonding material touching the substrate in order to form direct, continuous structural and electrical interface, securing the device while including conductive pathways.
Regarding claim 14, Chen discloses a method wherein the fill material (220) is coupled to and touching the first integrated device (100), the second integrated device (50) and the base substrate (202, par. 0059) (Fig. 18).
Regarding claim 15, Chen discloses a method wherein the metallization portion (222) comprises at least one passive device (242, par. 0071) (Fig. 18).
Regarding claim 16, Chen discloses a method wherein the metallization portion (222) comprises: at least one dielectric layer (224, 228, 232, 236); and a plurality of metallization interconnects (226, 230, 234) (Fig. 18, par. 0061).
Regarding claim 17, Chen discloses a method wherein the plurality of metallization interconnects comprise a plurality of damascene interconnects (par. 0091).
Regarding claim 20, Chen discloses a method wherein the base substrate comprises silicon (par. 0078), wherein the fill material comprises silicon oxide (par. 0082), and wherein the bonding material comprises oxide or silicon (par. 0028).
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Uzoh as applied to claims 1 and 12 above, and further in view of Lee et al. (2016/0133571, hereafter Lee).
Regarding claim 9, Chen and Uzoh, discussed above, fail to disclose a package wherein the plurality of metallization interconnects comprises interconnects with width and/or spacing that are less than 1 micron.
However, Lee taches a package wherein the plurality of metallization interconnects (306, 308, 310; Fig. 3) comprises interconnects with width and/or spacing that are less than 1 micron (par. 0068).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen and Uzoh with Lee by implementing interconnects with width and/or spacing less than 1 micron in order to provide a high-density electrical path for greater bandwidth, capacitance reduction, and decreased latency.
Regarding claim 18, Chen and Uzoh fail to disclose a package wherein the plurality of metallization interconnects comprises interconnects with width and/or spacing that are less than 1 micron.
However, Lee taches a package wherein the plurality of metallization interconnects (306, 308, 310; Fig. 3) comprises interconnects with width and/or spacing that are less than 1 micron (par. 0068).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen and Uzoh with Lee by implementing interconnects with width and/or spacing less than 1 micron in order to provide a high-density electrical path for greater bandwidth, capacitance reduction, and decreased latency.
Claims 3, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Uzoh as applied to claims 1 and 12 above, and further in view of Wang et al. (2024/0222287, hereafter Wang).
Regarding claim 3, Chen and Uzoh, discussed above, fail to disclose a package wherein the fill material is coupled to and touching the first integrated device, the second integrated device and the base substrate.
However, Wang teaches a package wherein the fill material (590) is coupled to and touching the first integrated device (500 left), the second integrated device (500 right) and the base substrate (410) (Fig. 3).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen and Uzoh with Wang by providing a fill material that touches integrated devices and the substrate in order to encapsulate the assembly, filling voids and protecting interconnects while enhancing thermal dissipation and structural integrity.
Regarding claim 10, Chen discloses a fill material comprising a first inorganic material (par. 0082), and wherein the bonding material comprises a second inorganic material (par. 0028).
Chen fails to disclose a package wherein the base substrate includes at least one cavity.
However, Wang teaches a package wherein the base substrate (410) includes at least one cavity (Fig. 1, par. 0047).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen and Uzoh with Wang by including a substrate with at least one cavity in order to provide thermal management through microfluidic cooling.
Regarding claim 19, Chen fails to disclose a method wherein the base substrate includes at least one cavity.
However, Wang teaches a method wherein the base substrate (410) includes at least one cavity (Fig. 1, par. 0047).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen and Uzoh with Wang by including a substrate with at least one cavity in order to provide thermal management through microfluidic cooling.
Response to Arguments
Applicant’s arguments with respect to claims 1, 2, 3, 11, and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.B./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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