DETAILED ACTION
This action is responsive application No. 18/590,785 filed on February 28, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 reading on Fig. 1 in the reply filed on 07/06/2026 is acknowledged. The Applicants indicated that claims 1-9 and 11-120 read on the elected species. Claim 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the recitations in claim 18 that “forming the air gap includes etching the insulating layer to expose a surface of the insulating layer that is recessed from the first surface of the substrate” and claim 19 that “forming a gate region by depositing a second polysilicon material on the insulating layer and etching the second polysilicon material”, must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 11-14, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Woo (US 10,304,933).
Regarding Claim 1, Woo (see, e.g., Fig. 1A), teaches a device, comprising:
a power MOSFET 100 (see, e.g., col. 3, ll. 18-19), including:
a substrate 101 (see, e.g., col. 3, ll. 18-20), including:
a recess 70 in a first surface (i.e., top surface) of the substrate 101, the first surface extending in a first direction (i.e., horizontal direction), the recess having sidewalls 70s extending in a second direction (i.e., vertical direction) transverse the first direction, the recess 70 including a second surface (i.e., bottom surface) extending in the first direction between the sidewalls 70s (see, e.g., col. 3, ll. 22-26);
an insulating layer 50g on the first surface of the substrate 101 and in the recess 70 (see, e.g., col. 3, ll. 52-53);
a first polysilicon region 60 in the insulating layer 50g, the first polysilicon region 60 extending in the second direction for a first dimension Ls (see, e.g., col. 4, ll. 44-50); and
an air gap 80A in the insulating layer 50g between the first polysilicon region 60 and the substrate 101, the air gap 80A extending in the second direction for a second dimension Lc being less than the first dimension Ls (see, e.g., col. 2, ll. 54-59, col. 4, ll. 44-50).
Regarding Claim 2, Woo teaches all aspects of claim 1. Woo (see, e.g., Fig. 1A), teaches that the air gap 80A extends in the first direction (i.e., horizontal direction) for a third dimension Wc being less than the second dimension Lc.
Regarding Claim 3, Woo teaches all aspects of claim 1. Woo (see, e.g., Fig. 1A), teaches that the first polysilicon region 60 extends in the first direction (i.e., horizontal direction) for a third dimension Ws being less than the first dimension Ls.
Regarding Claim 4, Woo teaches all aspects of claim 1. Woo (see, e.g., Fig. 1A), teaches that the first polysilicon region 60 has a first (i.e., lower end) end spaced from the second surface (i.e., bottom surface) of the recess 70 for a third dimension.
Regarding Claim 5, Woo teaches all aspects of claim 1. Woo (see, e.g., Fig. 1A), teaches that the air gap 80A has a first end (i.e., lower end) spaced from the second surface (i.e., bottom surface) of the recess 70 for a fourth dimension, the third dimension being less than the fourth dimension (see, e.g., Fig. 1A).
Regarding Claim 11, Woo teaches all aspects of claim 1. Woo (see, e.g., Fig. 1A), teaches that the air gap 80A is surrounded by the insulating layer 50g.
Regarding Claim 12, Woo (see, e.g., Fig. 1A), teaches a device, comprising:
a power MOSFET 100 (see, e.g., col. 3, ll. 18-19) including:
a recessed substrate 101 (see, e.g., col. 3, ll. 18-20);
an insulating layer 50g on the recessed substrate 101 (see, e.g., col. 3, ll. 52-53);
a first polysilicon region 60 in the insulating layer 50g (see, e.g., col. 4, ll. 44-50);
a first air gap 80A in the insulating layer 50g (see, e.g., col. 4, ll. 44-50); and
a second air gap 80B in the insulating layer 50g, the first polysilicon region 60 between the first and second air gaps 80A/80B.
Regarding Claim 13, Woo teaches all aspects of claim 12. Woo (see, e.g., Fig. 1A), teaches that the first and second air gaps 80A/80B are each equally spaced from the first polysilicon region 60 in a first direction (i.e., horizontal direction).
Regarding Claim 14, Woo teaches all aspects of claim 12. Woo (see, e.g., Fig. 1A), teaches that the first and second air gaps 80A/80B have substantially the same shape and dimensions (see, e.g., Fig. 1A).
Regarding Claim 16, Woo (see, e.g., Figs. 1A, 2A-2M), teaches a method, comprising:
forming a power MOSFET 100 device by (see, e.g., col. 3, ll. 18-19):
forming a first insulating layer 205 on a substrate 201 including a recess 204, the first insulating layer 205 covering a first surface (i.e., top surface) of the substrate 201, recess sidewalls 204s, and a second surface (i.e., low surface) of the recess 204 extending between the sidewalls 204s (see, e.g., Fig. 2B, col. 8, ll. 2-5);
forming a first polysilicon region 206 in the insulating layer 205 (see, e.g., Fig. 2C, col. 8, ll. 11-13); and
forming an air gap 209a in the insulating layer 205 on the substrate 201 (see, e.g., Fig. 2G, col. 8, ll. 43-48).
Regarding Claim 17, Woo teaches all aspects of claim 16. Woo (see, e.g., Figs. 1A, 2A-2M), teaches that forming the first polysilicon region 206 includes depositing a first polysilicon material 206a on the first insulating layer 205 and in the recess 204 (see, e.g., Fig. 2C, col. 8, ll. 11-13).
Regarding Claim 18, Woo teaches all aspects of claim 17. Woo (see, e.g., Figs. 1A, 2A-2M), teaches that forming the air gap 209a includes etching the insulating layer 205 to expose a surface of the insulating layer 205 that is recessed from the first surface of the substrate 201 (see, e.g., Fig. 2F, col. 8, ll. 31-39).
Regarding Claim 19, Woo teaches all aspects of claim 18. Woo (see, e.g., Figs. 1A, 2A-2M), teaches, comprising forming a gate region 210 by depositing a second polysilicon material on the insulating layer 205 and etching the second polysilicon material (see, e.g., Figs. 2I-2J, col. 8, ll. 58-67).
Regarding Claim 20, Woo teaches all aspects of claim 16. Woo (see, e.g., Figs. 1A, 2A-2M), teaches forming source and drain regions 212 on the substrate 201 (see, e.g., Fig. 2L, col. 9, ll. 7-11).
Allowable Subject Matter
Claims 6-9 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/Primary Examiner, Art Unit 2814
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