DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/25/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein said memory dies and said routing layer are completely overlapped…” However, it unclear how or what the memory dies and routing layers are overlapped by. Are the memory dies and routing layer completely overlapped by the substrate? By the air? From at least a direction from the dies 110 to the substrate 116 in FIG. 1, there appears to be nothing that completely overlaps both the dies and the routing layers. There is no support in the Specification for an overlap.
Therefore, claim 1 is rejected under 35 USC 112b for being indefinite, and claims 2-9 are rejected for at least their dependencies. Appropriate correction is required.
For the purposes of Examination, claim 1 will be interpreted such that the substrate completely overlaps both the dies and the routing layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over GANDHI et al. (US 20240203968 A1, hereinafter Gandhi) in view of KANG (US 20240030145 A1).
With regards to claim 1, Gandhi discloses a package architecture (FIG. 27) with interposer, comprising:
a package substrate; (substrate 600/702)
an interposer (dies 204 and bridge with bridge dies 400/304/1100) on said package substrate, and said interposer is comprised of a plurality of vertically-stacked memory dies (dies 204) and a topmost routing layer, (bridge with bridge dies 400/304) wherein said memory dies and said routing layer are completely overlapped; (See FIG. 27, where the substrate completely overlaps the dies 204 and the routing layers 400/304) and
a plurality of chips (structures 500) horizontally arranged on said routing layer, wherein said chips are electrically and respectively connected with said memory dies. (See FIG. 27 and Paragraph [0032)
However, Ghandi does not explicitly teach said chips are electrically connected with each other and connected with said memory dies through said routing layer.
KANG teaches said chips (chips CH1 and CH2) are electrically connected with each other and connected with said memory dies through said routing layer. (at least wiring layer 330, see at least FIG. 2, and paragraph [0044]: ‘the first and second semiconductor chips CH1 and CH2 may be electrically connected to the external connection terminals 700 through the connection substrate 100 and the third semiconductor chip 300.”)
It would have been obvious to one of ordinary skill in the art to modify the device of Ghandi using the connections of Kang, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that the interconnections allow for signals to be delivered more stably and promptly. (See kang Paragraph [0038])
With regards to claim 2, Gandhi in view of Kang teaches the package architecture with interposer of claim 1.
Ghandi further teaches wherein said memory dies are provided with multiple memory cells, and an integration density of said memory cells corresponds to an integration density of said chips right above said memory cells. (See FIG. 27, showing the density of dies 204 relative to the structures 500)
With regards to claim 3, in view of Kang teaches the package architecture with interposer of claim 1.
Ghandi further teaches wherein said memory dies are bonded together through through-silicon vias (TSVs) or hybrid bonding. (Paragraph [0005]: “A chip package and method for fabricating the same are provided that include hybrid bonded bridge dies…”)
With regards to claim 4, Gandhi in view of Kang teaches the package architecture with interposer of claim 1.
Ghandi further teaches wherein said chips are bonded on said routing layer through micro bumps or hybrid bonding. (Paragraph [0005]: “A chip package and method for fabricating the same are provided that include hybrid bonded bridge dies…”)
With regards to claim 5, Gandhi in view of Kang teaches the package architecture with interposer of claim 1.
Ghandi further teaches wherein said interposer is bonded on said package substrate through C4 bump. (see FIG. 27, showing the solder bump, i.e. C4 bump)
With regards to claim 6, Gandhi in view of Kang teaches the package architecture with interposer of claim 1.
Ghandi further teaches wherein said chips comprise system-on-a-chip (SoC), high bandwidth memory (HBM), integrated passive device (IPD), logic chiplet, (Paragraph [0027]: “The additional structures 500 may be dummy dies, passive devices, processor dies, memory dies or chiplets,”) radio frequency (RF) chiplet or microelectromechanical systems (MEMS) chip.
With regards to claim 7, Gandhi in view of Kang teaches the package architecture with interposer of claim 1.
Ghandi further teaches further comprising another routing layer (pillars 2304/connective die 1100) in a bottommost layer of said interposer.
With regards to claim 8, Gandhi in view of Kang teaches the package architecture with interposer of claim 1.
Ghandi further teaches wherein said memory dies are DRAM dies or SRAM dies. (Paragraph [0027]: “In the example depicted in FIG. 5, the additional structures 500 are memory dies, such as static random-access memory (SRAM).”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over GANDHI et al. (US 20240203968 A1, hereinafter Gandhi) in view of KANG (US 20240030145 A1), as applied to claim 1, and further in view of Tang et al. (US 20230317673 A1, hereinafter Tang)
With regards to claim 9, Gandhi in view of Kang teaches the package architecture with interposer of claim 1.
However, Gandhi does not explicitly teach wherein said package substrate is BT (bismaleimide triazine) resin substrate, ABF (ajinomoto build-up film) substrate or MIS (molded interconnect substrate) substrate.
Tang teaches using a MIS (molded interconnect substrate) substrate. (Paragraph [0015]: ‘Alternative package substrates include pre-molded lead frames (PMLF) and molded interconnect substrates (MIS)…”)
It would have been obvious to one of ordinary skill in the art to modify the device of Gandhi in view of Kang to have the MIS of Tang, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that using MIS is substituting one known element for another to obtain predictable results, such as supporting the dies in a package (See paragraph [0015] of Tang)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 have been considered but are moot because the new ground of rejection relies on kang which teaches the interconnection as recited above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230378110 A1 – multiple dies with interposers
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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