DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 06/02/2026 is acknowledged. Claims 19, 21-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/22/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5- 13 and 15-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kirby.
Regarding claim 1, Kirby disclose a semiconductor device (Fig. 1A- 3B, 300a, specifically Fig. 3B* annotated below), comprising:
a first semiconductor die (302) comprising a first substrate (as shown (1Sub) and ¶[0019]), a first interface circuit (1Int) and first bonding components (1BC), wherein the first bonding components (1BC) are arranged in a first bond array region (1BAR), the first interface circuit comprises a first interface logic circuit (¶[[0039] teaches logic circuitry), first transceivers and first receivers, and the first interface logic circuit (¶[0030] teaches the circuitry (318) to enable the circuitry (318) to transmit and receive signals to and from the circuit components at the dielectric layers (306)), the first transceivers and the first receivers are arranged inside the first bond array region (as shown); and
a second semiconductor die (304) comprising a second substrate (as shown (2Sub) and ¶[0019]), a second interface circuit (2Int) and second bonding components (2BC), wherein the first bonding components (1BC) are connected to the second bonding components (2BC), the first interface circuit (1Int) and the second interface circuit (2Int) are located between the first substrate (1Sub) and the second substrate (2Sub), and the first semiconductor die (302) and the second semiconductor die (304) are interlinked by an interface constructed by the first interface circuit, the first bonding components, the second interface circuit and the second bonding components (as shown in Fig. 3B).
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Regarding claim 3, Kirby disclose claim 1, Kirby discloses the first transceivers and the first receivers are electrically connected to the first bonding components, respectively (as shown in Fig. 3B, 318 is electrically connected to the bonding components and ¶[0030] teaches the circuitry (318) to enable the circuitry (318) to transmit and receive signals to and from the circuit components at the dielectric layers (306)).
Regarding claim 5, Kirby disclose claim 1, Kirby future discloses a portion of the first interface circuit overlaps one or more of the first bonding components (as shown in Fig. 3B, 318 is overlapping the bonding component (1BC)).
Regarding claim 6, Kirby disclose claim 1, Kirby future discloses the first semiconductor die (Fig. 3B, 302) further comprises function circuit, the function circuit is in signal communication to the first interface circuit (as shown in Fig. 3B interconnections electrically connected to the 1st interface circuit (1Int), ¶[0032] and ¶[0044] ).
Regarding claim 7, Kirby disclose claim 1, Kirby future disclose a portion of the function circuit is arranged inside the first bond array region (1BAR) (as shown in Fig. 3B*).
Regarding claim 8, Kirby disclose claim 1, Kirby future disclose the first semiconductor die (Fig. 3B*, 302) further comprises an interconnect wiring structure (as shown and ¶[0032]) disposed between the first bonding components and the first interface circuit (318).
Regarding claim 9, Kirby disclose claim 1, Kirby future disclose the first bonding components (1BC) and the second bonding components (2BC) comprises bonding pads (as shown), micro bumps or other types of 3D interconnection components (as shown in Fig. 3B*).
Regarding claim 10, Kirby disclose claim 1, Kirby future disclose the second bonding components (Fig. 3B*, 2BC) are arranged in a second bond array region (2BAR) substantially mirrored (as shown) from the first bond array region (1BAR).
Regarding claim 11, Kirby disclose claim 10, Kirby future disclose the second interface circuit (Fig. 3B*, 2Int) is arranged inside the second bond array region (2BAR).
Regarding claim 12, Kirby disclose claim 10, Kirby future disclose the second interface circuit (Fig. 3B, 2Int) comprises a second interface logic circuit (¶[[0039] teaches logic circuitry), second transceivers and second receivers (¶[0031] teaches the circuitry (316) to enable the circuitry (316) to transmit and receive signals to and from the circuit components at the dielectric layers (308)), and the second interface logic circuit, the second transceivers and the second receivers are arranged inside the second bond array region (as shown).
Regarding claim 13, Kirby disclose claim 12, Kirby future disclose the second transceivers and the second receivers are electrically connected to the second bonding components, respectively (as shown in Fig. 3B and ¶[0031] teaches the circuitry (316) to enable the circuitry (316) to transmit and receive signals to and from the circuit components at the dielectric layers (308)).
Regarding claim 15, Kirby disclose claim 1, Kirby future disclose a portion of the second interface circuit (Fig. 3B, 2Int) overlaps one or more of the second bonding components (2BC).
Regarding claim 16, Kirby disclose claim 1, Kirby future disclose the second semiconductor die (304) further comprises a function circuit (circuitry in the semiconductor die (304)), and the function circuit is in signal communication to the second interface circuit (as shown in Fig. 3B interconnections electrically connected to the 2nd interface circuit (2Int), ¶[0035] and ¶[0044] ).
Regarding claim 17, Kirby disclose claim 16, Kirby future disclose a portion of the function circuit (circuitry in the semiconductor die (304)) is arranged inside a second bond array region (2BAR) of the second bonding components (2BC) (as shown in Fig. 3B*).
Regarding claim 18, Kirby disclose claim 1, Kirby future disclose the second semiconductor die (Fig. 3B*, 304) further comprises an interconnect wiring structure (as shown) disposed between the second bonding components (2BC) and the second-interface circuit (2Int) (as shown in Fig. 3B interconnections electrically connected to the 2nd interface circuit (2Int), ¶[0032] and ¶[0044] ).
Allowable Subject Matter
Claims 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takair et al. [US 10,522,489 B1] discloses the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
Lee et al. [US 2022/0108964 A1] discloses the semiconductor device includes a first semiconductor die having a first bonding surface that is formed with a first set of contacts patterned with a first connection pitch. A second semiconductor die has a second bonding surface that is formed with a second set of contacts patterned with a second connection pitch.
Kim et al. [US 20210233900 A1] discloses a bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/Examiner, Art Unit 2897
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