DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, and 16-18 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Huang (USPN 6,110,799, hereinafter “Huang”) in view of Palmour et al. (USPN 4,945,394, hereinafter “Palmour”).
In reference to claim 1, fig. 1-9 and 12 of Huang discloses a similar method. Fig. 12 of Huang discloses a method of manufacturing a semiconductor device which comprises preparing a semiconductor substrate including a first n-type semiconductor layer (note bottommost N+ region with node) and a second n-type semiconductor layer (10) on the first n-type semiconductor layer (note bottommost N+ region with node). It is understood that the first n-type semiconductor layer (note bottommost N+ region with node) is present in fig. 1-9 since it acts as the required drain region for the transistor. Thus in fig. 1-9, the second n-type semiconductor layer (10) has a lower impurity concentration (N) than that of the first n-type semiconductor layer (fig. 12 - note bottommost N+ region with node). Fig. 8 shows that a first p-type semiconductor layer (35) is formed by irradiating p-type impurity ions to a surface of the second n-type semiconductor layer (10) in a manner such that the first p-type semiconductor layer (35) has a first boundary bottom between the second n-type semiconductor layer (10) and the first p-type semiconductor layer (35). Fig. 1 shows that a second p-type semiconductor layer (14) is formed by irradiating p-type impurity ions to a surface of the second n-type semiconductor layer (10) such that the second p-type semiconductor layer (14) has a second boundary bottom between the second n-type semiconductor layer (10) and the second p-type semiconductor layer (14). The second boundary bottom is at a depth position shallower than the first boundary bottom. After forming the second p-type semiconductor layer (14), a gate trench (20) is formed in a region where the second p-type semiconductor layer (14) is formed in a manner such that the gate trench (106) penetrates through the second p-type semiconductor layer (14) and reaches the second n-type semiconductor layer (10). The gate trench (20) has a bottom portion shallower than the first boundary bottom. A gate insulating layer (24) and a gate electrode (26) are formed in the gate trench (20). A recessed portion (34) is formed in the surface of the second n-type semiconductor layer (10). Forming the first p-type semiconductor layer (35) comprises irradiating p-type impurity to a region where the recessed portion (34) is formed. An impurity concentration of the first p-type semiconductor layer (35) is higher than an impurity concentration of the second p-type semiconductor layer (14).
Huang does not disclose that the device uses a silicon carbide material. However Palmour discloses (column 1, lines 57-67) that silicon carbide has advantageous characteristics such as a high thermal conductivity, a high melting point, a high electric field breakdown strength, a low dielectric constant, and a high saturated electron drift velocity which lead to semiconductor devices capable of operating at higher temperatures, high device densities, high speeds, and at high power levels and even under high radiation densities (relative to other semiconductor materials). In view of Palmour, it would therefore be obvious to implement the method of Huang with silicon carbide.
With regard to claim 10, the first p-type semiconductor layer (35) is formed below the recessed portion (34).
In reference to claim 16, fig. 1-9 and 12 of Huang discloses a similar method. Fig. 12 of Huang discloses a method of manufacturing a semiconductor device which comprises preparing a semiconductor substrate including a first n-type semiconductor layer (note bottommost N+ region with node) and a second n-type semiconductor layer (10) on the first n-type semiconductor layer (note bottommost N+ region with node). It is understood that the first n-type semiconductor layer (note bottommost N+ region with node) is present in fig. 1-9 since it acts as the required drain region for the transistor. Thus in fig. 1-9, the second n-type semiconductor layer (10) has a lower impurity concentration (N) than that of the first n-type semiconductor layer (fig. 12 - note bottommost N+ region with node). Fig. 8 shows that a first p-type semiconductor layer (35) is formed by irradiating p-type impurity ions to a surface of the second n-type semiconductor layer (10) in a manner such that the first p-type semiconductor layer (35) has a first boundary bottom between the second n-type semiconductor layer (10) and the first p-type semiconductor layer (35). Fig. 1 shows that a second p-type semiconductor layer (14) is formed by irradiating p-type impurity ions to a surface of the second n-type semiconductor layer (10) such that the second p-type semiconductor layer (14) has a second boundary bottom between the second n-type semiconductor layer (10) and the second p-type semiconductor layer (14). The second boundary bottom is at a depth position shallower than the first boundary bottom. A gate trench (20) is formed in a region where the second p-type semiconductor layer (14) is formed in a manner such that the gate trench (106) penetrates through the second p-type semiconductor layer (14) and reaches the second n-type semiconductor layer (10). A gate insulating layer (24) and a gate electrode (26) are formed in the gate trench (20). A recessed portion (34) is formed in the surface of the second n-type semiconductor layer (10). Forming the first p-type semiconductor layer (35) comprises irradiating p-type impurity to a region where the recessed portion (34) is formed. The first p-type semiconductor layer (35) is formed below the recessed portion (34). An impurity concentration of the first p-type semiconductor layer (35) is higher than an impurity concentration of the second p-type semiconductor layer (14).
Huang does not disclose that the device uses a silicon carbide material. However Palmour discloses (column 1, lines 57-67) that silicon carbide has advantageous characteristics such as a high thermal conductivity, a high melting point, a high electric field breakdown strength, a low dielectric constant, and a high saturated electron drift velocity which lead to semiconductor devices capable of operating at higher temperatures, high device densities, high speeds, and at high power levels and even under high radiation densities (relative to other semiconductor materials). In view of Palmour, it would therefore be obvious to implement the method of Huang with silicon carbide.
With regard to claim 17, the gate trench (20) is formed such that it has a bottom portion shallower than the first boundary bottom.
In reference to claim 18, the second p-type semiconductor layer (14) comprises a channel region formed along the gate trench (20) and held in contact with the second n-type semiconductor layer (14), and an impurity concentration (P) of the channel region is lower than the impurity concentration (P+) of the first p-type semiconductor layer (35).
Allowable Subject Matter
Claims 11-15 were allowed in a previous Office action.
Claims 9, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the examiner is unaware of any prior art which suggests or renders obvious a method of forming a silicon carbide semiconductor device with the suggested first and second n-type semiconductor layers as well as first and second p-type semiconductor layers, the specific positioning of the gate electrode and gate insulating layer in a trench, the suggested boundary bottoms in combination with the specific formation of a recessed portion or the required p-type semiconductor region as described by the applicant in claims 9 and 19. The reasons for the allowability of claims 11-15 were discussed in a previous Office action.
Response to Arguments
The examiner notes amended claims 10 and 16 and thus hereby withdraws the rejection of claims 10 and 16-20 made under 35 U.S.C. 112 (pre-AIA ), second paragraph, in the previous Office action.
Applicant’s arguments with respect to claims 1, 9, 10, and 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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