DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species X and Modification C, drawn to the device shown in Fig. 22 and the guard ring shown in Fig. 4C, and claims 1-4, 6, 7, 10-17, and 20 in the reply filed on 07/07/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 5, 8-9, 18-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/07/2026.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a processing device configured to process a signal output from the semiconductor device” in claim 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Regarding claim 20: the claim limitation: “processing device configured to process a signal output from the semiconductor device” will be interpreted as a CPU being connected to the semiconductor device in light of the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Larson US (20130049215 A1), hereinafter referred to as “Larson215”, in view of Zhu (US 20100224876 A1) hereinafter referred to as “Zhu876”.
Regarding claim 1: Larson215 teaches a semiconductor device that comprises a semiconductor layer comprising a first main surface and a second main surface on an opposite side of the first main surface (See at least Fig. 1, element 12, “silicon layer”, para. [0018]), a first insulating layer arranged in contact with the first main surface (See at least Fig. 1, element 28a, “first dielectric layer”, para. [0028]), and a second insulating layer arranged in contact with the second main surface (See at least Fig.1, element 20, “Base oxide layer 20 may include, for example, an electrically insulative material, such as silicon dioxide (SiO.sub.2) or sapphire (Al.sub.2O.sub.3).”, para. [0026]), wherein the semiconductor layer includes a first portion and a second portion (The first portion and the second portion are not defined in the specification, the examiner interprets the first and second portions to be include any regions that are not electrically connected within the semiconductor layer, See Fig. 1 annotated below, dashed blue line shows semiconductor layer divided into two regions by element 17b, “oxide isolation region”, para. [0019]), which are electrically separated in the semiconductor layer by a trench (The trench is interpreted by the examiner to mean an open-air gap or a material region that divides at least a portion of the semiconducting layer.) extending through the semiconductor layer, (See at least Fig. 1 annotated below, element 17b, “oxide isolation regions”, para. [0019], the isolation regions are depicted in Fig. 1 to extend through the silicon layer) and a semiconductor element is arranged in the second portion (See at least Fig. 1, elements 16c and 16d, “active silicon regions”, para. [0016], in light of the specification semiconductor elements include transistors), the first portion includes a first semiconductor region (See at least Fig. 1, element 16a, “active silicon regions”, para. [0016]) which forms a part of the first main surface, and a second semiconductor region (See at least Fig. 1, element 16b, “active silicon regions”, para. [0016]) which forms a part of the second main surface, the second portion includes a third semiconductor region (See at least Fig. 1, element 16d, “active silicon regions”, para. [0016]) which forms a part of the first main surface, and a fourth semiconductor region (See at least Fig. 1, element 16c, “active silicon regions”, para. [0016]) which forms a part of the second main surface, and a second conductive path configured to electrically connect the second semiconductor region and the fourth semiconductor region is arranged in the second insulating layer (See at least Fig. 1, element 22d, “fourth interconnect, para. [0027], element 22d connects active regions 16b and 16c).
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Fig. 1 from Larson215: Red dashed boxes indicate active regions in the semiconducting layer. Larson215 does not explicitly show that the upper (first) conductive path connects two active regions directly. Blue dashed line separates a first portion and a second portion.
Larson215 does not explicitly teach the doping type of the active regions stating, “In some examples, a respective one of active silicon regions 16 may include at least two doped regions (e.g., a source region and a drain region; not shown in FIG. 1). The two doped regions may be electrically connected to respective electrodes (e.g., a source electrode and a drain electrode). The construction of transistors is generally known in the art, and different types of transistors may be utilized in accordance with this disclosure.”, para. [0017]. Larson215 does also not explicitly teach that a first conductive path is configured to electrically connect the first semiconductor region and the third semiconductor region is arranged in the first insulating layer stating “Although FIG. 1 illustrates one example of connection and routing between first interconnect 22a and transistors and/or polysilicon gates 18 and between second interconnect 22b and transistors and/or polysilicon gates 18, first interconnect 22a and/or second interconnect 22b may be connected to different ones of the transistors (e.g., polysilicon conductors 18 and/or active silicon regions 16) and/or to different polysilicon conductors 18. Additionally, although FIG. 1 illustrates two interconnects 22a, 22b disposed on the first side of layer 12, in other examples, integrated circuit 10 may include more than two interconnects on the first side of layer 12. In general, integrated circuit 10 may include a plurality of transistors (e.g., thousands, millions, billions, or more) and any number of interconnects 22a, 22b useful to form the desired connections between respective ones of the plurality of transistors.”, para. [0021].
Zhu876 teaches a wiring and transistor configuration where active regions can be either p-type or n-type (See at least Fig. 12, elements 34, “The first source and drain regions 34 may be formed by employing block level masks and ion implantation of electrical dopants, i.e., p-type dopants and n-type dopants.”, para. [0035]). Zhu876 also explicitly shows a conductive path connecting the active regions on both sides of the semiconductor layer (See Fig. 12 annotated below, elements 46 and 96). Zhu876 teaches that such a wiring configuration is beneficial for three-dimensional stacking of semiconductor chips to increase device integration (“Three-dimensional integration of semiconductor chips typically employs through-substrate vias (TSV's) that connect the front side of a semiconductor chip to a back side of the same semiconductor chip. Multiple semiconductor chips may be vertically stacked employing the through-substrate vias (TSV's). Such three-dimensional integration of semiconductor chips provides a higher device density per area than a single semiconductor chip without any vertical stacking, and reduces the size of a packaging substrate correspondingly.”, para. [0003]).
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Fig. 12 from Zhu876: Active regions are shown inside the red dashed boxes (The TSV material 12 may also be made of a doped material, para. [0028]). Zhu876 explicitly shows that active regions between adjacent transistors may be connected by the same conductive path (elements 34 connected by wiring 46, and elements 84 connected by wiring 96), teaching the limitation that is not explicitly shown in Larson215. Dielectric liners (element 10 indicated by blue dashed line) may also be considered a trench that divides the semiconducting layer into two portions.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring structure that is explicitly shown in Larson215 to the one shown in Zhu876 in order to allow for improved 3D integration of the semiconductor device. Larson215 suggests that such a configuration is possible, and Zhu876 gives an explicit example of such a wiring structure, therefore the substitution of the wiring structure of Zhu876 into the insulating layers above and below the semiconductor layer disclosed in Larson215 could be performed with a reasonable expectation of success to arrive at the claimed invention.
Regarding claim 2: Larosn215 and Zhu876 teach the limitations of claim 1, Larson215 does not explicitly teach that there is fifth semiconductor region electrically connected to the fourth semiconductor region of the second conductivity type. Zhu876 also teaches that the semiconductor element includes a fifth semiconductor region (See Fig. 12 annotated above, elements 84 on the bottom of the semiconducting layer can be considered the fourth and fifth semiconductor regions and the TSV material (element 12) may be considered the second semiconductor region, “The conductive material may be a doped semiconductor material such as doped polysilicon or a doped silicon-containing semiconductor alloy”, para. [0028]), of the second conductivity type (“The second source and drain regions 84 may be formed by employing block level masks and ion implantation of electrical dopants, i.e., p-type dopants and n-type dopants”, para. [0045]) and the fourth semiconductor region.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the TSV structure disclosed in Zhu876 could be incorporated into the semiconductor layer disclosed in Larson215 in order to enable 3D integration with additional semiconductor devices, as explained in the rejection of claim 1. Such a modification could be made with a reasonable chance of success.
Regarding claim 4: Larson215 teaches that the material filling the trenches in the semiconducting layer is an insulating material. (“oxide isolation regions 17”, para. [0018]).
Regarding claim 6: Larosn215 and Zhu876 teach the limitations of claim 1. Zhu876 teaches that the first portion is arranged so as to surround the second portion (See Fig. 3 annotated below).
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Fig 3. From Zhu876: A trench (dielectric liner, element 10) electrically separates the first portion and the second portion. The first portion is defined to surround the second portion and the second portion is defined to surround the first portion.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device of Larson215 could be modified to include the wiring structure of Zhu876, and that such a modification would result in the 3D integration of the device being improved.
Regarding claim 7: The device according to claim 1, wherein the first portion forms at least a part of an outer edge of the semiconductor layer. (See Fig. 3, as annotated above, the first portion is defined to include the outside perimeter of the device.)
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Larson US (20130049215 A1), hereinafter referred to as “Larson215”, in view of Zhu (US 20100224876 A1) hereinafter referred to as “Zhu876”, and Yokoyama (US 20120248544 A1) hereinafter referred to as “Yokoyama544”.
Regarding claim 3: The device according to claim 1 is taught by Larson215 and Zhu876, these references do not teach that the semiconductor element includes at least one of a photodiode and an avalanche photodiode.
Yokoyama544 teaches that a semiconductor layer containing active regions of both the n-type and the p-type on opposite faces of the layer may be used in combination with a photodiode (”While, in the foregoing description of the embodiments, the case is described in which the semiconductor device includes a logic circuit device such as a CMOS inverter circuit or the like, the semiconductor device may be configured so as to further include a semiconductor device other than the logic circuit device. For example, the semiconductor device may be configured as a solid-state image pickup device in which a photoelectric conversion device such as a photodiode is provided for each of plural pixels”, para. [0702]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that a CMOS device could be used in combination with a photodiode such as to convert the electric signal into an image. The CMOS device and the photodiode are merely performing the same functions as they would independently.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Larson US (20130049215 A1), hereinafter referred to as “Larson215”, in view of Zhu (US 20100224876 A1) hereinafter referred to as “Zhu876”, and Huang et al. (US 20200126920 A1) hereinafter referred to as “Huang920”.
Regarding claim 10: Larson215 and Zhu876 teach the device according to claim 1, they do not explicitly show that the semiconductor layer is used as a first semiconductor layer, and the device further comprises a second semiconductor layer stacked on the first semiconductor layer via the first insulating layer. However, the wiring pattern disclosed in Zhu876 is for the purpose of increasing the 3D integration of the device (“Three-dimensional integration of semiconductor chips typically employs through-substrate vias (TSV's) that connect the front side of a semiconductor chip to a back side of the same semiconductor chip. Multiple semiconductor chips may be vertically stacked employing the through-substrate vias (TSV's). Such three-dimensional integration of semiconductor chips provides a higher device density per area than a single semiconductor chip without any vertical stacking, and reduces the size of a packaging substrate correspondingly.”, para. [0003]).
Huang920 teaches a semiconductor device that explicitly shows a second semiconducting layer (See at least Fig. 3, element 306, “second chip substrate”, para. [0034]) connected by a through-silicon via (See at least Fig. 3, element 318). Huang does not explicitly show the wiring pattern as claimed in claim 1. However, Huang920 states: “In some embodiments, the interconnect structure and the substrate at least partially define a first integrated chip, wherein the method further includes: forming a second integrated chip including a second interconnect structure and a second substrate; and bonding the first and second integrated chips together, such that the interconnect structure and the second interconnect structure are between the substrate and the second substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that multiple semiconductor layers would be stacked to form a 3D integrated circuit device, this was suggested by Zhu876 and shown explicitly in Huang920. Therefore, the device disclosed in Huang920 could be modified with the wiring pattern disclosed in Zhu876 with a reasonable expectation of success to arrive at the claimed invention.
Regarding claim 11: (The examiner notes that regions are being numbered by a convention that includes the withdrawn claim 8, while not necessarily improper, the examiner will interpret the 10th region to be separate from any other numbered region, not that there are 10 such regions) Huang920 teaches an electrode pad (See at least Fig. 3, element 116) for external connection is arranged in the first insulating layer (See at least Fig. 3, element 111), an opening portion extending through the first semiconductor layer (See at least Fig. 3, element 120) and configured to expose the electrode pad is arranged in the first semiconductor layer (See at least Fig. 3, element 106). Huang also teaches that there may be many semiconductor devices on the semiconducting layers even if they are not explicitly shown (“A plurality of logic devices 222 are between the array of pixel sensors 202 and at least one instance of the pad structure 104. For ease of illustration, only one of the logic devices 222 is labeled 222. The logic devices 222 may, for example, implement image signal processing (ISP) circuitry, read/write circuitry, some other suitable circuitry, or any combination of the foregoing.”, para. [0032]
Huang920 does not explicitly teach that the first semiconductor layer further includes a fourth portion between the second portion and the opening portion so as to surround the opening portion, the trench is used as a first trench, and a third trench extending through the first semiconductor layer so as to electrically separate the second portion and the fourth portion in the first semiconductor layer is arranged in the first semiconductor layer, the second portion further includes a 10th semiconductor region of the first conductivity type which forms a part of the first main surface, and an 11th semiconductor region of the second conductivity type which forms a part of the second main surface, the fourth portion includes a 12th semiconductor region of the first conductivity type which forms a part of the first main surface, and a 13th semiconductor region of the second conductivity type which forms a part of the second main surface, a fifth conductive path configured to electrically connect the 10th semiconductor region and the 12th semiconductor region is arranged in the first insulating layer, and a sixth conductive path configured to electrically connect the 11th semiconductor region and the 13th semiconductor region is arranged in the second insulating layer.
Zhu876 teaches that the through-silicon vias are surrounded by a dielectric liner layer (“Referring to FIGS. 2 and 3, dielectric liners 10 are formed on the sidewalls and bottom surfaces of the at least one deep via trench 2 and at least one deep marker trench 4 as well as on the first surface 7 of the semiconductor substrate 8.”, para. [0027]) which acts as trench that isolates active regions. A person of ordinary skill in the art would recognize that while prior art may only explicitly show one or two transistors, in reality, a semiconductor device may contain many more, as stated in Larson215: “In general, integrated circuit 10 may include a plurality of transistors (e.g., thousands, millions, billions, or more) and any number of interconnects 22a, 22b useful to form the desired connections between respective ones of the plurality of transistors.”, para. [0021]. Therefore, if the wiring pattern of claim 1 is obvious, then adding any number of semiconducting layers by vertically stacking, as in a 3D integrated circuit, or scaling horizontally by adding transistors in a semiconducting layer separated by any number of isolation trenches, into any number of semiconductor regions, with any number of individual conductive paths between adjacent active regions is also obvious, provided that the wiring structure could be incorporated with a reasonable expectation of success.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that a modification of the device disclosed in Huang920 to the wiring patterns disclosed in Zhu876 and Larson215 could be done with a reasonable expectation of success using the methods taught by Zhu876 and Larson215. Furthermore, Larson 215 states: “By forming the first interconnect on the first side of the layer and the second interconnect on the second side of the layer, interconnect density may be reduced and routing of interconnects may be simplified., [para. 0003]”, meaning such a modification would improve 3D integration and simplify the routing of the interconnections.
Regarding claim 12: Zhu 876 and Larson215 teach the device according to claim 1, but does not teach the additional limitations of claim 12.
Huang920 teaches that the semiconductor layer is used as a first semiconductor layer (See at least Fig. 3 element 306), and the device further comprises a second semiconductor layer stacked on the first semiconductor layer (See at least Fig. 3, element 106) via the first insulating layer ( See at least Fig. 3, element 111) an electrode pad for external connection is arranged in the first insulating layer (See at least Fig. 3, element 116) an opening portion extending through the first semiconductor layer and configured to expose the electrode pad is arranged in the first semiconductor layer (See at least Fig. 3, element 120) the first portion is arranged so as to surround the opening portion, and the second portion is arranged so as to surround the first portion (The specification does not define the first portion and the second portion, see Fig. 3 above for the examiner’s interpretation of the first and second portion, if the openings are in the first portion then the first portion surrounds them).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device disclosed in Huang920 could be modified with the wiring pattern taught by Zhu 876 and Larson 215 to improve 3D integration and reducing the density and complexity of the wiring patterns. This modification could be performed using the methods disclosed in Zhu 876 and Larson 215 with a reasonable expectation of success.
Claim(s) 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Larson US (20130049215 A1), hereinafter referred to as “Larson215”, in view of Zhu (US 20100224876 A1) hereinafter referred to as “Zhu876”, Huang et al. (US 20200126920 A1) hereinafter referred to as “Huang920”, and Yang et. al (US 20230049255 A1) hereinafter referred to as “Yang255”.
Regarding claim 13: Larson215 Zhu876 andHuang920 teach the device of claim 10. However, they do not explicitly teach that multiple semiconductor layers or wirings are electrically connected.
Yang255 teaches a device with three semiconductor layers (See at least Fig. 5, elements 102, 202, 302) where the electrical connection between semiconductor layer 202 and 302 are explicitly shown. Yang also teaches that many different circuits may be incorporated into a 3D integrated circuit device. “The first semiconductor wafer 101 and the second semiconductor wafer 201 may be sensor wafers and/or dies such as, for example, a backside illumination sensor (BIS) wafer and/or die, logic wafers and/or dies such as, for example, System-on-Chip (SOC) devices, application-specific integrated circuit (ASIC) devices comprising analog-to-digital converters, data processing circuits, memory circuits, bias circuits, reference circuits, any combinations thereof and/or the like.”, para. [0027]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that many different circuits may be integrated into a semiconductor device in many different ways, including having wiring that connects transistors on separate semiconducting layers as shown in Yang255. If the wiring pattern on claim 1 is obvious then making multiple copies of that wiring pattern or connecting the first or second conductive path to a semiconducting layer above or below it is also obvious.
Regarding claim 14: Zhu 876, Huang920, and Larson215 teach the limitations of claim 10. As explained in the rejections of claim 11 and claim 13 adding multiple copies of the wiring pattern in claim 1 or connecting the wiring pattern of claim 1 to additional semiconductor layers in a device is obvious if the wiring pattern of claim 1 is obvious, provided that it can be incorporated in the device with a reasonable expectation of success. Yang255 already has electrical connections between semiconductor surfaces connecting transistors, similar to Zhu875, therefore such a modification could be made with a reasonable expectation of success as discussed in the rejections of claim 11 and 13.
Regarding claims 15-17: Zhu 876, Huang920, Larson 215, and Yang255 teach the limitations of claim 14, claims 15-17 merely add more copies of the wiring pattern disclosed in claim 1 with additional connections between semiconductor layers. Therefore, claims 15 and 16 are rejected using the same reasoning as claim 11 and claim 13.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Larson US (20130049215 A1), hereinafter referred to as “Larson215”, in view of Zhu (US 20100224876 A1) hereinafter referred to as “Zhu876” and Han et al. (US 20150155233 A1) hereinafter referred to as Han233.
Regarding claim 20: Zhu876 and Larson215 teach the semiconductor device according to claim 1. They do not teach explicitly teach a processing device configured to process a signal output from the semiconductor device. In light of the specification, a processing device is interpreted by the examiner to be a CPU.
Han233 teaches the use of a semiconductor device (abstract) used in conjunction with a CPU (“A static random-access memory (SRAM) device 1221 may be used as a working memory of a central processing unit (CPU) 1222. A host interface unit 1223 may be configured to include a data communication protocol between the memory card 1200 and the host 1230. An error check and correction (ECC) block 1224 may detect and correct errors of data which are read out from the memory device 1210. A memory interface unit 1225 may interface with the memory device 1210. The CPU 1222 controls an overall operation of the memory controller 1220. The CPU 1222 may include at least one of the semiconductor devices 1 and 2 according to embodiments of the present inventive concepts.”, para. [0080]). Han233 teaches a semiconductor layer (See at least Fig. 1A, element 100) and a transistor (See at least Fig. 1A, element 111).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure a semiconductor device to a CPU. The semiconductor device and the CPU are mere performing the same functions that they would be independently. Furthermore, the wiring pattern of claim 1 could be incorporated into the semiconductor layer of the device disclosed by Han233 with a reasonable expectation of success using the methods as taught by Zhu876 and Larson215.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Yuan et al. (US 20130187280 A1) teaches transistors on both sides of a through-silicon via (TSV). Stuber (US 20150137307 A1) teaches transistors in series with front and backside wiring. Both could be used as evidence as to the obviousness of the wiring pattern of claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/ SPE, Art Unit 2898
Prosecution Insights