Prosecution Insights
Last updated: September 20, 2026
Application No. 18/591,188

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Feb 29, 2024
Priority
Sep 15, 2023 — JP 2023-150148
Examiner
NIX, NORA TAYLOR
Art Unit
4100
Tech Center
4100
Assignee
Kabushiki Kaisha Toshiba
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
79 granted / 88 resolved
+29.8% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
20 currently pending
Career history
103
Total Applications
across all art units

Statute-Specific Performance

§103
60.2%
+20.2% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 88 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Calafut et al. (US 20130075808 A1; hereinafter Calafut) in view of Inokuchi et al. (US 20220029012 A1; hereinafter Inokuchi). Regarding claim 1, FIG. 2 of Calafut teaches a semiconductor device (e.g. FIG. 2), comprising: a first electrode (21) including a first surface (upper surface of 21 ¶ [0019]); a major element (10) and a control element (20 ¶ [0019]), the control element (20) controlling the major element (10 ¶ [0003], control element 20 controls forward voltage drop and recovery time of major element 20), the major element (10) including the first electrode (21 ¶ [0021]), a second electrode (26 ¶ [0021]) positioned to be separated from the first electrode (21) in a first direction (direction extending between 21 and 26), the first direction (direction extending between 21 and 26) being along the first surface (upper surface of 21), a first semiconductor layer (24) located between the first electrode (21) and the second electrode (26 ¶ [0021]) in the first direction (direction extending between 21 and 26), and a first gate electrode (14 ¶ [0020]) facing the first semiconductor layer (24) in a second direction (direction extending between 17 and 19), the second direction (direction extending between 17 and 19) being along the first surface (upper surface of 21) and crossing the first direction (direction extending between 21 and 26), the control element (20) including a third electrode (13b ¶ [0025]), a fourth electrode (28 ¶ [0024]) positioned to be separated from the third electrode (13b) in a fourth direction (direction between 13b and 28), the fourth direction (direction between 13b and 28) being along the first surface (upper surface of 21), a second semiconductor layer (22 ¶ [0019]) located between the third electrode (13b) and the fourth electrode (28) in the fourth direction (direction extending between 13b and 28), the second semiconductor layer (22) forming a second Schottky junction (junction between 22 and 28) with the fourth electrode (28 ¶ [0024]), and a second gate electrode (13c ¶ [0020]) facing the second Schottky junction (junction between 22 and 28) in a fifth direction (direction extending between 13c and 28), the fifth direction (direction extending between 13c and 28) being along the first surface (upper surface of 21) and crossing the fourth direction (direction extending between 13b and 28). Calafut does not teach a support body. FIG. 1 of Inokuchi teaches a semiconductor device (110 ¶ [0040]), comprising: a support body (50S) including a first surface (50F ¶ [0040]-[0041]); a major element (major element on 50F shown in FIG. 1) located on the support body (50S). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Calafut with the support body taught by Inokuchi for the purpose of increasing the device density and channel surface area per unit area and reducing on-resistance (¶ [0060],[0067]). Regarding claim 2, Calafut as modified teaches the device according to claim 1, and FIG. 1 of Inokuchi further teaches wherein the support body (50S) includes a substrate (50u ¶ [0041]), and a first semiconductor layer (11e) and a second semiconductor layer (11c) each are located on the substrate (50u ¶ [0068],[0047]). Regarding claim 3, Calafut as modified teaches the device according to claim 2, and FIG. 1 of Inokuchi further teaches wherein the substrate (50u) includes a second surface (upper surface of 50u) positioned at a side opposite to the first surface (side of 50x opposite to 50F) in a third direction (z direction) crossing a first direction (y direction) and a second direction (x direction). Calafut and Inokuchi alone do not teach the third and fourth electrodes of the control element are positioned on the first surface but not positioned at the second surface. However, FIG. 2 of Calafut in view of FIG. 1 of Inokuchi further teaches the third and fourth electrodes (13b, 28 of Calafut) of the control element (20 of Calafut) are positioned on the first surface (50F of Inokuchi) but not positioned at the second surface (upper surface of 50u). Allowable Subject Matter Claims 4-5 and 8-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 4 recites the device according to claim 1, wherein a thickness in the first direction of the first semiconductor layer is greater than a thickness in the fourth direction of the second semiconductor layer. Calafut in view of Inokuchi teaches the device according to claim 1. However, the prior art fails to teach or reasonably suggest “wherein a thickness in the first direction of the first semiconductor layer is greater than a thickness in the fourth direction of the second semiconductor layer” together with all the limitations of claims 1 and 4 as claimed. Clam 5 recites the device according to claim 1, wherein a plurality of the control elements forms a NOT circuit. Calafut in view of Inokuchi teaches the device according to claim 1. However, the prior art fails to teach or reasonably suggest “wherein a plurality of the control elements forms a NOT circuit” together with all the limitations of claims 1 and 5 as claimed. Claim 8 recites the device according to claim 1, wherein at least one of the third electrode or the fourth electrode of the control element is electrically connected with the first gate electrode of the major element. Calafut in view of Inokuchi teaches the device according to claim 1. However, the prior art fails to teach or reasonably suggest “wherein at least one of the third electrode or the fourth electrode of the control element is electrically connected with the first gate electrode of the major element” together with all the limitations of claims 1 and 8 as claimed. Claim 9 recites the device according to claim 3, wherein the major element further includes an inter-layer insulating layer, and the inter-layer insulating layer contacts a top of the first semiconductor layer in the third direction. Calafut in view of Inokuchi teaches the device according to claim 3. FIG. 2 of Calafut teaches wherein the major element (10) further includes an inter-layer insulating layer (18 ¶ [0021]), and the inter-layer insulating layer (18) contacts a top of the first semiconductor layer (top of 24). However, the prior art fails to teach or reasonably suggest “the inter-layer insulating layer contacts a top of the first semiconductor layer in the third direction” together with all the limitations of claims 1-3 and 9 as claimed. Claim 10 contains allowable subject matter insofar as it depends upon and requires all the limitations of claims 1-3 and 9. Claim 11 recites the device according to claim 3, comprising: a plurality of the control elements, the plurality of control elements including at least a first control element and a second control element, the second control element being positioned in the fourth direction with respect to the first control element, the fourth electrode of the first control element and the third electrode of the second control element being connected as a continuous body. Calafut in view of Inokuchi teaches the device according to claim 3. However, the prior art fails to teach or reasonably suggest “comprising: a plurality of the control elements, the plurality of control elements including at least a first control element and a second control element, the second control element being positioned in the fourth direction with respect to the first control element, the fourth electrode of the first control element and the third electrode of the second control element being connected as a continuous body” together with all the limitations of claims 1-3 and 11 as claimed. Claim 12 contains allowable subject matter insofar as it depends upon and requires all the limitations of claims 1-3 and 11. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nora T. Nix/Assistant Examiner, Art Unit 2891 /MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Feb 29, 2024
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+9.4%)
3y 1m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 88 resolved cases by this examiner. Grant probability derived from career allowance rate.

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