DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06 April 2026 have been fully considered but they are not persuasive.
While the amendment clarifies that the source (an active region) of the equalizing transistor connects to the wiring structure, the bitline, via a direct contact, in order to overcome the Seo reference (US Pat 11,024,365), this feature is further considered and believed to be taught by Chang et al (US Pat 2008/0062790) in para 0045 with respect to fig. 3.
This establishes ground for the final rejection which follows.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US Pat 11,024,365) in view of Chang et al. (US Pat Pub 2008/0062790).
Regarding claim 1 and 11, Seo et al. disclose a bit-line sense amplifier (160, fig. 1, and figs. 6A&6B and all related texts) comprising:
an amplifying circuit (referred to as sense amplifying circuit 165, fig. 6A/6B) connected to a bit-line and a complementary bit-line (SBL & SBLB, fig. 6A/6B), the amplifying circuit (165) configured to sense a voltage difference between the bit-line and the complementary bit-line (BL/BLB, fig. 6A/6B) based on a first control signal and a second control signal (control signals, col. 4, line 62 – col. 5, line 14), and adjust a voltage of a sensing bit-line and a complementary sensing bit-line based on the voltage difference (as shown in fig. 10, voltage difference between Ble/BLBe is sensed and amplified in SBLe/SBLBe; voltage difference between Blo/BLBo is sensed and amplified in SBLo/SBLBo);
an isolation circuit configured to connect the bit-line and the complementary bit-line to the sensing bit-line and the complementary sensing bit-line, respectively (referred to as ISO circuits 161 and 162, ISO_1 and ISO_2), based on an isolation signal (ISO, fig. 6A/6B);
an offset cancellation circuit (163/164, fig. 6A/6B) configured to connect the bit-line and the complementary bit-line to the complementary sensing bit-line and the sensing bit-line (as shown), respectively, based on an offset cancellation signal (OC); and
an equalizer (including transistors EQ1, EQ2, EQ3, fig. 6A/6B) connected to the sensing bit-line (BL/BLB), the equalizer configured to equalize the bit-line and the complementary bit-line to a precharge voltage (VPRE, see col. 5, lines 51 – 58), based on an equalizing signal (PEQ, P3_E, P3_O, fig. 6A/6B),
wherein the equalizer includes an equalizing transistor (for example the equalizing transistor EQ1, fig. 6A/6B) that has a source (connected to SBLB), a gate configured to receive the equalizing signal (PEQ), and a drain (connected to receive signal VPRE), and
wherein the source of the equalizing transistor is connected to a wiring structure through a direct contact (as shown for example fig. 14A – 21B), and the wiring structure is configured to receive the precharge voltage (as shown for example in fig. 14A, EQ1 transistor is configured to receive VPRE through direct contact as shown in the upper portion of fig. 14A – 15B).
Seo et al. disclose the bit-line sense amplifier as set forth above except wherein the direct contact directly connects the source of the equalizing transistor, the wiring structure, and the sensing bit-line.
This feature is taught by Chang et al. (figs. 1 – 3 and para 0045 discloses an active region ACTIVE_TR of equalizing transistor connects to the bitlines BL&/BL via a direct contact. The wiring structure is considered as the bit-line/inverted bit-line constructing bit-line pair and forms the source/drain of the equalizing transistors).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the references as cited, so that equalizing time may be improved (see abstract).
Allowable Subject Matter
Claims 2 – 10 and 12 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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/LY D PHAM/Primary Examiner, Art Unit 2827 April 22, 2026
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