DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I and the species shown in Fig. 15A, directed to claims 1-4, 6, 11, and 12 in the reply filed on 07/02/2026 is acknowledged.
Claims 5 and 7-10 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/02/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 3: The claim limitation “wherein a width of the plate-shaped portion in the second lateral direction is narrower than a width of an upper end portion of the plate-shaped portion at a height position of the semiconductor layer.” The examiner interprets this claim limitation to mean that the plate-shaped portion is narrower at some point other than at the top of semiconducting layer. However, looking at the plate shaped portion in Fig. 2A of the application for example, the plate shaped portion (elements 55 and 25) have their narrowest width at the top of the semiconducting layer (elements SPb) and therefore there is no portion of the plate-shaped portion that is narrower than at the top of the semiconducting layer. Since the claim language appears to directly contradict what is shown in the specification, claim 3 is rejected on the basis of not being supported by the specification. The examiner will interpret this limitation to read “The plate-shaped portion is narrower at the top of the semiconductor layer than at another portion of the plate-shaped portion”.
Claims 2 and 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 2 and 3: recites the limitation "the second lateral direction" in paragraph 2 of claim 2 and paragraph 2 of claim 3. There is insufficient antecedent basis for this limitation in the claim.
It is unclear to the examiner if the “second lateral direction” of claims 2 and 3 is the same direction as the “second direction” of claim 1 or a different direction, making the scope of the claims unclear. The examiner will interpret the second lateral direction to mean the second direction for the purposes of examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20210305266 A1), hereinafter referred to as “Lee266”.
Regarding claim 1: Lee266 teaches a semiconductor storage device (“memory device”, abstract) comprising: a stacked body including a plurality of conductive layers (See Fig. 26 conductive layers 146) and a plurality of insulating layers (See Fig. 26 insulating layers 132) alternately stacked on top of one another in a stacking direction (See Fig. 26, annotated below); a first region extending in a first direction (See Fig. 25B annotated below) intersecting the stacking direction and has a width in a second direction (See Fig. 25B annotated below) intersecting the stacking direction and the first direction (See Fig. 25B annotated below); a plurality of first pillars (Fig. 26, support pillar structures 20) disposed in a second region on a first side of the first region in the second direction (See Fig. 25B annotated below), and each extending in the stacked body, wherein first memory cells are formed at intersections between the plurality of conductive layers and the plurality of first pillars (See Fig. 26 annotated below, “The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.”, para. [0122]), respectively; a plurality of second pillars disposed in a third region on a second side of the first region in the second direction (See Fig. 25B annotated below), and each extending in the stacked body, and wherein second memory cells are formed at intersections between the plurality of conductive layers and the plurality of second pillars, respectively (Third region in Fig. 25B is identical to second region in structure); a plate-shaped portion disposed in the first region (See Figs. 25B and 26, dielectric wall structure 176), extending in the first direction, and dividing the stacked body in the second direction (See Fig. 25B and 26); and a semiconductor layer disposed in the first region adjacent to the plate-shaped portion in the second direction (See Fig. 26 The etch stop layer 180 is laterally adjacent to the dielectric wall structure 176, and deposited on all sides of the wall structure 176 surrounding it in the lateral directions), the semiconductor layer having an upper end portion around upper end portions of the plurality of first and second pillars (See at least Fig. 12A, The upper side of etch stop layer 180 is shown to be flush with the tops of the pillars in the first stacking layer, which includes first and second pillars), and a lower end portion above an uppermost conductive layer of the plurality of conductive layers (See at least Fig. 26, The lower edge of etch stop layer 180 is above the top-most conductive layer 146 in the first stacked structure).
Regarding claim 2: In addition to the limitations of claim 1, as best understood Lee266 teaches that the semiconductor layer (Etch stop layer 180) is disposed on both sides of the plate-shaped portion in the second lateral direction (Etch stop layer 180 is deposited over the first stacked body and extends in both the first and second directions).
Regarding claim 4: In addition to the limitations of claim 1, Lee266 teaches that the semiconductor layer continuously extends in the first lateral direction along the plate-shaped portion. (Etch stop layer 180 is deposited over the first stacked body and extends in both the first and second directions).
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Annotated Fig 25B from Lee266: Second region and first pillars have identical structure to third region and second pillars. First region is defined as area between first and second pillars. Regions are indicated by dashed outlines.
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Annotated Fig. 26 from Lee266: Plate-shaped portion 176 extends through the first and second stacked body.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee266 (US 20210305266 A1) hereinafter referred to as “Lee266”.
Regarding claim 6: Lee266 teaches a semiconductor storage device comprising: a first stacked body including a plurality of first conductive layers and a plurality of first insulating layers alternately stacked on top of one another in a stacking direction (See Fig 26 annotated above, conducting layers 146, and insulating layers 132); a second stacked body disposed above the first stacked body (See Fig. 26 annotated above, and including a plurality of second conductive layers and a plurality of second insulating layers alternately stacked on top of one another in the stacking direction (See Fig. 26 annotated above, conducting layers 246 and insulating layers 232); a first region that extends in a first direction intersecting the stacking direction and has a width in a second direction intersecting the stacking direction and the first direction; a plurality of first pillars disposed in a second region on a first side of the first region in the second direction, and each extending in the first and second stacked bodies (See Fig. 25B annotated above) wherein first memory cells are formed at intersections between the plurality of first and second conductive layers and the plurality of first pillars, respectively; a plurality of second pillars disposed in a third region on a second side of the first region in the second direction, and each extending in the first and second stacked bodies, wherein second memory cells are formed at intersections between the plurality of first and second conductive layers and the plurality of second pillars, respectively (See Fig. 26 annotated below, “The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.”, para. [0122], second and third regions have identical structure forming first and second memory cells); a plate-shaped portion disposed in the first region, extending in the first direction, and dividing the first and second stacked bodies in the second direction (See Figs. 25B and 26 annotated above, plate-shaped portion 176 extends through first and second stacked body); a first semiconductor layer disposed in the first region adjacent to the plate-shaped portion in the second direction and in an uppermost first insulating layer among the plurality of first insulating layers (See at least Fig. 12A, etch stop layer 180 is above top-most insulating layer 132);
Lee266 does not explicitly teach a second semiconductor layer disposed in the first region adjacent to the plate-shaped portion in the second direction and in an uppermost second insulating layer of the plurality of second insulating layers in the same embodiment as discussed above. However, Lee266 discloses another embodiment with two semiconducting layers where the second semiconducting layer is above the top-most insulating layer of the second stacked body (See Fig. 32, second etch-stop layer 280 is above top-most insulating layer 232, “The schemes of the various embodiments of the present disclosure may be extended to structures including more than two tier structures. Referring to FIG. 32, a fourth alternative configuration of the exemplary structure is illustrated, which can be derived from the exemplary structure illustrated in FIGS. 7A and 7B by forming a second etch stop material layer 280 and not forming an insulating cap layer 270 prior to formation of the various second-tier openings and sacrificial second-tier opening fill structures 348, by forming a third alternating stack of third insulating layers 932 and third sacrificial material layers 942 and by forming an insulating cap layer 270, by forming third-tier memory openings and third-tier support openings, and by performing the processing steps of FIGS. 8-30 as described above with necessary adjustments to the various processing steps in view of the presence of the third alternating stack (932, 942). Generally, the methods and the structures of the present disclosure can be extended to structures including three or more alternating stacks and two or more etch stop material layers.”, para. [0208]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device disclosed in Fig. 26 could be modified to include a third stacking layer and a second etch stop layer, as shown in Fig. 32, to arrive at the claimed invention. Each additional stacking layer would be performing the same function as it would separately and the results of adding more stacking layers is predictable.
Claim(s) 3, 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210305266 A1), hereinafter referred to as “Lee266” in view of Nishikawa (US 20210249434 A1), hereinafter referred to as Nishikawa434.
Regarding claim 3: Lee266 teaches the limitations of claim 2. Lee266 does not teach that a width of the plate-shaped portion in the second lateral direction is narrower than a width of an upper end portion of the plate-shaped portion at a height position of the semiconductor layer.
Nishikawa434 teaches a plate-shaped portion (See at least Fig. 2A elements 51 and 20 are considered the plate-shaped portion) with a bowed shape (See at least Fig. 2A, The top of the plate shape portion is narrower near the top) the stacked structure taught by Nishikawa is designed to suppress a leakage current (“With the semiconductor storage device 1 in the embodiment, the diameter of the bottom surface of the columnar portion HM is larger than the width of the widest portion of the beam portion BM. Consequently, even after the upper end portion of the main body portion MPb of the trench TRb to be the beam portion BM is closed, the material gas of the insulating layer, which is a filler, is supplied through the opening of the end portion EDb of the trench TRb to be the columnar portion HM. Accordingly, the void is suppressed from remaining in the beam portion BM. Therefore, even if a divided surface of the beam portion BM by the slit ST is exposed in the slit ST, the conductive layer is not filled. It is possible to suppress a leak current from occurring between the conductive layer and the word line.” Para. [0133])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the stacked structure disclosed in Lee266 could be modified to that disclosed in Nishikawa434 to arrive at the claimed invention (Since the plate shaped portion is narrower at the top where the semiconducting etch stop layer would be). Such a modification would have the advantage of suppressing the leak current from occurring between the conductive layer and the word line. This could be performed following the methods disclosed in Nishikawa434 during the formation of the stacked word line structures in the memory device with a reasonable chance of success.
Regarding claim 11: Lee266 teaches the limitations of claim 1. Lee 266 does not teach that the plate shaped portion contains a conductive material.
Nishikawa434 teaches that a conductive layer fills the plate-shaped portion (See at least Fig. 2A, “The contact LI including the conductive layer 20 connected to the plug V0 is disposed on the n.sup.+ diffused region 13 of the substrate SB, whereby the contact LI functions as, for example, source line contacts. However, instead of the contact LI, an insulating layer such as an SiO.sub.2 layer may divide the stacked bodies LMa and LMb in the Y direction”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device disclosed in Lee266 could be modified to include a conductive material into the plate shaped portion to arrive at the claimed invention. This would add functionality to the device allowing the plate-shaped portion to serve as a source line contact. Nishikawa434 discloses that the plate shaped portion may also be an insulating layer as was disclosed in Lee266, therefore such a modification could be made with a reasonable expectation of success.
Regarding claim 12: As discussed in the rejection of claim 6, Lee266 teaches all aspects of the device claimed in claim 6 by combining two embodiments to form a memory device with three or more stacked sections and two or more semiconducting layers. Lee266 does not teach that the plate shaped portion contains a conductive material.
Nishikawa434 teaches that a conductive layer fills the plate-shaped portion (See at least Fig. 2A, “The contact LI including the conductive layer 20 connected to the plug V0 is disposed on the n.sup.+ diffused region 13 of the substrate SB, whereby the contact LI functions as, for example, source line contacts. However, instead of the contact LI, an insulating layer such as an SiO.sub.2 layer may divide the stacked bodies LMa and LMb in the Y direction”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the device disclosed Lee266, modified to have three or more stacked layers, could be further modified to include a conductive material into the plate shaped portion to arrive at the claimed invention. This would add functionality to the device allowing the plate-shaped portion to serve as a source line contact. Nishikawa434 discloses that the plate shaped portion may also be an insulating layer as was disclosed in Lee266, therefore such a modification could be made with a reasonable expectation of success.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure:
Hossain et al. (US 20210327885 A1) teaches a method to reduce processing errors in stacked memory device layers by using a semiconducting layer as an etch stop. Zhang et al. (US 9570463 B1) teaches a semiconductor layer deposited between word line stacks in a memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/ SPE, Art Unit 2898
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