DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, Species 1 in the reply filed on 06/24/2026 is acknowledged.
Claim Objections
Claim 23 is objected to because of the following informalities:
Claim 23 recites “a with” should be width.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-23, 25-27, 30, 33 and 36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. 20230066284.
Regarding claim 17, figs. 3/4-8 of Huang disclose a method for forming an integrated circuit (IC) structure, comprising:
forming a stack of layers (110/112) over a base substrate 402 (fig. 5), wherein the stack of layers includes an etch stop layer 112 (this will stop some type of etch) over the base substrate and a lower semiconductor layer 110 (pa [0017]) on the etch stop layer;
forming a plurality of semiconductor devices (transistors) on the lower semiconductor layer;
forming a first interconnect structure 108 on a frontside of the plurality of semiconductor devices, wherein the first interconnect structure comprises a plurality of first conductive interconnects disposed in a first dielectric structure 109;
bonding the first interconnect structure to a carrier substrate 102 (fig. 8);
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removing the base substrate, the etch stop layer, and the lower semiconductor layer from over a backside of the plurality of semiconductor devices (fig. 10 show the base substrate, the etch stop layer, and the lower semiconductor layer of fig. 5 is removed as the structure is fig. 10 is now the same as that of fig. 5 and therefore, the stacks of layer over base substrate 402 of fig. 5 is removed to form that of fig. 10),
where the backside is opposite the frontside; and
forming a first high thermal conductivity layer 112 on the backside of the plurality of semiconductor devices.
Regarding claim 26, Huang discloses a method for forming an integrated circuit (IC) structure, comprising:
depositing a first thermal conductivity layer 112 (pa r[0016]) on a semiconductor layer 402;
forming a semiconductor device (110 is a device which comprises 120 transistor) on the first thermal conductivity layer, wherein the semiconductor device comprises a gate structure 202 between a pair of source/drain structures,
wherein the first thermal conductivity layer abuts a first side of the semiconductor device and interfaces with the gate structure;
forming an interconnect structure 108 on a second side of the semiconductor device opposite the first side, wherein the interconnect structure comprises a plurality of conductive wires in a plurality of inter-level dielectric (ILD) layers 109 (interconnect dielectric structures which has multiple layers between the interconnects and vias),
wherein a thermal conductivity of at least one of the plurality of ILD layers is less than a thermal conductivity of the first thermal conductivity layer (this is necessary the case as – see pa [0014]) ;
bonding the interconnect structure to a substrate 102 (fig. 8);
performing a removal process to remove the semiconductor layer and expose the first thermal conductivity layer (fig. 10); and
forming a pair of conductive contacts 112 (fig. 11 shows on 118 which is on source/drain and therefore are on) on the pair of source/drain structures, wherein the first thermal conductivity layer extends laterally between the pair of conductive contacts.
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Regarding claim 33, fig. 3 of Huang discloses a method for forming an integrated circuit (IC) structure, comprising:
forming a plurality of semiconductor devices 120 (of layer 101) on a first thermal conductivity layer 112 (fig. 3), wherein the first thermal conductivity layer 112 is arranged on a first side (110b) of the plurality of semiconductor devices;
forming an etch stop layer 110 (fig. 3) on the first thermal conductivity layer, wherein a thermal conductivity of the first thermal conductivity layer is greater than a thermal conductivity of the etch stop layer (this is necessary the case as a first high-temperature heat dispersion layer 112 – see par [0014]);
forming a first interconnect structure 108 (of layer 101) on a second side (110t) of the plurality of semiconductor devices opposite the first side,
wherein the first interconnect structure comprises a first plurality of conductive contacts in a first dielectric layer 109 and on the plurality of semiconductor devices (fig. 8),
wherein the etch stop layer 110 is arranged between the first dielectric layer 109 and the first thermal conductivity layer 112;
depositing a second thermal conductivity layer 112 (of layer 103) on the first thermal conductivity layer and the first etch stop layer; and
forming a second interconnect structure (as labeled by examiner above) on the first side of the plurality of semiconductor devices,
wherein the second interconnect structure comprises a second plurality of conductive contacts (as labeled by examiner above) extending through the first 112 and second 112 thermal conductivity layers to contact the plurality of semiconductor devices (see 122 contacts 108 and 108 contacts 120s).
Regarding claim 35, par [0020] of Huang discloses wherein the first and second thermal conductivity layers have a cubic crystalline structure (same material as that listed by applicant’s specification).
Regarding claim 18, par [0014] of Huang discloses wherein a thermal conductivity of the first high thermal conductivity layer is greater than that of the etch stop layer.
Regarding claim 19, fig. 11 of Huang discloses further comprising: forming a plurality of conductive contacts 122 in the first high thermal conductivity layer, wherein the conductive contacts contact the semiconductor devices.
Regarding claim 20, par [0035] of Huang discloses wherein the first high thermal conductivity layer is formed by physical vapor deposition (PVD), chemical vapordeposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD) at a temperature within a range of about 100 to 400 degrees Celsius.
Regarding claim 21 (see rejection claim 33), Huang discloses further comprising: depositing a second high thermal conductivity layer on the first high thermal conductivity layer; and depositing a first dielectric layer on the second high thermal conductivity layer, wherein thermal conductivities of the first and second high thermal conductivity layers are greater than a thermal conductivity of the first dielectric layer; wherein the plurality of conductive contacts extend through the first dielectric layer and the second high thermal conductivity layer.
Regarding claim 22, fig. 3 of Huang discloses wherein forming the plurality of conductive contacts comprises: etching the first high thermal conductivity layer, the second high thermal conductivity layer, and the first dielectric layer to form openings over the plurality of semiconductor devices; depositing a conductive material in the openings; and performing a planarization process on the conductive material (CMP – par [0048]).
Regarding claim 25, fig. 5 of Huang discloses wherein the first high thermal conductivity layer is formed before the first interconnect structure.
Regarding claim 27, fig. 3 of Huang (see rejection of claim 33 above) further comprising: depositing a second thermal conductivity layer on the first thermal conductivity layer, wherein the second thermal conductivity layer contacts sidewalls of the first thermal conductivity layer.
Regarding claim 30, fig. 3 of Huang discloses further comprising: depositing a first dielectric layer 109 on the second thermal conductivity layer, wherein the first dielectric layer extends between the pair of conductive contacts 122s; depositing a third thermal conductivity layer 104 on the first dielectric layer; and depositing a second dielectric layer 106 on the third thermal conductivity layer, wherein thermal conductivities of the second and third thermal conductivity layers are greater than thermal conductivities of the first and second dielectric layers (it is necessary case as the second and third thermal conductivity layers are high-temperature heat dispersion layer).
Regarding claim 36, par [0020] of Huang discloses wherein the first thermal conductivity layer comprises one or more of aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond- like carbon, and diamond.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23-24, 28-29, 31-32 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Huang
Regarding claim 23, fig. 3 of Huang discloses wherein a first conductive contact of the plurality of conductive contacts has a first segment in the first dielectric layer and a second segment in the first and second high thermal conductivity layers.
Huang does not disclose wherein a with of the first segment is greater than a width of the second segment.
MPEP § 2144.04 (IV) cites Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), which held that where the only difference between the prior art and the claims was a recitation of relative dimensions, and a device with those dimensions would not perform differently, the claimed device was not patentably distinct
As such it would have been obvious to form a structure comprising wherein a with of the first segment is greater than a width of the second segment in order to accommodate process variation.
Regarding claim 24, Huang discloses wherein a lateral surface of the first segment directly contacts a lateral surface of the second high thermal conductivity layer.
Regarding claim 28, Huang does not disclose of wherein a thickness of the first thermal conductivity layer is less than a thickness of the second thermal conductivity layer.
MPEP § 2144.04 (IV) cites Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), which held that where the only difference between the prior art and the claims was a recitation of relative dimensions, and a device with those dimensions would not perform differently, the claimed device was not patentably distinct
As such it would have been obvious to form a structure comprising wherein a thickness of the first thermal conductivity layer is less than a thickness of the second thermal conductivity layer in order to accommodate heat requirement.
Regarding claim 29, par [0020] of discloses high-temperature heat dispersion layers 112 comprise a dielectric material, such as aluminum nitride (e.g., AlN), aluminum oxide (e.g., Al.sub.2O.sub.3), silicon nitride (e.g., Si.sub.3N.sub.4), silicon carbide (e.g., SiC), carbon (e.g., such as diamond, graphene, or the like), boron nitride (e.g., BN), beryllium oxide (e.g., BeO), magnesium oxide (e.g., MgO), another suitable material, or any combination of the foregoing.
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v.Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
As such it would have been obvious to form a structure comprising wherein the first thermal conductivity layer comprises a first material and the second thermal conductivity layer comprises a second material different from the first material in order to accommodate heat requirement.
Regarding claim 31, Huang does not disclose of wherein a thickness of the second dielectric layer is greater than a thickness of the third thermal conductivity layer.
MPEP § 2144.04 (IV) cites Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), which held that where the only difference between the prior art and the claims was a recitation of relative dimensions, and a device with those dimensions would not perform differently, the claimed device was not patentably distinct
As such it would have been obvious to form a structure comprising wherein a thickness of the second dielectric layer is greater than a thickness of the third thermal conductivity layer in order to accommodate heat requirement.
wherein a thickness of the second dielectric layer is greater than a thickness of the third thermal conductivity layer.
Regarding claim 32, fig. 3 of Huang disclose of I/O contact 216. As such it would have been obvious to form a structure further comprising: etching the third thermal conductivity layer and the second dielectric layer to form openings over the pair of conductive contacts; and forming a pair of conductive interconnects in the openings, wherein a bottom surface of the pair of conductive interconnects is aligned with a bottom surface of the third thermal conductivity layer in order to provide electrical connections to the I/O contact 216.
Regarding claim 34, Huang does not discloses of wherein a thickness of the first thermal conductivity layer is greater than a thickness of the etch stop layer.
MPEP § 2144.04 (IV) cites Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), which held that where the only difference between the prior art and the claims was a recitation of relative dimensions, and a device with those dimensions would not perform differently, the claimed device was not patentably distinct
As such it would have been obvious to form a structure comprising wherein a thickness of the first thermal conductivity layer is greater than a thickness of the etch stop layer in order to accommodate heat requirement.
Conclusion
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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