DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 16 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 8, 12, 13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and correction of the 112 Rejection below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16 – 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 16 states: “without another ground via being positioned between the single ground via and the first pair of signal vias and between the single ground via and the second pair of signal vias along the axis”.
As seen by Applicant’s Specification, [0027-0000], the Applicant describes the via layout, however the Applicant does not provide any specific limitations to the lacking or abstaining of vias or holes in the board. Thus, the Applicant’s Specification does not explicitly disclose a structure that is without another ground via being positioned between the single ground via and the first pair of signal vias and between the single ground via and the second pair of signal vias along the axis. In other words, the disclosure does not explicitly teach the negative limitation of “without another ground via being positioned between the single ground via and the first pair of signal vias and between the single ground via and the second pair of signal vias along the axis”. See MPEP 2173.05(i) stating that any negative limitation or exclusionary proviso must have basis in the original disclosure.
Claims 17 – 20 are rejected due to dependency from claim 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 7, 11, 14 and 16 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gingrich (US 2024/0145994 A1) in view of Loffink (US 10,522,949 B1).
Regarding Claim 1, Gingrich (US 2024/0145994 A1) discloses an apparatus (Fig 1-4) comprising: a layer (layer as seen in Fig 4 would have some thickness) of a printed circuit board (16); a first pair of signal vias (pair of 60 in left-side box in Fig 4; annotated FIRST PAIR OF SIGNAL VIAS) extending through the layer and configured to propagate respective signals ([0031]); a second pair of signal vias (other adjacent pair of 60 in right-side box in Fig 4; annotated SECOND PAIR OF SIGNAL VIAS) extending through the layer and configured to propagate respective signals ([0031]); a first plurality of ground vias (a plurality of 70,72a,72b,72c at least partially surrounding 60 on left side of Fig 4) extending through the layer and at least partially circumferentially surrounding (see Fig 4 showing 70,72 vias at least partially surround pair of 60 in left-side box in Fig 4) a first signal via (60) of the first pair of signal vias, wherein each ground via (70 or 72) of the first plurality of ground vias is positioned at a distance (see Fig 1-4 showing a distance between vias) away from the first signal via (60); and a second plurality of ground vias (a plurality of 70,72a,72b,72c at least partially surrounding 60 on right side of Fig 4) extending through the layer and at least partially circumferentially surrounding (see Fig 4 showing 70,72 vias at least partially surround pair of 60 in right-side box in Fig 4) a second signal via (60) of the second pair of signal vias, and the first plurality of ground vias (a plurality of 70,72a,72b,72c) and the second plurality of ground vias (a plurality of 70,72a,72b,72c) share a common ground via (as the claim language allows overlapping of ground vias within the first plurality of ground vias and second plurality of ground vias, a single 70 or 72a or 72b or 72c among the plurality of ground vias can be construed as a shared or common ground via shared by both pluralities).
Gingrich is in the field of pins interfacing with vias in the printed circuit board ([0049] “the pattern or positioning of the signal contact vias 70 and the ground contact receiving vias 90 matches the pattern of the signal mounting pins 26 and the ground mounting pins 28 of the daughtercard circuit board 18”), however Gingrich does not explicitly disclose wherein each ground via of the second plurality of ground vias is positioned at the distance away from the second signal via, and wherein each ground via of the second plurality of ground vias is positioned at the distance away from the second signal via, and the first plurality of ground vias and the second plurality of ground vias share a common ground via positioned at the distance away from the first signal via and the second signal via.
Loffink (US 10,522,949 B1), also in the field of pin layouts and vias (Column 1, lines 5-10) teaches of an apparatus (Fig 9) comprising: a layer of a printed circuit board (Column 1, lines 5-10); a first pair of signal pins (pair of 25 at lower left most side of Fig 9) extending through the layer (pins would have some three-dimensional depth through the Fig 9 and into the view of Fig 9) and configured to propagate respective signals (Column 10, lines 1-3,65-68; “differential signal pair 25”, “signal pins 27,29”); a second pair of signal pins (pair of 25 at upper left most side of Fig 9) extending through the layer and configured to propagate respective signals (Column 10, lines 1-3,65-68); a first plurality of ground pins (17; annotated FIRST PLURALITY OF GROUND PINS; Column 5, lines 1-10 “ground pin”) extending through the layer and at least partially circumferentially surrounding (see Fig 9 showing; left most row of 17 partially circumferentially surrounding leftmost column of 25) a first signal pin (27; annotated FIRST SIGNAL PIN) of the first pair of signal vias (25), wherein each ground pin (17) of the first plurality of ground vias (17; annotated FIRST PLURALITY OF GROUND PINS) is positioned at a distance (Column 10, lines 40-46 “for each pin that has a plurality of immediate neighbor pins, that pin is equidistant or substantially equidistant from each of its immediate neighbor pins. Also preferably, a distance between any two immediate neighbor pins is equal to a distance between any other two immediate neighbor pins”) away from the first signal pin (27); and a second plurality of ground pins (17; annotated SECOND PLURALITY OF GROUND PINS; Column 5, lines 1-10 “ground pin”) extending through the layer and at least partially circumferentially surrounding (see Fig 9 showing; left most row of 17 partially circumferentially surrounding leftmost column of 25) a second signal pin (29; annotated SECOND SIGNAL PIN) of the second pair of signal pins, wherein each ground pin (17) of the second plurality of ground pins is positioned at the distance (Column 10, lines 40-46 “equidistant or substantially equidistant”, “equal”) away from the second signal pin (29; annotated SECOND SIGNAL PIN), and the first plurality of ground pins (17) and the second plurality of ground pins (17) share a common ground pin (17; annotated COMMON GROUND PIN) positioned at the distance (Column 10, lines 40-46 “equidistant or substantially equidistant”, “equal”) away from the first signal pin (27; annotated FIRST SIGNAL PIN) and the second signal pin (29; annotated SECOND SIGNAL PIN).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board comprising signal and ground vias as disclosed by Gingrich, wherein each ground pin of the first plurality of ground pins is positioned at a distance away from the first signal via; wherein each ground pin of the second plurality of ground pins is positioned at the distance away from the second signal pin, and the common ground pin is positioned at the distance away from the first signal pin and the second signal pin as taught by Loffink, in order to maintain signal integrity, provide higher isolation, improve isolation, improve speed, affect magnitude of crosstalk, reduce aggressors, leverage differential cancellation, have zero net aggressor, provide differential cancellation, provide a net effect of zero, and improve signal integrity (Loffink, Column 1, lines 14-24, Column 3, lines 15-26, Column 4, lines 27-65, Column 5, lines 1-51, Column 6, lines 13-22, Column 8, lines 3-17, Column 9, line 59-Column 10, line 3, Column 10, lines 40-46), such that the combination of Gingrich in view of Loffink teaches wherein each ground via of the first plurality of ground vias is positioned at a distance away from the first signal via; and a second plurality of ground vias extending through the layer and at least partially circumferentially surrounding a second signal via of the second pair of signal vias, wherein each ground via of the second plurality of ground vias is positioned at the distance away from the second signal via, and the first plurality of ground vias and the second plurality of ground vias share a common ground via positioned at the distance away from the first signal via and the second signal via. Note that the combination would also provide advantageous effects of controlling capacitance and controlling impedance. Please note that in the instant application, [0014,0067,0069,0071], Applicant has not disclosed any criticality for the claimed limitations.
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Annotated Fig 4 from Gingrich (US 2024/0145994 A1)
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Annotated Fig 9 from Loffink (US 10,522,949 B1)
Regarding Claim 2, Gingrich further discloses the apparatus (Fig 1-4) of claim 1, wherein the first pair of signal vias (pair of 60 in left-side box in Fig 4), the second pair of signal vias (other adjacent pair of 60 in right-side box in Fig 4), and the common ground via (70 or 72a or 72b or 72c) are offset (see in Fig 4 how 60,60 and 70 or 72 are not aligned in an up-down direction) from one another along a first axis (an imaginary line in up-down direction of Fig 4) and aligned (see Fig 4 showing 60, 60 and 70 and 72a are aligned along an imaginary line going left-right; [0031]) with one another along a second axis (an imaginary line in left-right direction of Fig 4) that is perpendicular to the first axis.
Regarding Claim 3, Gingrich further discloses the apparatus (Fig 1-4) of claim 2, further comprising an additional ground via (72b on above row is shown aligned with 72a) extending through the layer, wherein the additional ground via (72b on above row is shown aligned with 72a) is aligned with the common ground via (72a) along the first axis (an imaginary line in up-down direction of Fig 4) and offset from the common ground via along the second axis (an imaginary line in left-right direction of Fig 4).
Regarding Claim 4, Gingrich further discloses the apparatus (Fig 1-4) of claim 2, wherein the first plurality of ground vias (a plurality of 70,72a,72b,72c surrounding 60 on left side of Fig 4) comprises a first ground via (72a) and a second ground via (72b), wherein the first ground via and the second ground via are aligned (see annotated figure showing FIRST AND SECOND GROUND VIAS ALIGNED) with one another along the first axis (an imaginary line in up-down direction of Fig 4) and offset from one another along the second axis (an imaginary line in left-right direction of Fig 4).
Regarding Claim 5, Gingrich further discloses the apparatus (Fig 1-4) of claim 2, wherein the first plurality of ground vias comprises a first ground via (72b about FIRST PAIR OF SIGNAL VIAS), the second plurality of ground vias comprises a second ground via (72b about SECOND PAIR OF SIGNAL VIAS), and the first ground via (72b) and the second ground via (72b) are offset from one another along the first axis (an imaginary line in up-down direction of Fig 4) and aligned with one another along the second axis (an imaginary line in left-right direction of Fig 4).
Regarding Claim 6, Gingrich further discloses the apparatus (Fig 1-4) of claim 2, further comprising a third plurality of ground vias (72b,72b,72b partially surrounding a pair of 60 in Fig 1 showing the patten of vias repeats along 16; see Fig 4 for analogous pattern) extending through the layer and at least partially surrounding a third signal via (60 of FIRST PAIR OF SIGNAL VIAS) of the first pair of signal vias, wherein the first plurality of ground vias (a plurality of 70,72a,72b,72c partially surrounding FIRST PAIR OF SIGNAL VIAS) comprises a first ground via (72b), the third plurality of ground vias (72b,72b) comprises a second ground via, and the first ground via and the second ground via are offset (Fig 4 showing 72b and 72b around FIRST PAIR OF SIGNAL VIAS is offset from one another along an imaginary axis going up-down in Fig 4 but aligned along an imaginary line going left-right) from one another along the first axis (an imaginary axis going up-down in Fig 4) and aligned with one another along the second axis (an imaginary line in left-right direction of Fig 4).
Regarding Claim 7, Gingrich further discloses the apparatus (Fig 1-4) of claim 6, further comprising a trace (62) coupled to the first signal via (60) or the third signal via (60) of the first pair of signal vias (FIRST PAIR OF SIGNAL VIAS), wherein the trace (62) is routed along the layer of the printed circuit board in a direction away from (see Fig 4 showing 62 first bends downward away from ground vias above 60) the first ground via or away from the second ground via.
Regarding Claim 11, Gingrich discloses a method (Fig 1-4; [0018,0019] “mating” “mounting”) comprising: forming adjacent pairs of signal vias (60) through a layer (*layer as seen in Fig 4 has thickness) of a printed circuit board (16); forming a first plurality of ground vias (a plurality of 70,72a,72b,72c surrounding 60 on left side of Fig 4) through the layer of the printed circuit board (16) to at least partially circumferentially surround (see Fig 4 showing 70,72 vias at least partially surround pair of 60 in left-side box in Fig 4) a first signal via (60) of a first pair of signal vias (pair of 60 in left-side box in Fig 4; annotated FIRST PAIR OF SIGNAL VIAS) of the adjacent pairs of signal vias (60), wherein each ground via (70 or 72) of the first plurality of ground vias is positioned at a distance (see Fig 1-4 showing a distance between vias) away from the first signal via (60); and forming a second plurality of ground vias (a plurality of 70,72a,72b,72c partially surrounding 60 on right side of Fig 4) through the layer of the printed circuit board to at least partially circumferentially surround (see Fig 4 showing 70,72 vias at least partially surround pair of 60 in right-side box in Fig 4) a second signal via (60) of a second pair (other adjacent pair of 60 in right-side box in Fig 4; annotated SECOND PAIR OF SIGNAL VIAS) of signal vias of the adjacent pairs of signal vias, wherein the first plurality of ground vias (a plurality of 70,72a,72b,72c) and the second plurality of ground vias (a plurality of 70,72a,72b,72c) comprise a common ground via (as the claim language allows overlapping of ground vias within the first plurality of ground vias and second plurality of ground vias, a single 70 or 72a or 72b or 72c among the plurality of ground vias can be construed as a shared or common ground via shared by both pluralities).
Gingrich is in the field of pins interfacing with vias in the printed circuit board ([0049] “the pattern or positioning of the signal contact vias 70 and the ground contact receiving vias 90 matches the pattern of the signal mounting pins 26 and the ground mounting pins 28 of the daughtercard circuit board 18”), however Gingrich does not explicitly disclose wherein each ground via of the second plurality of ground vias is positioned at the distance away from the second signal via, and wherein each ground via of the second plurality of ground vias is positioned at the distance away from the second signal via, and the first plurality of ground vias and the second plurality of ground vias share a common ground via positioned at the distance away from the first signal via and the second signal via.
Loffink (US 10,522,949 B1), in the field of pin layouts and vias (Column 1, lines 5-10) teaches of a method (Fig 10) and an apparatus (Fig 9) comprising: a layer of a printed circuit board (Column 1, lines 5-10); a first pair of signal pins (pair of 25 at lower left most side of Fig 9) extending through the layer (pins would have some three-dimensional depth through the Fig 9 and into the view of Fig 9) and configured to propagate respective signals (Column 10, lines 1-3,65-68; “differential signal pair 25”, “signal pins 27,29”); a second pair of signal pins (pair of 25 at upper left most side of Fig 9) extending through the layer and configured to propagate respective signals (Column 10, lines 1-3,65-68); a first plurality of ground pins (17; annotated FIRST PLURALITY OF GROUND PINS; Column 5, lines 1-10 “ground pin”) extending through the layer and at least partially circumferentially surrounding (see Fig 9 showing; left most row of 17 partially circumferentially surrounding leftmost column of 25) a first signal pin (27; annotated FIRST SIGNAL PIN) of the first pair of signal vias (25), wherein each ground pin (17) of the first plurality of ground vias (17; annotated FIRST PLURALITY OF GROUND PINS) is positioned at a distance (Column 10, lines 40-46 “for each pin that has a plurality of immediate neighbor pins, that pin is equidistant or substantially equidistant from each of its immediate neighbor pins. Also preferably, a distance between any two immediate neighbor pins is equal to a distance between any other two immediate neighbor pins”) away from the first signal pin (27); and a second plurality of ground pins (17; annotated SECOND PLURALITY OF GROUND PINS; Column 5, lines 1-10 “ground pin”) extending through the layer and at least partially circumferentially surrounding (see Fig 9 showing; left most row of 17 partially circumferentially surrounding leftmost column of 25) a second signal pin (29; annotated SECOND SIGNAL PIN) of the second pair of signal pins, wherein each ground pin (17) of the second plurality of ground pins is positioned at the distance (Column 10, lines 40-46 “equidistant or substantially equidistant”, “equal”) away from the second signal pin (29; annotated SECOND SIGNAL PIN), and the first plurality of ground pins (17) and the second plurality of ground pins (17) share a common ground pin (17; annotated COMMON GROUND PIN) positioned at the distance (Column 10, lines 40-46 “equidistant or substantially equidistant”, “equal”) away from the first signal pin (27; annotated FIRST SIGNAL PIN) and the second signal pin (29; annotated SECOND SIGNAL PIN).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method comprising signal and ground vias as disclosed by Gingrich, wherein each ground pin of the first plurality of ground pins is positioned at a distance away from the first signal via; wherein each ground pin of the second plurality of ground pins is positioned at the distance away from the second signal pin, and the common ground pin is positioned at the distance away from the first signal pin and the second signal pin as taught by Loffink, in order to maintain signal integrity, provide higher isolation, improve isolation, improve speed, affect magnitude of crosstalk, reduce aggressors, leverage differential cancellation, have zero net aggressor, provide differential cancellation, provide a net effect of zero, and improve signal integrity (Loffink, Column 1, lines 14-24, Column 3, lines 15-26, Column 4, lines 27-65, Column 5, lines 1-51, Column 6, lines 13-22, Column 8, lines 3-17, Column 9, line 59-Column 10, line 3, Column 10, lines 40-46), such that the combination of Gingrich in view of Loffink teaches wherein each ground via of the first plurality of ground vias is positioned at a distance away from the first signal via; and a second plurality of ground vias extending through the layer and at least partially circumferentially surrounding a second signal via of the second pair of signal vias, wherein each ground via of the second plurality of ground vias is positioned at the distance away from the second signal via, and the first plurality of ground vias and the second plurality of ground vias share a common ground via positioned at the distance away from the first signal via and the second signal via. Note that the combination would also provide advantageous effects of controlling capacitance and controlling impedance. Please note that in the instant application, [0014,0067,0069,0071], Applicant has not disclosed any criticality for the claimed limitations.
Further as no specific steps are provided, the Office reads this in the broadest sense to include any manufacturing steps.
Regarding Claim 14, Gingrich further discloses the method (Fig 1-4; [0018,0019] “mating” “mounting”) of claim 11, further comprising coupling a trace (62) to the first signal via (60) or to the second signal via (60) and routing the trace along the layer (see Fig 4).
Further as no specific steps are provided, the Office reads this in the broadest sense to include any manufacturing steps.
Regarding Claim 16, Gingrich discloses an apparatus (Fig 1-4) comprising: a first pair of signal vias (pair of 60 in left-side box in Fig 4; annotated FIRST PAIR OF SIGNAL VIAS) of a printed circuit board, wherein the first pair of signal vias are configured to propagate respective signals ([0031]); a second pair of signal vias (other adjacent pair of 60 in right-side box in Fig 4; annotated SECOND PAIR OF SIGNAL VIAS) of the printed circuit board, wherein the second pair of signal vias are configured to propagate respective signals ([0031]), and the signal vias (60) of the first pair of signal vias and the second pair of signal vias are offset (60 are spaced apart in the left-right direction) from one another along a first axis (an imaginary line in up-down direction of Fig 4) and aligned (see Fig 4 showing 60 aligned in the left-right direction) with one another along a second axis (an imaginary line in left-right direction of Fig 4) that is perpendicular to the first axis; and a single ground via (70,72) positioned between and colinear ([0031] “72a are positioned in line with an axis of a row of respective signal contact receiving vias 60 and ground contact receiving vias 70”) to the first pair of signal vias (60) and the second pair of signal vias (60) along the first axis.
Gingrich does not explicitly disclose a single ground via positioned between and colinear to the first pair of signal vias and the second pair of signal vias along the first axis without another ground via being positioned between the single ground via and the first pair of signal vias and between the single ground via and the second pair of signal vias along the axis.
Loffink (US 10,522,949 B1), in the field of pin layouts and vias (Column 1, lines 5-10) teaches of an apparatus (Fig 9) comprising: a first pair of signal pins (pair of 25 at lower left most side of Fig 9) of a printed circuit board (Column 1, lines 5-10), wherein the first pair of signal pins (25) are configured to propagate respective signals (Column 10, lines 1-3,65-68; “differential signal pair 25”, “signal pins 27,29”); a second pair of signal pins (pair of 25 at upper left most side of Fig 9) of the printed circuit board, wherein the second pair of signal pins are configured to propagate respective signals (Column 10, lines 1-3,65-68), and the signal pins of the first pair of signal pins (25) and the second pair of signal pins (25) are offset from one another along a first axis (an axis going left-right in Fig 9) and aligned with one another along a second axis (axis going up-down in Fig 9 along the center of 27,29) that is perpendicular to the first axis; and a single ground pin (17; annotated COMMON GROUND PIN) positioned between and colinear (see Fig 9; Column 10, lines 33-46) to the first pair of signal pins (25) and the second pair of signal pins (25) along the first axis without another ground pin being positioned between the single ground pin (17; annotated COMMON GROUND PIN) and the first pair of signal pins (25) and between the single ground pin (17; annotated COMMON GROUND PIN) and the second pair of signal pins (15) along the axis.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus comprising signal and ground vias as disclosed by Gingrich, wherein the single ground pin positioned between and colinear to the first pair of signal pins and the second pair of signal pins along the first axis without another ground pin being positioned between the single ground pin and the first pair of signal pins and between the single ground pin and the second pair of signal pins along the axis as taught by Loffink, in order to maintain signal integrity, provide higher isolation, improve isolation, improve speed, affect magnitude of crosstalk, reduce aggressors, leverage differential cancellation, have zero net aggressor, provide differential cancellation, provide a net effect of zero, and improve signal integrity (Loffink, Column 1, lines 14-24, Column 3, lines 15-26, Column 4, lines 27-65, Column 5, lines 1-51, Column 6, lines 13-22, Column 8, lines 3-17, Column 9, line 59-Column 10, line 3, Column 10, lines 40-46), such that the combination of Gingrich in view of Loffink teaches a single ground via positioned between and colinear to the first pair of signal vias and the second pair of signal vias along the first axis without another ground via being positioned between the single ground via and the first pair of signal vias and between the single ground via and the second pair of signal vias along the axis. Note that the combination would also provide advantageous effects of controlling capacitance and controlling impedance. Please note that in the instant application, [0014,0067,0069,0071], Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 17, Gingrich further discloses the apparatus (Fig 1-4) of claim 16, wherein the single ground via (72a positioned in Fig 4 between FIRST PAIR OF SIGNAL VIAS and SECOND PAIR OF SIGNAL VIAS) is positioned equidistant to a first signal via (60) of the first pair of signal vias and a second signal via (60) of the second pair of signal vias.
Please note that in the instant application, [0014,0067,0069,0071], applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 18, Gingrich in view of Loffink teaches the limitations of the preceding claim and Gingrich further discloses the apparatus (Fig 1-4) of claim 17, further comprising: a first plurality of ground vias (a plurality of 70,72a,72b,72c at least partially surrounding 60 on left side of Fig 4) circumferentially surrounding the first signal via of the first pair of signal vias; and a second plurality of ground vias (a plurality of 70,72a,72b,72c at least partially surrounding 60 on right side of Fig 4) circumferentially surrounding the second signal via of the second pair of signal vias, wherein the single ground via is of both the first plurality of ground vias and the second plurality of ground vias (as the claim language allows overlapping of ground vias within the first plurality of ground vias and second plurality of ground vias, a single 70 or 72a or 72b or 72c among the plurality of ground vias can be construed as a shared or common ground via shared by both pluralities).
Gingrich does not explicitly disclose wherein each ground via of the first plurality of ground vias is positioned at the same distance away from the first signal via.
Loffink (US 10,522,949 B1), also in the field of pin layouts and vias (Column 1, lines 5-10) teaches of an apparatus (Fig 9) comprising: a layer of a printed circuit board (Column 1, lines 5-10); a first pair of signal pins (pair of 25 at lower left most side of Fig 9) extending through the layer (pins would have some three-dimensional depth through the Fig 9 and into the view of Fig 9) and configured to propagate respective signals (Column 10, lines 1-3,65-68; “differential signal pair 25”, “signal pins 27,29”); a second pair of signal pins (pair of 25 at upper left most side of Fig 9) extending through the layer and configured to propagate respective signals (Column 10, lines 1-3,65-68); a first plurality of ground pins (17; annotated FIRST PLURALITY OF GROUND PINS; Column 5, lines 1-10 “ground pin”) extending through the layer and at least partially circumferentially surrounding (see Fig 9 showing; left most row of 17 partially circumferentially surrounding leftmost column of 25) a first signal pin (27; annotated FIRST SIGNAL PIN) of the first pair of signal vias (25), wherein each ground pin (17) of the first plurality of ground vias (17; annotated FIRST PLURALITY OF GROUND PINS) is positioned at a distance (Column 10, lines 40-46 “for each pin that has a plurality of immediate neighbor pins, that pin is equidistant or substantially equidistant from each of its immediate neighbor pins. Also preferably, a distance between any two immediate neighbor pins is equal to a distance between any other two immediate neighbor pins”) away from the first signal pin (27); and a second plurality of ground pins (17; annotated SECOND PLURALITY OF GROUND PINS; Column 5, lines 1-10 “ground pin”) extending through the layer and at least partially circumferentially surrounding (see Fig 9 showing; left most row of 17 partially circumferentially surrounding leftmost column of 25) a second signal pin (29; annotated SECOND SIGNAL PIN) of the second pair of signal pins, wherein each ground pin (17) of the second plurality of ground pins is positioned at the distance (Column 10, lines 40-46 “equidistant or substantially equidistant”, “equal”) away from the second signal pin (29; annotated SECOND SIGNAL PIN), and the first plurality of ground pins (17) and the second plurality of ground pins (17) share a common ground pin (17; annotated COMMON GROUND PIN) positioned at the distance (Column 10, lines 40-46 “equidistant or substantially equidistant”, “equal”) away from the first signal pin (27; annotated FIRST SIGNAL PIN) and the second signal pin (29; annotated SECOND SIGNAL PIN).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus comprising signal and ground vias as taught by Gingrich in view of Loffink, wherein each ground via of the first plurality of ground vias is positioned at the same distance away from the first signal via as taught by Loffink, in order to maintain signal integrity, provide higher isolation, improve isolation, improve speed, affect magnitude of crosstalk, reduce aggressors, leverage differential cancellation, have zero net aggressor, provide differential cancellation, provide a net effect of zero, and improve signal integrity (Loffink, Column 1, lines 14-24, Column 3, lines 15-26, Column 4, lines 27-65, Column 5, lines 1-51, Column 6, lines 13-22, Column 8, lines 3-17, Column 9, line 59-Column 10, line 3, Column 10, lines 40-46). Note that the combination would also provide advantageous effects of controlling capacitance and controlling impedance. Please note that in the instant application, [0014,0067,0069,0071], Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 19, Gingrich in view of Loffink teaches the limitations of the preceding claim and Loffink further teaches the apparatus (Fig 9) of claim 16, wherein a first signal via (27) of the first pair of signal vias is positioned equidistant (Column 10, lines 33-46) to the single ground via (17; annotated COMMON GROUND PIN) and a second signal via (29) of the first pair of signal vias. Please note that in the instant application, [0014,0067,0069,0071], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Gingrich (US 2024/0145994 A1) in view of Loffink (US 10,522,949 B1) as applied to claims 1 and 11 above, and further in view of Kawai (US 2013/0215588 A1).
Regarding Claim 9, Gingrich in view of Loffink teaches the limitations of the preceding claim and Gingrich further discloses the apparatus (Fig 4) of claim 1, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the apparatus comprises a third pair of signal vias (see Fig 4 showing a plurality of pairs of 60) and configured to propagate respective signals.
Gingrich does not explicitly disclose the apparatus of claim 1, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the printed circuit board comprises a second outer layer extending along a second side, opposite the first side, of the printed circuit board, the apparatus comprises a third pair of signal vias extending through the second outer layer and configured to propagate respective signals, and each of the first pair of signal vias, the second pair of signal vias, and the third pair of signal vias extends through a common inner layer between the first outer layer and the second outer layer.
Kawai (US 2013/0215588 A1) teaches of an apparatus (Fig 2-5), wherein a layer (2J) is a first outer layer extending along a first side of a printed circuit board, the printed circuit board comprises a second outer layer (3A) extending along a second side, opposite the first side, of the printed circuit board, the apparatus comprises a third pair of signal vias (20 in Fig 5) extending through the second outer layer and configured to propagate respective signals ([0047]), and each of the first pair of signal vias (20A), the second pair of signal vias (20B), and the third pair of signal vias (20C) extends through a common inner layer (91A) between the first outer layer and the second outer layer.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as taught by Gingrich in view of Loffink, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the printed circuit board comprises a second outer layer extending along a second side, opposite the first side, of the printed circuit board, the apparatus comprises a third pair of signal vias extending through the second outer layer and configured to propagate respective signals, and each of the first pair of signal vias, the second pair of signal vias, and the third pair of signal vias extends through a common inner layer between the first outer layer and the second outer layer as taught by Kawai, in order to increase density of electrical circuitry and meet demands, (Kawai, [0011]) and furthermore increase functionality of the circuit board by providing additional circuitry and a multilayered board.
Regarding Claim 15, Gingrich in view of Loffink teaches the limitations of the preceding claim.
Gingrich further discloses the method (Fig 4) of claim 11, wherein the layer is a first outer layer extending along a first side of the printed circuit board, and the method further comprises forming an additional pair of signal vias (see Fig 4 showing a plurality of pairs of 60).
Gingrich does not explicitly disclose the method of claim 11, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the printed circuit board comprises a second outer layer extending along a second side, opposite the first side, of the printed circuit board, and the method further comprises forming an additional pair of signal vias extending through the second outer layer such that the adjacent pair of signal vias and the additional pair of signal vias each extend through a common inner layer between the first outer layer and the second outer layer.
Kawai (US 2013/0215588 A1) teaches of an apparatus (Fig 2-5), wherein a layer (2J) is a first outer layer extending along a first side of a printed circuit board, the printed circuit board comprises a second outer layer (3A) extending along a second side, opposite the first side, of the printed circuit board, the apparatus comprises a third pair of signal vias (20 in Fig 5) extending through the second outer layer and configured to propagate respective signals ([0047]), and each of the first pair of signal vias (20A), the second pair of signal vias (20B), and the third pair of signal vias (20C) extends through a common inner layer (91A) between the first outer layer and the second outer layer.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method as taught by Gingrich in view of Loffink, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the printed circuit board comprises a second outer layer extending along a second side, opposite the first side, of the printed circuit board, and the method further comprises forming an additional pair of signal vias extending through the second outer layer such that the adjacent pair of signal vias and the additional pair of signal vias each extend through a common inner layer between the first outer layer and the second outer layer as taught by Kawai, in order to increase density of electrical circuitry and meet demands, (Kawai, [0011]) and furthermore increase functionality of the circuit board by providing additional circuitry and a multilayered board.
Further as no specific steps are provided, the Office reads this in the broadest sense to include any manufacturing steps.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gingrich (US 2024/0145994 A1) in view of Loffink (US 10,522,949 B1) as applied to claim 1 above, and further in view of Park (US 10,194,524 B1).
Regarding Claim 10, Gingrich in view of Loffink teaches the limitations of the preceding claim.
Gingrich further discloses the apparatus (Fig 4) of claim 1, wherein the layer is a layer (as seen in Fig 4) that comprises a ground portion (portion about 70,72), and the first plurality of ground vias (70,72) and the second plurality of ground vias (70,72) extend through (components and structure as seen in Fig 4 would have a thickness) the ground portion.
Gingrich does not disclose wherein the layer is a power layer that comprises a power section configured to receive power and a ground portion separated from the power section via a cutout, and the first plurality of ground vias, the second plurality of ground vias, the first pair of signal vias, and the second pair of signal vias are formed through the ground portion.
Park (US 10,194,524 B1) teaches of an apparatus (Fig 1-3), wherein a layer is a power layer (12p) that comprises a power section (portion or section of 12p) configured to receive power and a ground portion (12d) separated (see Fig 1A) from the power section via a cutout (17), and a first plurality of ground vias (18), a second plurality of ground vias (18), a first pair of signal vias (14), and a second pair of signal vias (14) are formed through the ground portion (at 17).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as taught by Gingrich in view of Loffink, wherein the layer is a power layer that comprises a power section configured to receive power and a ground portion separated from the power section via a cutout, and the first plurality of ground vias, the second plurality of ground vias, the first pair of signal vias, and the second pair of signal vias are formed through the ground portion as taught by Park, in order to transmit electrical power, reduce errors, increase circuit density, increase signal speeds, and improve quality of signals (Park, Column 1, lines 11-24).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
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