DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the third pair of signal vias extends in overlap with the first pair of signal vias and/or with the second pair of signal vias at an inner layer between the first outer layer and the second outer layer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 8, 11, 14 and 16 – 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gingrich (US 2024/0145994 A1).
Regarding Claim 1, Gingrich (US 2024/0145994 A1) discloses an apparatus (Fig 1-4) comprising: a layer (layer as seen in Fig 4 would have some thickness) of a printed circuit board (16); a first pair of signal vias (pair of 60 in left-side box in Fig 4; annotated FIRST PAIR OF SIGNAL VIAS) extending through the layer and configured to propagate respective signals ([0031]); a second pair of signal vias (other adjacent pair of 60 in right-side box in Fig 4; annotated SECOND PAIR OF SIGNAL VIAS) extending through the layer and configured to propagate respective signals ([0031]); a first plurality of ground vias (a plurality of 70,72a,72b,72c at least partially surrounding 60 on left side of Fig 4) extending through the layer and at least partially circumferentially surrounding (see Fig 4 showing 70,72 vias at least partially surround pair of 60 in left-side box in Fig 4) a first signal via (60) of the first pair of signal vias; and a second plurality of ground vias (a plurality of 70,72a,72b,72c at least partially surrounding 60 on right side of Fig 4) extending through the layer and at least partially circumferentially surrounding (see Fig 4 showing 70,72 vias at least partially surround pair of 60 in right-side box in Fig 4) a second signal via (60) of the second pair of signal vias, wherein the first plurality of ground vias (a plurality of 70,72a,72b,72c) and the second plurality of ground vias (a plurality of 70,72a,72b,72c) share a common ground via (as the claim language allows overlapping of ground vias within the first plurality of ground vias and second plurality of ground vias, a single 70 or 72a or 72b or 72c among the plurality of ground vias can be construed as a shared or common ground via shared by both pluralities).
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Annotated Fig 4 from Gingrich (US 2024/0145994 A1)
Regarding Claim 2, Gingrich further discloses the apparatus (Fig 1-4) of claim 1, wherein the first pair of signal vias (pair of 60 in left-side box in Fig 4), the second pair of signal vias (other adjacent pair of 60 in right-side box in Fig 4), and the common ground via (70 or 72a or 72b or 72c) are offset (see in Fig 4 how 60,60 and 70 or 72 are not aligned in an up-down direction) from one another along a first axis (an imaginary line in up-down direction of Fig 4) and aligned (see Fig 4 showing 60, 60 and 70 and 72a are aligned along an imaginary line going left-right; [0031]) with one another along a second axis (an imaginary line in left-right direction of Fig 4) that is perpendicular to the first axis.
Regarding Claim 3, Gingrich further discloses the apparatus (Fig 1-4) of claim 2, further comprising an additional ground via (72b on above row is shown aligned with 72a) extending through the layer, wherein the additional ground via (72b on above row is shown aligned with 72a) is aligned with the common ground via (72a) along the first axis (an imaginary line in up-down direction of Fig 4) and offset from the common ground via along the second axis (an imaginary line in left-right direction of Fig 4).
Regarding Claim 4, Gingrich further discloses the apparatus (Fig 1-4) of claim 2, wherein the first plurality of ground vias (a plurality of 70,72a,72b,72c surrounding 60 on left side of Fig 4) comprises a first ground via (72a) and a second ground via (72b), wherein the first ground via and the second ground via are aligned (see annotated figure showing FIRST AND SECOND GROUND VIAS ALIGNED) with one another along the first axis (an imaginary line in up-down direction of Fig 4) and offset from one another along the second axis (an imaginary line in left-right direction of Fig 4).
Regarding Claim 5, Gingrich further discloses the apparatus (Fig 1-4) of claim 2, wherein the first plurality of ground vias comprises a first ground via (72b about FIRST PAIR OF SIGNAL VIAS), the second plurality of ground vias comprises a second ground via (72b about SECOND PAIR OF SIGNAL VIAS), and the first ground via (72b) and the second ground via (72b) are offset from one another along the first axis (an imaginary line in up-down direction of Fig 4) and aligned with one another along the second axis (an imaginary line in left-right direction of Fig 4).
Regarding Claim 6, Gingrich further discloses the apparatus (Fig 1-4) of claim 2, further comprising a third plurality of ground vias (72b,72b,72b partially surrounding a pair of 60 in Fig 1 showing the patten of vias repeats along 16; see Fig 4 for analogous pattern) extending through the layer and at least partially surrounding a third signal via (60 of FIRST PAIR OF SIGNAL VIAS) of the first pair of signal vias, wherein the first plurality of ground vias (a plurality of 70,72a,72b,72c partially surrounding FIRST PAIR OF SIGNAL VIAS) comprises a first ground via (72b), the third plurality of ground vias (72b,72b) comprises a second ground via, and the first ground via and the second ground via are offset (Fig 4 showing 72b and 72b around FIRST PAIR OF SIGNAL VIAS is offset from one another along an imaginary axis going up-down in Fig 4 but aligned along an imaginary line going left-right) from one another along the first axis (an imaginary axis going up-down in Fig 4) and aligned with one another along the second axis (an imaginary line in left-right direction of Fig 4).
Regarding Claim 7, Gingrich further discloses the apparatus (Fig 1-4) of claim 6, further comprising a trace (62) coupled to the first signal via (60) or the third signal via (60) of the first pair of signal vias (FIRST PAIR OF SIGNAL VIAS), wherein the trace (62) is routed along the layer of the printed circuit board in a direction away from (see Fig 4 showing 62 first bends downward away from ground vias above 60) the first ground via or away from the second ground via.
Regarding Claim 8, Gingrich further discloses the apparatus (Fig 1-4) of claim 7, further comprising a plurality of ground microvias (70 or 72 on a row below FIRST PAIR OF SIGNAL VIAS; note that no official definition of microvia is provided; the Office will assume microvia is defined as any small via; [0036]) formed through the layer and surrounding (at least partially) the trace (62).
Regarding Claim 11, Gingrich discloses a method (Fig 1-4; [0018,0019] “mating” “mounting”) comprising: forming adjacent pairs of signal vias (60) through a layer (*layer as seen in Fig 4 has thickness) of a printed circuit board (16); forming a first plurality of ground vias (a plurality of 70,72a,72b,72c surrounding 60 on left side of Fig 4) through the layer of the printed circuit board (16) to at least partially circumferentially surround (see Fig 4 showing 70,72 vias at least partially surround pair of 60 in left-side box in Fig 4) a first signal via (60) of a first pair of signal vias (pair of 60 in left-side box in Fig 4; annotated FIRST PAIR OF SIGNAL VIAS) of the adjacent pairs of signal vias (60); and forming a second plurality of ground vias (a plurality of 70,72a,72b,72c partially surrounding 60 on right side of Fig 4) through the layer of the printed circuit board to at least partially circumferentially surround (see Fig 4 showing 70,72 vias at least partially surround pair of 60 in right-side box in Fig 4) a second signal via (60) of a second pair (other adjacent pair of 60 in right-side box in Fig 4; annotated SECOND PAIR OF SIGNAL VIAS) of signal vias of the adjacent pairs of signal vias, wherein the first plurality of ground vias (a plurality of 70,72a,72b,72c) and the second plurality of ground vias (a plurality of 70,72a,72b,72c) comprise a common ground via (as the claim language allows overlapping of ground vias within the first plurality of ground vias and second plurality of ground vias, a single 70 or 72a or 72b or 72c among the plurality of ground vias can be construed as a shared or common ground via shared by both pluralities).
Further as no specific steps are provided, the Office reads this in the broadest sense to include any manufacturing steps.
Regarding Claim 14, Gingrich further discloses the method (Fig 1-4; [0018,0019] “mating” “mounting”) of claim 11, further comprising coupling a trace (62) to the first signal via (60) or to the second signal via (60) and routing the trace along the layer (see Fig 4).
Further as no specific steps are provided, the Office reads this in the broadest sense to include any manufacturing steps.
Regarding Claim 16, Gingrich discloses an apparatus (Fig 1-4) comprising: a first pair of signal vias (pair of 60 in left-side box in Fig 4; annotated FIRST PAIR OF SIGNAL VIAS) of a printed circuit board, wherein the first pair of signal vias are configured to propagate respective signals ([0031]); a second pair of signal vias (other adjacent pair of 60 in right-side box in Fig 4; annotated SECOND PAIR OF SIGNAL VIAS) of the printed circuit board, wherein the second pair of signal vias are configured to propagate respective signals ([0031]), and the signal vias (60) of the first pair of signal vias and the second pair of signal vias are offset (60 are spaced apart in the left-right direction) from one another along a first axis (an imaginary line in up-down direction of Fig 4) and aligned (see Fig 4 showing 60 aligned in the left-right direction) with one another along a second axis (an imaginary line in left-right direction of Fig 4) that is perpendicular to the first axis; and a single ground via (70,72) positioned between the first pair of signal vias and the second pair of signal vias along the first axis.
Regarding Claim 17, Gingrich further discloses the apparatus (Fig 1-4) of claim 16, wherein the single ground via (72a positioned in Fig 4 between FIRST PAIR OF SIGNAL VIAS and SECOND PAIR OF SIGNAL VIAS) is positioned equidistant to a first signal via (60) of the first pair of signal vias and a second signal via (60) of the second pair of signal vias.
Please note that in the instant application, [0014,0067,0069,0071], applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 18, Gingrich further discloses the apparatus (Fig 1-4) of claim 17, further comprising: a first plurality of ground vias (a plurality of 70,72a,72b,72c at least partially surrounding 60 on left side of Fig 4) circumferentially surrounding the first signal via of the first pair of signal vias; and a second plurality of ground vias (a plurality of 70,72a,72b,72c at least partially surrounding 60 on right side of Fig 4) circumferentially surrounding the second signal via of the second pair of signal vias, wherein the single ground via is of both the first plurality of ground vias and the second plurality of ground vias (as the claim language allows overlapping of ground vias within the first plurality of ground vias and second plurality of ground vias, a single 70 or 72a or 72b or 72c among the plurality of ground vias can be construed as a shared or common ground via shared by both pluralities).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Gingrich (US 2024/0145994 A1) as applied to claims 1 and 11 above, and further in view of Choi (US 2024/0431026 A1).
Regarding Claim 9, Gingrich discloses the limitations of the preceding claim.
Gingrich does not explicitly disclose the apparatus of claim 1, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the printed circuit board comprises a second outer layer extending along a second side, opposite the first side, of the printed circuit board, the apparatus comprises a third pair of signal vias extending through the second outer layer and configured to propagate respective signals, and the third pair of signal vias extends in overlap with the first pair of signal vias and/or with the second pair of signal vias at an inner layer between the first outer layer and the second outer layer.
Choi (US 2024/0431026 A1) teaches of an apparatus (Fig 2,7), wherein a layer is a first outer layer (201) extending along a first side (towards L1) of a printed circuit board (110), the printed circuit board comprises a second outer layer (202) extending along a second side (towards L16), opposite the first side, of the printed circuit board, the apparatus comprises a third pair of signal vias (212,213) extending through the second outer layer and configured to propagate respective signals ([0026]), and the third pair of signal vias (212,213) extends in overlap with a first pair of signal vias (210,211) and/or with the second pair of signal vias at an inner layer between the first outer layer and the second outer layer.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Gingrich, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the printed circuit board comprises a second outer layer extending along a second side, opposite the first side, of the printed circuit board, the apparatus comprises a third pair of signal vias extending through the second outer layer and configured to propagate respective signals, and the third pair of signal vias extends in overlap with the first pair of signal vias and/or with the second pair of signal vias at an inner layer between the first outer layer and the second outer layer as taught by Choi, in order to form a capacitive coupling, increase mutual capacitance, provide balance, and improve overall performance (Choi, [0006,0018,0029-0035]).
Regarding Claim 15, Gingrich discloses the limitations of the preceding claim.
Gingrich does not explicitly disclose the method of claim 11, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the printed circuit board comprises a second outer layer extending along a second side, opposite the first side, of the printed circuit board, and the method further comprises forming an additional pair of signal vias extending through the second outer layer in overlap with the adjacent pair of signal vias at an inner layer between the first outer layer and the second outer layer.
Choi (US 2024/0431026 A1) teaches of an apparatus (Fig 2,7), wherein a layer is a first outer layer (201) extending along a first side (towards L1) of a printed circuit board (110), the printed circuit board comprises a second outer layer (202) extending along a second side (towards L16), opposite the first side, of the printed circuit board, the apparatus comprises a third pair of signal vias (212,213) extending through the second outer layer and configured to propagate respective signals ([0026]), and the third pair of signal vias (212,213) extends in overlap with a first pair of signal vias (210,211) and/or with the second pair of signal vias at an inner layer between the first outer layer and the second outer layer.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method as disclosed by Gingrich, wherein the layer is a first outer layer extending along a first side of the printed circuit board, the printed circuit board comprises a second outer layer extending along a second side, opposite the first side, of the printed circuit board, and the method further comprises forming an additional pair of signal vias extending through the second outer layer in overlap with the adjacent pair of signal vias at an inner layer between the first outer layer and the second outer layer as taught by Choi, in order to form a capacitive coupling, increase mutual capacitance, provide balance, and improve overall performance (Choi, [0006,0018,0029-0035]).
Further as no specific steps are provided, the Office reads this in the broadest sense to include any manufacturing steps.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gingrich (US 2024/0145994 A1) as applied to claim 1 above, and further in view of Minich (US 2014/0209370 A1).
Regarding Claim 10, Gingrich discloses the limitations of the preceding claim.
Gingrich further discloses the apparatus (Fig 4) of claim 1, wherein the layer is a layer (as seen in Fig 4) that comprises a ground portion (portion about 70,72), and the first plurality of ground vias (70,72) and the second plurality of ground vias (70,72) extend through (components and structure as seen in Fig 4 would have a thickness) the ground portion.
Gingrich does not disclose wherein the layer is a power layer.
Minich (US 2014/0209370 A1) teaches of an apparatus (Fig 1-2), wherein a layer (102; [0017]) is a power layer that comprises a ground portion (portion or area or region about G,g; [0021]), and a first plurality of ground vias (112,134) and a second plurality of ground vias (112,134) extend through (see Fig 2) the ground portion.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Gingrich, wherein the layer is a power layer as taught by Minich, in order to transmit electrical power and electrically connect different components along the printed circuit board (Minich, [0017]).
Claim(s) 12, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gingrich (US 2024/0145994 A1) as applied to claims 11 and 16 above, and further in view of Miller (US 6,744,130 B1).
Regarding Claim 12, Gingrich discloses the limitations of the preceding claim.
Gingrich does not disclose the method of claim 11, wherein the layer comprises a power shape with a cutout, and the adjacent pairs of signal vias, the first plurality of ground vias, and the second plurality of ground vias are formed through the cutout.
Miller (US 6,744,130 B1) teaches of a substrate (Fig 1-5), wherein a layer (38,46) comprises a power shape with a cutout (see Fig 5 showing cutout or opening in 38,46 about 12a,12b), and adjacent pairs of signal vias (see Fig 1; 20,22), a first plurality of ground vias (16), and a second plurality of ground vias (16) are formed through the cutout (see Fig 5 showing cutout or opening in 38,46 about 12a,12b).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Gingrich, wherein the layer comprises a power shape with a cutout, and the adjacent pairs of signal vias, the first plurality of ground vias, and the second plurality of ground vias are formed through the cutout as taught by Miller, in order to assist in transmitting and receiving power, to power vias, provide isolation and support a broad range of circuit designs (Miller, Abstract, Column 2, lines 34-42, Column 6, lines 26-67, Column7, lines 4-18).
Further as no specific steps are provided, the Office reads this in the broadest sense to include any manufacturing steps.
Regarding Claim 13, Gingrich in view of Miller teaches the limitations of the preceding claim.
Miller further teaches the method (Fig 1-5) of claim 12, further comprising positioning a ground shape (a plurality or group of 16 in Fig 1 is shown having a shape and can be construed as a ground shape; 16 is for grounding; note that the claim has not structurally defined the claimed shape) within the cutout (see Fig 5 showing cutout or opening in 38,46 about 12a,12b), wherein the adjacent pairs of signal vias (20,22), the first plurality of ground vias (16), and the second plurality of ground vias (16) are formed through ground shape (a plurality or group of 16 in Fig 1).
Further as no specific steps are provided, the Office reads this in the broadest sense to include any manufacturing steps.
Regarding Claim 20, Gingrich discloses the limitations of the preceding claim.
Gingrich does not explicitly disclose the apparatus of claim 16, wherein the first pair of signal vias, the second pair of signal vias, and the single ground via extend through a cutout of a power shape of the printed circuit board to avoid contact with the power shape.
Miller (US 6,744,130 B1) teaches of a substrate (Fig 1-5), wherein a layer (38,46) comprises a power shape with a cutout (see Fig 5 showing cutout or opening in 38,46 about 12a,12b), and adjacent pairs of signal vias (see Fig 1; 20,22), a first plurality of ground vias (16), and a second plurality of ground vias (16) are formed through the cutout (see Fig 5 showing cutout or opening in 38,46 about 12a,12b).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Gingrich, wherein the first pair of signal vias, the second pair of signal vias, and the single ground via extend through a cutout of a power shape of the printed circuit board to avoid contact with the power shape as taught by Miller, in order to assist in transmitting and receiving power, to power vias, provide isolation and support a broad range of circuit designs (Miller, Abstract, Column 2, lines 34-42, Column 6, lines 26-67, Column7, lines 4-18).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Gingrich (US 2024/0145994 A1) as applied to claim 16 above, and further in view of Lee (US 2004/0150970 A1).
Regarding Claim 19, Gingrich discloses the limitations of the preceding claim.
Gingrich does not explicitly disclose the apparatus of claim 16, wherein a first signal via (60) of the first pair of signal vias is positioned equidistant to the single ground via and a second signal via of the first pair of signal vias.
Lee (US 2004/0150970 A1) teaches of an apparatus (Fig 3-5), wherein a first signal via (18) of the first pair of signal vias (18,18) is positioned equidistant ([0017,0026,0027]) to a single ground via (24) and a second signal via (18) of the first pair of signal vias (18,18).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Gingrich, wherein a first signal via (60) of the first pair of signal vias is positioned equidistant to the single ground via and a second signal via of the first pair of signal vias as taught by Lee, in order to affect capacitance and affect impedance (Lee, [0017,0026,0027]) and furthermore since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art in order to affect capacitance and affect impedance. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, [0014,0067,0069,0071], applicant has not disclosed any criticality for the claimed limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Azeroual (US 12,295,094 B1) teaches of an apparatus (Fig 2-4) comprising: a first pair of signal vias (404 in Fig 4) and configured to propagate respective signals; a second pair of signal vias (other 404) extending through the layer and configured to propagate respective signals; a first plurality of ground vias (a number of 402) extending through the layer and at least partially circumferentially surrounding (see Fig 4 showing 402 vias at least partially surround pair of 404) a first signal via of the first pair of signal vias; and a second plurality of ground vias (a number of 402) extending through the layer and at least partially circumferentially surrounding (see Fig 4) a second signal via (404) of the second pair of signal vias, wherein the first plurality of ground vias (402) and the second plurality of ground vias (402) share a common ground via (as the claim language allows overlapping of ground vias within the first plurality of ground vias and second plurality of ground vias, a single 402 can be construed as a common ground via).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896