Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on February 29, 2024, and August 27, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed February 10, 2026 has been entered. Claims 1-20 remain pending in the application. Claims 1-2, 4, 7, 13-16 & 18-20 have been amended. Applicant’s amendments to the Claims have overcome each and every objection and 35 U.S.C. § 112(b) rejections previously set forth in the Non-Final Office Action mailed November 12, 2025, hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant's arguments, please refer to pp. 9-11 of applicant’s remarks, filed February 10, 2026, that prior art references with respect to the rejection(s) of amended independent claim 1, under U.S.C. § 103, Ueno (US 2013/0215302 A1, hereinafter, Ueno), in view Hanzawa et al. (US 2018/0109744 A1, hereinafter, Hanzawa), and further in view of Berens (US 2015/0280561 A1, hereinafter, Berens), have been fully considered and are persuasive. However, upon further consideration, in the light of the amendment(s), a new ground(s) of rejection is made in view of Ueno, in view of Hanzawa, in view of Berens, and further in view of Omran et al. (US 2018/025479 A1, hereinafter, Omran), and applicant’s arguments are rendered moot. Therefore, the rejection(s) of amended independent claim 1, and dependent claims 2-15, which depend from and incorporate the limitations of amended independent claim 1, are respectively maintained. Updated rejections based on amended features follow.
Applicant's arguments, please refer to pp. 11-12 of applicant’s remarks, filed February 10, 2026, that prior art references with respect to the rejection(s) of amended dependent claim 2, under U.S.C. § 103, Ueno, in view Hanzawa, and further in view of Berens, have been fully considered and are persuasive. However, upon further consideration, in the light of the amendment(s), a new ground(s) of rejection is made in view of Ueno, in view of Hanzawa, in view of Berens, in view of Omran, and further in view of Ebihara et al. (US 2018/0091752 A1, hereinafter, Ebihara), and applicant’s arguments are rendered moot. Therefore, the rejection(s) of amended dependent claim 2, and dependent claims 2-6, which depend from and incorporate the limitations of amended dependent claim 2, are respectively maintained. Updated rejections based on amended features follow.
Applicant's arguments, please refer to p. 12 of applicant’s remarks, filed February 10, 2026, that prior art references with respect to the rejection(s) of amended dependent claim 5, under U.S.C. § 103, Ueno, in view Hanzawa, and further in view of Berens, fail to disclose, teach and/or suggest individually or in combination, each and every limitation of the claimed invention, to include: “and each of the…fifth, and sixth transistors are NMOS transistors”, and “the fifth and sixth transistors of claim 1 are within the amplifier and have a specific connectivity”.
The examiner respectfully disagrees in regard to the submission of what the applicant states as the prior cited references, fail to disclose, teach and/or suggest, “although the NMOS transistors can be used as switches within the comparator, the fifth and sixth transistors of claim 1 are within the amplifier and have a specific connectivity.” The examiner appreciates the explanation and additional evidence; however it is noted that the features upon which the applicant relies (i.e., p. 12 of applicant’s remarks) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Currently, the claims do not recite or define that the fifth and sixth transistors of claim 1 are within the amplifier. The applicant may believe that their terminology defines the claimed limitation(s) to a particular component and/or methodology, but when the claims are examined, they are given the broadest reasonable interpretation. In the immediate case of this application, the examiner has taken the interpretation that other components/methodologies and techniques with increased accuracy and precision can be applied to the “fifth and sixth transistors of claim 1 are within the amplifier and have a specific connectivity.”
Applicant's arguments, please refer to pp. 12-13 of applicant’s remarks, filed February 10, 2026, that prior art references with respect to the rejection(s) of amended dependent claim 13, under U.S.C. § 103, Ueno, in view Hanzawa, and further in view of Berens, fail to disclose, teach and/or suggest individually or in combination, each and every limitation of the claimed invention, to include: “the power switch include a PMOS in series with an NMOS and also an additional transistor coupled between that NMOS and a third voltage supply”.
The examiner respectfully disagrees in regard to the submission of what the applicant states as the prior cited references, fail to disclose, teach and/or suggest, “the power switch include a PMOS in series with an NMOS and also an additional transistor coupled between that NMOS and a third voltage supply” The examiner appreciates the explanation and additional evidence; however it is noted that the features upon which the applicant relies (i.e., pp. 12-13 of applicant’s remarks) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Currently, the claims do not recite or define that the power switch includes a PMOS in series with an NMOS and an additional transistor coupled between that NMOS in series with a PMOS and a third voltage. The applicant may believe that their terminology defines the claimed limitation(s) to a particular component and/or methodology, but when the claims are examined, they are given the broadest reasonable interpretation. In the immediate case of this application, the examiner has taken the interpretation that other components and/or methodologies and techniques with increased accuracy and precision can be applied to the “the power switch further include a PMOS in series with an NMOS and also an additional transistor coupled between than NMOS and a third voltage supply.”
Applicant's arguments, please refer to pp. 13-14 of applicant’s remarks, filed February 10, 2026, that prior art references with respect to the rejection(s) of amended dependent claim 14, under U.S.C. § 103, Ueno (US 2013/0215302 A1, hereinafter, Ueno), in view Hanzawa et al. (US 2018/0109744 A1, hereinafter, Hanzawa), and further in view of Berens (US 2015/0280561 A1, hereinafter, Berens), have been fully considered and are persuasive. However, upon further consideration, in the light of the amendment(s), a new ground(s) of rejection is made in view of Ueno, in view of Hanzawa, in view of Berens, in view of Omran, in view of Mednik (US 10778080 B1, hereinafter, Mednik), and further in view of Chaput et al. (US 2020/0014395 A1, hereinafter, Chaput), and applicant’s arguments are rendered moot. Therefore, the rejection(s) of amended dependent claim 14, and dependent claim 15, which depends from and incorporate the limitations of amended independent claim 1 and amended dependent claim 14, are respectively maintained. Updated rejections based on amended features follow.
Applicant's arguments, please refer to pp. 13-14 of applicant’s remarks, filed February 10, 2026, that prior art references with respect to the rejection(s) of amended dependent claim 15, under U.S.C. § 103, Ueno (US 2013/0215302 A1, hereinafter, Ueno), in view Hanzawa et al. (US 2018/0109744 A1, hereinafter, Hanzawa), and further in view of Berens (US 2015/0280561 A1, hereinafter, Berens), have been fully considered and are persuasive. However, upon further consideration, in the light of the amendment(s), a new ground(s) of rejection is made in view of Ueno, in view of Hanzawa, in view of Berens, in view of Omran, and further in view of and applicant’s arguments are rendered moot. Therefore, the rejection(s) of amended dependent claim 15, which depends from and incorporate the limitations of amended independent claim 1 and amended dependent claim 14, are respectively maintained. Updated rejections based on amended features follow.
Applicant's arguments, please refer to p. 14 of applicant’s remarks, filed February 10, 2026, that prior art references with respect to the rejection(s) of amended independent claim 16, under U.S.C. § 103, Ueno, in view Hanzawa, and further in view of Berens, have been fully considered and are persuasive. However, upon further consideration, in the light of the amendment(s) (similar to amended independent claim 1), a new ground(s) of rejection is made in view of Ueno, in view of Hanzawa, in view of Berens, and further in view of Omran, and applicant’s arguments are rendered moot. Therefore, the rejection(s) of amended independent claim 16, and dependent claims 17-20, which depend from and incorporate the limitations of amended independent claim 16, are respectively maintained. Updated rejections based on amended features follow.
Applicant's arguments, please refer to pp. 11-12 of applicant’s remarks, filed February 10, 2026, that prior art references with respect to the rejection(s) of amended dependent claim 18 (in a manner similar to dependent claim 2), under U.S.C. § 103, Ueno, in view Hanzawa, and further in view of Berens, have been fully considered and are persuasive. However, upon further consideration, in the light of the amendment(s), a new ground(s) of rejection is made in view of Ueno, in view of Hanzawa, in view of Berens, in view of Omran, and further in view of Ebihara, and applicant’s arguments are rendered moot. Therefore, the rejection(s) of amended dependent claim 18, is respectively maintained. Updated rejections based on amended features follow.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a single-ended cascode amplifier having an input and an output, wherein the second circuit node is coupled to a first terminal of a third capacitor, and a second terminal of the third capacitor, different from the first terminal, is coupled to the input of the single-ended cascode amplifier;” in ll. 18-22, where “the first and second terminal of the third capacitor” and “different from the first terminal” are considered new matter. The disclosure does not mention the specific second circuit node coupled to a first terminal of a third capacitor and a second terminal of the third capacitor, but mentions these terminals for transistors instead. Claims 2-15 are rejected by virtue of dependency on amended independent claim 1, which do not rectify the defect.
Claim 2 recites “wherein the second terminal of the third capacitor is coupled to the control electrode of the fifth transistor; ” in ll. 5-6, where “the second terminal of the third capacitor coupled to the control electrode of the fifth transistor” is considered new matter. The disclosure does not mention the specific second terminal of the third capacitor coupled the control electrode of the fifth transistor, but mentions “the single-ended cascode amplifier includes a fifth transistor having a control electrode configured as the input of the single-ended cascode amplifier, a first current electrode coupled to the second voltage supply terminal, and a second current electrode;” instead. Claims 3-6 are rejected by virtue of dependency on amended dependent claim 2, which do not rectify the defect.
Claim 16 recites “a single-ended cascode amplifier having an input and an output, wherein the second circuit node is coupled to a first terminal of a third capacitor, and a second terminal of the third capacitor, different from the first terminal, is coupled to the input of the single-ended cascode amplifier;” in ll. 18-22, where “the first and second terminal of the third capacitor” and “different from the first terminal” are considered new matter. The disclosure does not mention the specific second circuit node coupled to a first terminal of a third capacitor and a second terminal of the third capacitor, but mentions these terminals for transistors instead. Claims 17-20 are rejected by virtue of dependency on amended independent claim 16, which do not rectify the defect.
Claim 18 recites “wherein the second terminal of the third capacitor is coupled to the control electrode of the fifth transistor; ” in ll. 5-6, where “the second terminal of the third capacitor coupled to the control electrode of the fifth transistor” is considered new matter. The disclosure does not mention the specific second terminal of the third capacitor coupled the control electrode of the fifth transistor, but mentions “the single-ended cascode amplifier includes a fifth transistor having a control electrode configured as the input of the single-ended cascode amplifier, a first current electrode coupled to the second voltage supply terminal, and a second current electrode;” instead.
Claim 19 recites “A first DC-DC converter comprising: ” in line 1, where “the first DC-DC converter” is considered new matter. The disclosure does not mention the specific “first DC-DC converter”, but mentions generalized embodiments of DC-DC converter instead.
Claim 20 recites “A second DC-DC converter comprising: ” in line 1, where “the second DC-DC converter” is considered new matter. The disclosure does not mention the specific “second DC-DC converter” or any other numbered or plurality of DC-DC converters, but mentions generalized embodiments of a DC-DC converter instead.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-13, 16-17 & 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ueno (US 2013/0215302 A1, Pub. Date Aug. 22, 2013, hereinafter, Ueno), in view Hanzawa et al. (US 2018/0109744 A1, Pub. Date Apr. 19, 2018, hereinafter, Hanzawa), in view of Berens (US 2015/0280561 A1, Pub. Date Oct. 1, 2015, hereinafter, Berens), and further in view of Omran et al. (US 2018/0254779 A1, Pub. Date Sep. 6, 2018, hereinafter, Omran).
Regarding independent claim 1, Ueno, teaches:
A current comparator (Figs. 17 & 25; [0031]-[0032] & [0330]-[0331]: comparator 500), comprising:
a first capacitor having a first terminal coupled to a first input signal (Figs. 17 & 25; [0031], [0256]-[0257], [0263] & [0334]-[0335]: capacitor C511 has a second electrode connected to input terminal TRAMP for the ramp signal (first input signal));
a second capacitor having a first terminal coupled to a second input signal (Fig. 17; [0257], [0263] & [0334]-[0335]: capacitor C512 has a second electrode connected to input terminal TVSL for the analog signal VSL (second input signal));
a first transistor (Fig. 17: NT511) having a first current electrode coupled to a first voltage supply terminal (Fig. 17: GND) via a first current source (Fig. 17: NT513), a control electrode (Fig. 17: C511 gate) coupled to a second terminal of the first capacitor (Fig. 17: node ND513, second terminal of C511 (first capacitor)), and a second current electrode (Fig. 17: C512) coupled to a first circuit node (Figs. 17 & 25; [0250]-[0251], [0253]-[0260] & [0333]: gate of NT511 (first transistor) is coupled to the first electrode of C511 (second terminal of the first capacitor), its gate (control electrode) is connected to node ND513 (second terminal of C511 (first capacitor)), the gate of NT512 (second transistor) is coupled to the first electrode of C512 (second terminal of second capacitor), its drain (first current electrode) is connected to node ND511, the current source is transistor NT513, which is connected between the sources of NT511/NT512, and GND (first voltage supply terminal), and node ND511 is the first circuit node);
a second transistor having a first current electrode (Fig. 17: NT512) coupled to the first current electrode of the first transistor (Fig. 17: NT512 source (first current electrode) coupled to the source of NT511 (coupled to NT513 current source)), a control electrode coupled to a second terminal of the second capacitor (Fig. 17: second terminal of C512), and a second current electrode (Fig. 17: drain coupled to ND512) coupled to a second circuit node (Figs. 17 & 25; [0250]-[0251], [0253]-[0260] & [0333]: transistor NT512 (second transistor), its gate is connected to node ND514 (second terminal of C512), its drain is connected to the drain of NT511 (shared connection), its source is connected to the source of NT511, the second current electrode (drain) is connected to output node ND512 (second circuit node));
a third transistor (Fig. 17: PT511) having a first current electrode (Fig. 17: drain of PT511) coupled to the first circuit node (Fig. 17: connected to node ND511), a second current electrode (Fig. 17: source of PT511) coupled to a second voltage supply terminal (Fig. 17: VDD), and a control electrode coupled to the first circuit node (Figs. 17 & 25; [0250]-[0261] & [0333]-[0334]: transistor PT511 (third transistor), its source (first current electrode) is connected to VDD (second voltage supply terminal), its drain is connected to node ND511 (first circuit node), its gate (control electrode) is connected to its drain and to node ND512 (diode-connected));
a fourth transistor (Fig. 17: PT512) having a first current electrode (Fig. 17: drain of PT512) coupled to the second circuit node (Fig. 17: coupled to ND512), a control electrode coupled to the control electrode of the third transistor (Fig. 17: gate of PT512 (control electrode) is coupled to the connection point of the drain and gate of PT511 (control electrode of PT511)), and a second current electrode (Fig. 17: source of PT512) coupled to the second voltage supply terminal (Figs. 17 & 25; [0250]-[0260] & [0334]: transistor PT512 (fourth transistor), its source is connected to VDD (second voltage supply terminal), its gate is connected to the gate of PT511, its drain is connected to node ND512 (second circuit node));
a logic stage coupled to receive the output of the single-ended cascode amplifier, and configured to provide an output of the current comparator (Figs. 17 & 27; [0274], [0352] & [0365]-[0375]: logic gate 610 (an inverter composed of PT611 and NT611) is connected to, see Fig. 27, the output node ND521 of the second amplifier 520 to provide the final comparator output, the output of the 2nd amplifier 520 (ND521) is the output of the comparator 500 (TOUT) and the output of the logic stage ND611(C) is the output of the logic gate and serves as the final output); and
PNG
media_image1.png
659
1009
media_image1.png
Greyscale
PNG
media_image2.png
676
1004
media_image2.png
Greyscale
PNG
media_image3.png
621
986
media_image3.png
Greyscale
Ueno, and Hanzawa, are silent in regard to:
a set of auto-zero switches configured to, in response to an auto-zero control signal, selectively short the control electrode of the first transistor to the second current electrode of the first transistor and selectively short the control electrode of the second transistor to the second current electrode of the second transistor.
However, Berens, further teaches:
a set of auto-zero switches configured to, in response to an auto-zero control signal, selectively short the control electrode of the first transistor to the second current electrode of the first transistor and selectively short the control electrode of the second transistor to the second current electrode of the second transistor (Fig. 3; [0019]-[0020] & [0023]-[0024]: switch 59 is an auto-zero switch that is closed during the auto-zero phase, shorting the control electrode (gate) and the second current electrode (drain) of transistor 60 (a diode-connected transistor in the first stage)).
PNG
media_image4.png
609
761
media_image4.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a set of auto-zero switches configured to, in response to an auto-zero control signal, selectively short the control electrode of the first transistor to the second current electrode of the first transistor and selectively short the control electrode of the second transistor to the second current electrode of the second transistor, of Berens to Ueno and Hanzawa, in order to attain, by combining prior art references that operate in the same field (CMOS image sensor ADCs) and address related problems (offset, delay, noise), and motivated to improve the overall comparator, where Ueno teaches auto-zero switches that short the gate-to-drain of the input transistors, and Berens provides a simplified example of the exact function, where switch 59 shorts the gate and drain of a transistor 60 during auto-zero, by combination, such a configuration for offset cancellation is known and makes it obvious to apply the known technique to improve the comparator of Ueno, and yield expected predictable results (KSR).
Ueno, in combination with Hanzawa, and Berens, are silent in regard to:
a single-ended cascode amplifier having an input and an output, wherein the second circuit node is coupled to a first terminal of a third capacitor, and a second terminal of the third capacitor, different from the first terminal, is coupled to the input of the single-ended cascode amplifier;
However, Omran, further teaches:
a single-ended cascode amplifier having an input and an output, wherein the second circuit node is coupled to a first terminal of a third capacitor, and a second terminal of the third capacitor, different from the first terminal, is coupled to the input of the single-ended cascode amplifier (Figs. 8 & 9; [0116], [0118] & [0125]: teaches placing a third capacitor COS in series between stages to isolate DC offsets, and using a single-ended cascode architecture for the subsequent amplifier stage to boost again);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the auto-zeroed current comparator of Ueno to include an AC-coupled single-ended cascode amplifier at the output of the first stage, as taught by Omran, according to known methods. A POSITA would have been motivated to make this modification for the purpose of increasing the voltage gain of the subsequent amplifier stage, while utilizing the series capacitor, simultaneously, to block and store DC offset values between the stages during the auto-zeroing phase. Doing so would prevent the propagation of mismatch errors from the first stage to the logic gate, improving the sensitivity and accuracy of Ueno’s comparator using known circuit techniques, and yielding predictable results (KSR).
Regarding dependent claim 7, Ueno, teaches:
The current comparator of claim 1 (Figs. 17 & 25; [0031]-[0032], [0244]-[0245], [0248]-[0249], [0251]-[0252], [0266], [0275] & [0330]-[0331]: comparator 500), wherein the current comparator is configured to operate in an auto-zero phase followed by a compare phase ([0024], [0048], [0251]-[0253] & [0270]-[0271]: AZ phase sets the operating point before the comparison operation begins),
Ueno, and Hanzawa, are silent in regard to:
wherein, during the auto-zero phase, the set of auto-zero switches are configured to short the control electrode to the second current electrode of each of the first and second transistors, and during the compare-phase, the set of auto-zero switches is each in a high-impedance state.
However, Berens, further teaches:
wherein, during the auto-zero phase ([0023]), the set of auto-zero switches are configured to short the control electrode to the second current electrode ([0023]-[0024]: switch 59, transistor 60) of each of the first and second transistors ([0019]-[0020]), and during the compare-phase, the set of auto-zero switches is each in a high-impedance state ([0023]-[0025]: an open switch is a high-impedance state, breaks the AZ short, allowing the circuit to perform the comparison).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate during the auto-phase, the set of auto-zero switches configured to short the control electrode to the second current electrode of each of the first and second transistors, and during the compare-phase, the set of auto-zero switches is each in a high-impedance state, of Berens to Ueno and Hanzawa, according to known methods. In order to attain and improve the accuracy of the comparator disclosed by Ueno, combining Ueno’s two-phase comparator architecture with the well-known auto-zeroing technique taught by Berens. Applying the shorting technique to both transistors (first and second), leading to improved zero current detection described by Berens, that yield expected predictable results, addressing the offset mismatch in comparators (KSR).
Regarding dependent claim 8, Ueno, teaches:
the current comparator of claim 1 (Figs. 17 & 25; [0031]-[0032], [0244]-[0245], [0248]-[0249], [0251]-[0252], [0266], [0275] & [0330]-[0331]: comparator 500);
Ueno, and Hanzawa, are silent in regard to:
A DC-DC converter comprising:
an input signal switch configured to provide auto-zero phase inputs as the first and second input signals of the current comparator during the auto-zero phase and to provide compare phase inputs as the first and second input signals of the current capacitor during the compare phase.
However, Berens, further teaches:
A DC-DC converter comprising ([Abstract], [0005], [0014], [0025] & [0027]):
an input signal switch configured to provide auto-zero phase inputs as the first and second input signals of the current comparator during the auto-zero phase (Fig. 3; [0017]-[0020], [0023] & [0025]) and to provide compare phase inputs as the first and second input signals of the current capacitor during the compare phase (Fig. 3; [0017]-[0020], [0023] & [0025]-[0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a DC-DC converter comprising, an input signal switch configured to provide auto-zero phase inputs as the first and second input signals of the current comparator during the auto-zero phase and to provide compare phase inputs as the first and second input signals of the current capacitor during the compare phase, of Berens to Ueno and Hanzawa, in order to attain and improve the accuracy of the comparator disclosed by Ueno, combining Ueno’s two-phase comparator architecture with the DC-DC buck converter that includes a comparator, the two-phase operation that distinguishes between auto-zero phase and the compare phase, and the use of set input switches for these phases of Berens, where Berens teaches how to implement an input signal switch for auto-zero/compare phases of a DC-DC converter, and applying the auto-zero switching scheme to the comparator of Ueno to improve the DC-DC converter accuracy by mitigating comparator offset errors, and yield expected predictable results (KSR).
Regarding dependent claim 9, Ueno, and Hanzawa, are silent in regard to:
The DC-DC converter of claim 8, wherein the auto-zero phase inputs provided as the first and second input signals during the auto-zero phase are a same signal, and the compare phase inputs provided as the first and second input signals during the compare phase are a pair of signals being compared such that the output of the current comparator is provided based on the comparison of the pair of signals.
However, Berens, further teaches:
The DC-DC converter of claim 8 ([Abstract], [0005], [0014]-[0016], [0025] & [0027]-[0028]), wherein the auto-zero phase inputs provided as the first and second input signals during the auto-zero phase are a same signal ([0014]-[0015], [0023]-[0025] & [0036]), and the compare phase inputs provided as the first and second input signals during the compare phase are a pair of signals being compared ([0016], [0025]-[0026] & [0038) such that the output of the current comparator is provided based on the comparison of the pair of signals ([0016], [0025]-[0026] & [0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the DC-DC converter, wherein the auto-zero phase inputs provided as the first and second input signals during the auto-zero phase are a same signal, and the compare phase inputs provided as the first and second input signals during the compare phase are a pair of signals being compared such that the output of the current comparator is provided based on the comparison of the pair of signals, of Berens to Ueno and Hanzawa, in order to attain and improve the accuracy of the comparator disclosed by Ueno, modifying the DC-DC converter of Berens, that teaches a two-phase comparator with auto-zero and compare modes, with the auto-zero comparator structures of Ueno or Hanzawa, where Berens provides the core application, DC-DC converter, and the overall operational method (auto-zero phase with equal inputs, compare phase with differential inputs), and Ueno and Hanzawa provide details on how a comparator is constructed and operated, confirming that the function of shorting inputs during an auto-zero phase is a standard technique in the field of analog comparison, such as in image sensors and AD converters, therefore the claimed invention is a predictable combination of known prior art elements that will improve the DC-DC converter accuracy, and yield expected predictable results (KSR).
Regarding dependent claim 10, Ueno, and Hanzawa, are silent in regard to:
The DC-DC converter of claim 8, further comprising:
a power switch having a PMOS transistor in series with an NMOS transistor, wherein a first internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor.
However, Berens, further teaches:
The DC-DC converter of claim 8 (Fig. 1; [Abstract], [0005], [0014]-[0015] & [0028]), further comprising:
a power switch (Fig. 1; [0005] &[0015]: PMOS transistor 14 and NMOS transistor 28 are the main power switches) having a PMOS transistor in series with an NMOS transistor (Fig. 1; [0005] & [0015]: PMOS14 and NMOS28 are connected in series between Vin and ground), wherein a first internal circuit node between the PMOS transistor and the NMOS transistor (Fig. 1; [0005] & [0015]: circuit node 16) is configured to be coupled to an inductor (Fig. 1; [0005] & [0015]: PMOS14 and NMOS28 power switches are coupled directly to the inductor 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the DC-DC converter, where a power switch having a PMOS transistor in series with an NMOS transistor, a first internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor, of Berens to Ueno and Hanzawa, in order to attain and improve the accuracy of the comparator disclosed by Ueno, where Berens discloses a DC-DC buck converter that utilizes PMOS transistor 14 and NMOS transistor 28 as power switches for synchronous rectification, the two transistors are connected to a common node, circuit node 16 (Vcoil), and the same node is coupled to the inductor 18, which is the standard half-bridge power stage for a synchronous buck converter, as disclosed by Berens, that would be combined with the general comparator structure of series-connected PMOS/NMOS transistor pairs as taught by Ueno and Hanzawa, where combining the prior art teachings to form the claimed power switch only involves the predictable use of prior art elements (the PMOS/NMOS series pair) acting as a switch in the known field of power conversion circuits, therefore the claimed invention is a predictable combination of known prior art elements that will improve the DC-DC converter accuracy, and yield expected predictable results (KSR).
Regarding dependent claim 11, Ueno, and Hanzawa, are silent in regard to:
The DC-DC converter of claim 10, wherein:
during the auto-zero phase, the input signal switch couples a first ground signal to each of the first and second input signals of the current comparator, and during the compare phase, the input signal switch couples a second internal circuit node of the power switch and a second ground signal to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when a voltage on the second internal circuit node reaches a voltage of the second ground signal.
However, Berens, further teaches:
The DC-DC converter of claim 10 (Fig. 1; [Abstract], [0005], [0014]-[0015], & [0027]-[0028]), wherein:
during the auto-zero phase, the input signal switch couples a first ground signal to each of the first and second input signals of the current comparator (Fig. 3; [0023]-[0025]), and during the compare phase ([0023]-[0025]), the input signal switch couples a second internal circuit node of the power switch and a second ground signal to the first and second input signals of the current comparator (Figs. 1 & 3; [0005], [0015], & [0023]-[0025]), wherein the output of the current comparator indicates when a voltage on the second internal circuit node reaches a voltage of the second ground signal ([0016]-[0017] & [0023]-[0025]: the output signal RECT32 from the comparator indicates the moment when the voltage at the internal node (Vcoil) reaches or crosses the voltage of the ground signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the DC-DC converter, that during the auto-zero phase, the input signal switch couples a first ground signal to each of the first and second input signals of the current comparator, and during the compare phase, the input signal switch couples a second internal circuit node of the power switch and a second ground signal to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when a voltage on the second internal circuit node reaches a voltage of the second ground signal, of Berens to Ueno and Hanzawa, according to known methods. In order to attain and improve the accuracy of the comparator disclosed by Ueno, where Berens discloses a DC-DC buck converter, a two-phase operation (AZ and compare), during the AZ phase both comparator inputs are coupled to the same signal (ground), during the compare phase, one input is coupled to the internal circuit node (Vcoil) and the other input is coupled to ground, and the comparator’s output indicates when Vcoil reaches zero (ground), by combining a two-phase comparator (Ueno or Berens) used in the DC-DC converter of Berens to perform zero-current detection by applying a common reference input (AZ) and then monitoring the Vcoil node versus ground (comparing). Outputting a signal when zero-crossing is contained, therefore the claimed invention is a predictable combination of known prior art elements that will improve the DC-DC converter accuracy, and yield expected predictable results (KSR).
Regarding dependent claim 12, Ueno, and Hanzawa, are silent in regard to:
The DC-DC converter of claim 11, further comprising:
control circuitry, wherein when the output of the current comparator is asserted to indicate that the voltage on the second internal circuit node has reached the voltage of the second ground signal, the control circuitry disables the NMOS transistor of the power switch.
However, Berens, further teaches:
The DC-DC converter of claim 11 (Fig. 1; [Abstract], [0005], [0014]-[0016], & [0027]-[0028]), further comprising:
control circuitry ([0015]-[0017]: combination of the comparator output (RECT32), the inverter 26 and the AND gate 30, interpreted as “control circuitry,” that processes the comparator’s output to generate a control signal NG for the power switch), wherein when the output of the current comparator is asserted ([0015]-[0017]: assertion of the output RECT32 indicates the voltage on the internal circuit node Vcoil has reached the reference (ground)) to indicate that the voltage on the second internal circuit node has reached the voltage of the second ground signal ([0015]-[0017] & [0025]: the second internal circuit node is the first current electrode of transistor 28, which is node 16 (Vcoil), the second ground signal is the ground potential connected to the comparator’s negative input, comparator asserts its output when the voltage at node 16 reaches the ground potential, indicating zero current), the control circuitry disables the NMOS transistor of the power switch ([0006] & [0015]-[0017]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the DC-DC converter, the control circuitry, wherein when the output of the current comparator is asserted to indicate that the voltage on the second internal circuit node has reached the voltage of the second ground signal, the control circuitry disables the NMOS transistor of the power switch, of Berens to Ueno and Hanzawa, according to known methods. In order to attain and improve the accuracy of the comparator disclosed by Ueno, where Berens discloses every limitation of the claimed element, the buck converter (DC-DC converter) uses a comparator 24 to monitor the voltage at node 16 (Vcoil) relative to ground. When the voltage reaches ground, indicates zero inductor current, the comparator asserts its output signal RECT32, the signal is fed into control circuitry comprising inverter 26 and an AND gate 30, then the circuitry drives the gate signal NG’ of the NMOS transistor 28 of the power switch to a logic low, disabling it. A POSITA would find it obvious to combine the teachings/elements of Ueno and Hanzawa, therefore the claimed invention is a predictable combination of known prior art elements that will improve the DC-DC converter accuracy, and yield expected predictable results (KSR).
Regarding dependent claim 13, Ueno, and Hanzawa, are silent in regard to:
The DC-DC converter of claim 12, wherein:
the power switch further comprises an additional NMOS transistor coupled between the NMOS transistor of the power switch and a third voltage supply terminal configured to provide the second ground signal, the second internal circuit node of the power switch corresponds to a node between the NMOS transistor and the additional NMOS transistor of the power switch, and the first ground signal is provided by one of the second voltage supply terminal or the third voltage supply terminal.
However, Berens, further teaches:
The DC-DC converter of claim 12 (Fig. 1; [Abstract], [0005], [0014]-[0016], [0025], & [0027]-[0028]), wherein:
the power switch further comprises an additional NMOS transistor coupled between the NMOS transistor of the power switch and a third voltage supply terminal configured to provide the second ground signal (Figs. 1 & 3; [0015]-[0019], [0022]-[0025], & [0029]: transistor 44 (NMOS) is coupled between other circuit elements and transistor 46 (an additional NMOS), whose source is connected to ground (third voltage supply terminal)), the second internal circuit node of the power switch corresponds to a node between the NMOS transistor and the additional NMOS transistor of the power switch (Figs. 1 & 3; [0014]-[0017] & [0025]: figures further illustrates node 16 is formed by the interconnection of transistors 28, 44, 46, 66, 68, 70, etc., where the connection between transistor 28 and transistor 444 is part of node 16, illustrating a node between the NMOS transistor and additional NMOS transistor), and the first ground signal is provided by one of the second voltage supply terminal or the third voltage supply terminal ([0011], [0015]-[0017], & [0025]: discloses that during the auto-zero phase, both comparator inputs are set to ground, the negative input during the compare phase is coupled to ground, NMOS power switch is also coupled to ground).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the DC-DC converter, where the power switch further comprises an additional NMOS transistor coupled between the NMOS transistor of the power switch and a third voltage supply terminal configured to provide the second ground signal, the second internal circuit node of the power switch corresponds to a node between the NMOS transistor and additional NMOS transistor of the power switch, and the first ground signal is provided by one of the second voltage supply terminal or the third voltage supply terminal, of Berens to Ueno and Hanzawa, in order to attain and improve the accuracy of the comparator disclosed by Ueno, where Berens discloses the DC-DC buck converter using an MOS power switch 28 coupled to ground, and a comparator 24 that uses a common ground signal for auto-zeroing and senses the Vcoil node 16 versus ground for zero-current detection, and employs the claimed transistor stacking configuration, and would have been obvious to apply the robust, multi-transistor grounding and sensing architecture of Berens to the general power switching circuitry of Ueno to improve performance, manage different circuit domains, and enhance control, therefore the claimed invention is a predictable combination of known prior art elements, and yield expected predictable results (KSR).
Regarding independent claim 16, Ueno, teaches:
A current comparator (Figs. 17 & 25; [Abstract], [0031]-[0032] & [0330]-0331]: comparator 500), comprising:
a first capacitor having a first terminal coupled to a first input signal (Figs. 17 & 25; [0031], [0256]-[0257], [0263] & [0334]: capacitor C511 has a second electrode connected to input terminal TRAMP for the ramp signal (first input signal));
a second capacitor having a first terminal coupled to a second input signal (Figs. 17 & 25; [0031], [0255]-[0257], [0263], [0285] & [0334]: capacitor C512 has a second electrode connected to input terminal TVSL for the analog signal VSL (second input signal));
a first transistor (Figs. 17 & 25; [0251] & [0263]: NT511) having a first current electrode coupled to a first voltage supply terminal (Fig. 17; [0253], [0255]-[0256] & [0285]: GND) via a first current source (Fig. 17; [0255]-[0256] & [0285]: NT513), a control electrode (Fig. 17; [0257]: C511 gate) coupled to a second terminal of the first capacitor (Fig. 17; [0256]-[0257]: node ND513, second terminal of C511 (first capacitor)), and a second current electrode (Fig. 17; [0253], [0256]-[0257] & [0333]: C512) coupled to a first circuit node (Figs. 17 & 25; [0250]-[0251], [0253]-[0260] & [0333]: gate of NT511 (first transistor) is coupled to the first electrode of C511 (second terminal of the first capacitor), its gate (control electrode) is connected to node ND513 (second terminal of C511 (first capacitor)), the gate of NT512 (second transistor) is coupled to the first electrode of C512 (second terminal of second capacitor), its drain (first current electrode) is connected to node ND511, the current source is transistor NT513, which is connected between the sources of NT511/NT512, and GND (first voltage supply terminal), and node ND511 is the first circuit node);
a second transistor having a first current electrode (Figs. 17 & 25; [0254]-[0255] & [0333]: NT512) coupled to the first current electrode of the first transistor (Fig. 17; [0254]-[0255]: NT512 source (first current electrode) coupled to the source of NT511 (coupled to NT513 current source)), a control electrode coupled to a second terminal of the second capacitor (Fig. 17; [0257]: second terminal of C512), and a second current electrode (Fig. 17; [0255]: drain coupled to ND512) coupled to a second circuit node (Figs. 17 & 25; [0250]-[0251], [0253]-[0260] & [0333]: transistor NT512 (second transistor), its gate is connected to node ND514 (second terminal of C512), its drain is connected to the drain of NT511 (shared connection), its source is connected to the source of NT511, the second current electrode (drain) is connected to output node ND512 (second circuit node));
a third transistor (Figs. 17 & 25; [0253] & [0333]-[0334]: PT511) having a first current electrode (Fig. 17; [0253]: drain of PT511) coupled to the first circuit node (Fig. 17; [0253]: connected to node ND511), a second current electrode (Fig. 17; [0253]: source of PT511) coupled to a second voltage supply terminal (Figs. 17 & 25; [0253] & [0333]-[0334]: VDD), and a control electrode coupled to the first circuit node (Figs. 17 & 25; [0250]-[0260] & [0333]-[0334]: transistor PT511 (third transistor), its source (first current electrode) is connected to VDD (second voltage supply terminal), its drain is connected to node ND511 (first circuit node), its gate (control electrode) is connected to its drain and to node ND512 (diode-connected));
a fourth transistor (Figs. 17 & 25; [0255] & [0333]-[0334]: PT512) having a first current electrode (Fig. 17; [0255]: drain of PT512) coupled to the second circuit node (Fig. 17; [0255]: coupled to ND512), a control electrode coupled to the control electrode of the third transistor (Fig. 17; [0253]-[0254]: gate of PT512 (control electrode) is coupled to the connection point of the drain and gate of PT511 (control electrode of PT511)), and a second current electrode (Fig. 17 & 25; [0253]-[0254] & [0333]-[0334]: source of PT512) coupled to the second voltage supply terminal (Figs. 17 & 25; [0250]-[0260] & [0333]-[0334]: transistor PT512 (fourth transistor), its source is connected to VDD (second voltage supply terminal), its gate is connected to the gate of PT511, its drain is connected to node ND512 (second circuit node)); and
wherein the current comparator is configured to operate in an auto-zero phase followed by a compare phase ([0248], [0262]-[0265] & [0281]-[0287]: the comparator utilizes an auto-zero phase followed by a normal comparison phase),
Ueno, and Hanzawa, are silent in regard to:
wherein, during the auto the auto-zero phase, the current comparator is configured to short the control electrode to the second current electrode of each of the first and second transistors, and during the compare phase, the current comparator is configured to not short the control electrode to the second control electrode of each of the first and second transistors.
However, Berens, further teaches:
wherein, during the auto-phase, the current comparator is configured to short the control electrode to the second current electrode of each of the first and second transistors (Fig. 3; [0019]-[0020] & [0023]-[0024]: switch 59 is an auto-zero switch that is closed during the auto-zero phase, shorting the control electrode (gate) and the second current electrode (drain) of transistor 60 (a diode-connected transistor in the first stage)), and during the compare phase, the current comparator is configured to not short the control electrode to the second current electrode of each of the first and second transistors (Fig. 3; [0023]-[0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the current comparator configured to operate in an auto-zero phase followed by a compare phase, wherein, during the auto-phase, the current comparator is configured to short the control electrode to the second current electrode of each of the first and second transistors, and during the compare phase, the current comparator is configured to not short the control electrode to the second current electrode of each of the first and second transistors, of Berens to Ueno and Hanzawa, according to known methods. In order to attain, by combining prior art references that operate in the same field (CMOS image sensor ADCs) and address related problems (offset, delay, noise). A POSITA, motivated to improve the overall comparator, where Ueno teaches auto-zero switches that short the gate-to-drain of the input transistors, and Berens teaches operating a comparator in two distinct phases, an auto-zero phase followed by a compare phase, describing that during the auto-zero phase, a switch is closed to short the control electrode to the second current electrode of a transistor, and that during the compare phase, this switch is opened, ceasing to short, by combining and implementing the auto-zero function taught by Berens in the comparator structure of Ueno. Where applying the phasing of Ueno’s AZ switches as a matter of design choice to cancel the offset, and such a configuration for offset cancellation is known and makes it obvious to apply the known technique to improve the comparator of Ueno, and yield expected predictable results (KSR).
Ueno, in combination with Hanzawa, and Berens, are silent in regard to:
a single-ended cascode amplifier having an input and an output, wherein the second circuit node is coupled to a first terminal of a third capacitor, and a second terminal of the third capacitor, different from the first terminal, is coupled to the input of the single-ended cascode amplifier;
However, Omran, further teaches:
a single-ended cascode amplifier having an input and an output, wherein the second circuit node is coupled to a first terminal of a third capacitor, and a second terminal of the third capacitor, different from the first terminal, is coupled to the input of the single-ended cascode amplifier (Figs. 8 & 9; [0116], [0118] & [0125]: teaches placing a third capacitor COS in series between stages to isolate DC offsets, and using a single-ended cascode architecture for the subsequent amplifier stage to boost again);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the single-ended cascode of Ueno to be a single-ended cascode amplifier, as taught by Omran, according to known methods. A POSITA would have been motivated to make this modification for the purpose of increasing the amplifier’s gain of the subsequent amplifier stage, while utilizing the series capacitor, simultaneously, to block and store DC offset values between the stages during the auto-zeroing phase. A POSITA would recognize that increasing the gain of Ueno’s second stage would improve the sensitivity, accuracy, and comparison of the comparator, prevent the propagation of mismatch errors from the first stage to the logic gate, further improving the sensitivity and accuracy of Ueno’s comparator using known circuit techniques, and yielding predictable results (KSR).
Regarding dependent claim 17, Ueno, teaches:
The current comparator of claim 16 (Figs. 17 & 25; [Abstract], [0031]-[0032] & [0330]-[0331]: comparator 500), further comprising:
a logic stage coupled to receive the output of the single-ended cascode amplifier, and configured to provide an output of the current comparator (Figs. 17 & 27; [0352] & [0365]-[0375]: logic gate 610 (an inverter composed of PT611 and NT611) is connected to, see Fig. 27, the output node ND521 of the second amplifier 520 to provide the final comparator output, the output of the 2nd amplifier 520 (ND521) is the output of the comparator 500 (TOUT) and the output of the logic stage ND611(C) is the output of the logic gate and serves as the final output).
Regarding dependent claim 19, Ueno, teaches:
the current comparator of claim 16 (Figs. 17 & 25; [Abstract], [0031]-[0032] & [0330]-[0331]: comparator 500);
Ueno, in combination with Hanzawa, are silent in regard to:
A first DC-DC converter comprising:
a power switch having a PMOS transistor in series with an NMOS transistor, wherein an internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor, wherein:
during the auto-zero phase, a first ground signal is provided as each of the first and second input signals of the current comparator, and
during the compare phase, a second internal circuit node of the power switch and a second ground signal are provided to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when a voltage on the second internal circuit node reaches a voltage of the second ground signal.
However, Berens, further teaches:
A first DC-DC converter comprising (Fig. 1; [Abstract], [0005], [0008], [0014]-[0016], [0025], & [0027]-[0028]: teaches a DC-DC converter comprising a comparator): a power switch (Fig. 1; [0005] &[0015]: PMOS transistor 14 and NMOS transistor 28 are the main power switches) having a PMOS transistor in series with an NMOS transistor (Fig. 1; [0005] & [0015]: PMOS14 and NMOS28 are connected in series between Vin and ground), wherein an internal circuit node between the PMOS transistor and the NMOS transistor (Fig. 1; [0005] & [0015]: circuit node 16) is configured to be coupled to an inductor (Fig. 1; [0005] & [0015]: PMOS14 and NMOS28 power switches are coupled directly to the inductor 18, Fig. 1 further illustrates a standard synchronous power stage (power switch) where PMOS transistor 14 is in series with NMOS transistor 28, they connect at an internal circuit node 16, which is directly coupled to inductor 18), wherein:
during the auto-zero phase, a first ground signal is provided as each of the first and second input signals of the current comparator (Figs. 2 & 3; [0023]-[0025]: Fig. 2 illustrates signals during AP1/AP2, teaches an auto-zero phase where switches (transistors 66 and 72) are used to short both the positive and the negative inputs of the comparator to a ground signal), and
during the compare phase ([0023]-[0025]), a second internal circuit node of the power switch and a second ground signal are provided to the first and second input signals of the current comparator (Figs. 1, 2, & 3; [0005], [0015], & [0023]-[0025]: Fig. 2 illustrates signals during CP1/CP2: during the compare phase, teaches reconfiguring the input switches so that one input receives the voltage from the internal switch node 16 located between the PMOS and NMOS, and the other input receives a ground signal), wherein the output of the current comparator indicates when a voltage on the second internal circuit node reaches a voltage of the second ground signal ([0016]-[0017] & [0023]-[0025]: the output signal RECT32 from the comparator indicates the moment when the voltage at the internal node (Vcoil) reaches or crosses the voltage of the ground signal, further, teaches that the comparator functions as a zero-crossing detector, comparing the switch node voltage against ground, and outputs a signal RECT32 when it detects the zero-crossing to shut off the NMOS transistor and prevent reverse current).
PNG
media_image5.png
718
668
media_image5.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the DC-DC converter, where a power switch having a PMOS transistor in series with an NMOS transistor, wherein an internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor, where during the auto-zero phase, a first ground signal is provided as each of the first and second input signals of the current comparator, and during the compare phase, a second internal circuit node of the power switch and a second ground signal are provided to the first and second input signals of the current comparator, where the output of the current comparator indicates when a voltage on the second internal circuit node reaches a voltage of the second ground signal, of Berens to Ueno and Hanzawa, according to known methods. In order to attain and improve the accuracy of the comparator disclosed by Ueno, where Ueno provides a comparator with auto-zero and compare phases, where its inputs are switched between different signals (e.g., a common mode during AZ and two different potentials during compare), and also teaches a general output behavior of a comparator upon input signal crossing. Berens discloses the application of Ueno’s comparator in a DC-DC buck converter, detailing the power switch, PMOS transistor 14 and NMOS transistor 28, the internal node 16 (Vcoil) between them, the inductor 18 connected to that node, the specific input signals to the comparator during the auto-zero phase (both inputs to ground), the input signals during the compare phase (internal node voltage vs. ground), and the purpose of the comparator output. A POSITA would find it obvious to modify the internal comparator of Omran and the gate-to-drain auto-zeroing switches of Ebihara to increase the gain and resolution of the zero-crossing detector, ensuring a faster and more accurate shut-off of the NMOS transistor to improve the converter’s efficiency. Implementing a zero-current detection circuit in a synchronous DC-DC converter as taught by Berens, and combining with auto-zeroing from Ueno would be obvious to improve the accuracy and efficiency of the system, therefore the claimed invention is a predictable combination of known prior art elements that will improve the DC-DC converter accuracy, and yield expected predictable results (KSR).
Regarding dependent claim 20, Ueno, teaches:
the current comparator of claim 16 (Figs. 17 & [0025]; [Abstract], [0031]-[0032] & [0330]-[0331]: comparator 500);
Ueno, and Hanzawa, are silent in regard to:
A second DC-DC converter comprising:
a power switch having a PMOS transistor in series with an NMOS transistor, wherein
an internal circuit node between the PMOS transistor and the NMOS transistor is
configured to be coupled to an inductor, wherein:
during the auto-zero phase, a supply voltage is provided as each of the first and second input signals of the current comparator, and
during the compare phase, a voltage indicative of a predetermined maximum current through the inductor and the internal circuit node are coupled to the first and second input signals of the current comparator,
wherein the output of the current comparator indicates when a voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current.
However, Berens, further teaches:
A second DC-DC converter comprising (Fig. 1; [Abstract], [0005], [0008], [0014]-[0016], [0025], & [0027]-[0028]):
a power switch (Fig. 1; [0005] &[0015]: PMOS transistor 14 and NMOS transistor 28 are the main power switches) having a PMOS transistor in series with an NMOS transistor (Fig. 1; [0005] & [0015]: PMOS14 and NMOS28 are connected in series between Vin and ground), wherein an internal circuit node between the PMOS transistor and the NMOS transistor (Fig. 1; [0005] & [0015]: circuit node 16) is configured to be coupled to an inductor (Fig. 1; [0005] & [0015]: PMOS14 and NMOS28 power switches are coupled directly to the inductor 18), wherein:
during the auto-zero phase, a supply voltage is provided as each of the first and second input signals of the current comparator (Figs. 1 & 3; [0023]-[0025] & [0036]: Vout (node 118) is the converter’s output voltage and a supply potential for the comparator reference, inputs to the comparator are set to be equal), and
during the compare phase, a voltage indicative of a predetermined maximum current through the inductor and the internal circuit node are coupled to the first and second input signals of the current comparator (Figs. 2 & 3; [0015]-[0017], [0023]-[0025], [0029] & [0038]),
wherein the output of the current comparator indicates when a voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current (Fig. 2; [0015]-[0017] & [0023]-[0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the DC-DC converter, where a power switch having a PMOS transistor in series with an NMOS transistor, where an internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor, where during the auto-zero phase, a supply voltage is provided as each of the first and second input signals of the current comparator, and during the compare phase, a voltage indicative of a predetermined maximum current through the inductor and the internal circuit node are coupled to the first and second input signals of the current comparator, where the output of the current comparator indicates when a voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current, of Berens to Ueno and Hanzawa, in order to attain and improve the accuracy of the comparator disclosed by Ueno, where Ueno provides a comparator with auto-zero and compare phases, where its inputs are switched between different signals (e.g., a common mode during AZ and two different potentials during compare), and also teaches a general output behavior of a comparator upon input signal crossing, and Berens discloses the DC-DC buck converter structure including a power switch, PMOS transistor 14 and NMOS transistor 28, the internal node 16 (Vcoil) between them, the inductor 18 connected to that node, and a comparator 24 whose output indicates when a voltage on the internal node reaches a voltage indicative of a predetermined current (zero current) through the inductor, Ueno and Hanzawa teach a detailed comparator with an auto-zero (AZ) phase and a compare phase, where a POSITA seeking to improve the accuracy and noise performance of the comparator in Berens’ DC-DC converter would be motivated to incorporate the auto-zero comparator architecture from Ueno or Hanzawa, and apply a known voltage, such as a supply voltage or ground (as taught by Berens for setting inputs equal), to both inputs of the Ueno/Hanzawa comparator to cancel offset, during the compare phase would connect the inputs as taught by Berens, one to the internal node Vcoil and the other to the reference voltage indicative of the target current (ground, for zero current detection), and the output would function as disclosed by both Berens and Ueno to indicate the crossing point, therefore the claimed invention is an obvious combination of the teachings of Berens, Ueno, and Hanzawa that will improve the DC-DC converter accuracy, and yield expected predictable results (KSR).
Claims 2-6 & 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ueno, in view Hanzawa, in view of Berens, in view of Omran, and further in view of Ebihara et al. (US 2018/0091752 A1, Pub. Date Mar. 29, 2018, hereinafter, Ebihara).
Regarding dependent claim 2, Ueno, teaches:
The current comparator of claim 1 (Figs. 17 & 25; [0031]-[0032] & [0330]-[0331]: comparator 500), wherein the single-ended cascode amplifier comprises (Figs. 17 & 27; [0265]-[0269] & [0272]: second amplifier 520):
a fifth transistor having a control electrode configured as the input of the single-ended cascode amplifier, a first current electrode coupled to the second voltage supply terminal, and a second current electrode (Figs. 17 & 27; [0265]-[0269] & [0273]: PMOS transistor PT521 corresponds to the fifth transistor, its gate is the input (connected to ND512), its source (first current electrode) of PT521 is coupled to VDD (the second voltage supply terminal) and it has a drain (second current electrode)),
Ueno, in combination with Hanzawa, and Berens, are silent in regard to:
wherein the second terminal of the third capacitor is coupled to the control electrode of the fifth transistor; and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode, and a second current electrode coupled to the output of the single-ended cascode amplifier,
However, Omran, further teaches:
wherein the second terminal of the third capacitor is coupled to the control electrode of the fifth transistor (Figs. 8-9 & 11; [0115]-[0116] & [0122]: the series capacitor from the previous claim couples to the gate of the input transistor of the cascode stage); and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode, and a second current electrode coupled to the output of the single-ended cascode amplifier (Fig. 9; [0118] & [0125]: maps the physical connections of a standard cascode (sixth) transistor stacked on top of an input (fifth transistor), with the source (first current electrode) is coupled to the drain of the 5th transistor, and the drain (second current electrode) serves as the output node),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the auto-zeroed current comparator of Ueno to include an AC-coupled single-ended cascode amplifier at the output of the first stage, as taught by Omran, according to known methods. A POSITA would have been motivated to make this modification for the predictable purpose of increasing the voltage gain of the subsequent amplifier stage, while utilizing the series capacitor to block and store DC offset voltages between the stages during the auto-zeroing phase. Doing so would prevent the propagation of mismatch errors from the first stage to the logic gate, improving the overall sensitivity and accuracy of Ueno’s comparator.
Ueno, in combination with Hanzawa, Berens, and Omran, are silent in regard to:
wherein the set of auto-zero switches is further configured to, in response to the auto-zero control signal, selectively short the control electrode of the fifth transistor to the second current electrode of the fifth transistor and selectively short the control electrode of the sixth transistor to the second current electrode of the sixth transistor.
However, Ebihara, further teaches:
wherein the set of auto-zero switches is further configured to, in response to the auto-zero control signal, selectively short the control electrode of the fifth transistor to the second current electrode of the fifth transistor and selectively short the control electrode of the sixth transistor to the second current electrode of the sixth transistor (Fig. 5; [0070] & [0075]-[0076]: teaches an auto-zero phase (controlled by XAZ_1) that simultaneously selectively shorts the input gate (via AZQ1 to auto-zero input) and selectively shorts the cascode gate (via switch 552 to sample the CASC BIAS). Matches the dual-shorting configuration of the 5th and 6th control electrodes during the auto-zero phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the auto-zero switch of the Ueno and Omran combination to selectively short the control electrodes of both the fifth (input) and sixth (cascode) transistors during the auto-zero phase, as taught by Ebihara, according to known methods. A POSITA would have been motivated to make this modification for the purpose of locally sampling and holding the bias voltage for the cascode transistors during the auto-modification for the purpose of locally sampling and holding the bias voltage for the cascode transistors during the auto-zero phase. Doing so, would predictably shield the global bias lines from switching disturbances (reducing H-banding noise) and reduce kickback noise when the comparator flips, yielding a more stable and accurate high-gain comparator circuit (KSR).
Regarding dependent claim 3, Ueno, teaches:
The current comparator of claim 2 (Figs. 17 & 25; [0031]-[0032] & [0330]-[0331]: comparator 500),
Ueno, and Hanzawa, are silent in regard to:
wherein the control electrode of the sixth transistor is coupled to the second voltage supply terminal via a fourth capacitor.
However, Berens, further teaches:
wherein the control electrode of the sixth transistor is coupled to the second voltage supply terminal via a fourth capacitor (Fig. 23; [0023]: figure illustrates the gate of transistor 60 is coupled via capacitor 58 (fourth capacitor) to the circuit, which during auto-zero (switch 59 is closed), stores a voltage relative to the power supply, coupling it to the supply terminal for offset cancellation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the control electrode of the sixth transistor is coupled to the second voltage supply terminal via a fourth capacitor, of Berens to Ueno and Hanzawa, in order to attain, by combining prior art references that operate in the same field (CMOS image sensor ADCs) and address related problems (offset, delay, noise), where Berens discloses a comparator where the control electrode (gate) of a transistor 60 is coupled via a capacitor 58 for auto-zeroing , to improve the comparator of Ueno, and yield expected predictable results (KSR).
Regarding dependent claim 4, Ueno, teaches:
The current comparator of claim 2 (Figs. 17 & 25; [0031]-[0032] & [0330]-[0331]: comparator 500),
Ueno, is silent in regard to:
wherein the current comparator is configured to operate in an auto-zero phase followed by a compare phase, wherein, during the auto-zero phase, the set of auto-zero switches are configured to short the control electrode to the second current electrode of each of the first, second, fifth, and sixth transistors,
However, Hanzawa, further teaches:
wherein the current comparator is configured to operate in an auto-zero phase followed by a compare phase (Fig. 3; [0087]-[0093]: comparator 100A is described as having an AZ period (auto-zero phase) followed by a P-phase (compare phase for reset level) and D-phase (compare phase for signal level)), wherein, during the auto-phase, the set of auto-zero switches are configured to short the control electrode to the second current electrode of each of the first, second, fifth, and sixth transistors (Fig. 3; [0065]-[0075] & [0077]-[0085]: first transistor NT111, second transistor NT112, gates ND113/ND114 are shorted to the drains ND111/ND112 via AZ switches PT113 & PT114, when the AZ signal PSEL is active, fifth transistor NT121, sixth transistor PT121, the gate of the fifth transistor NT121 at node ND122 is shorted to its drain ND121 via AZ switch NT122, the sixth transistor PT121 is the input transistor of the second stage, gate is connected to node ND112 that is auto-zeroed by the first stage),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the current comparator is configured to operate in an auto-zero phase followed by a compare phase, wherein, during the auto-phase, the set of auto-zero switches are configured to short the control electrode to the second current electrode of each of the first, second, fifth, and sixth transistors, of Hanzawa to Ueno, in order to attain and improve the accuracy of the comparator disclosed by Ueno, which includes an AZ phase, would be motivated to incorporate the auto-zero and compare phase operation of Hanzawa, which is identical to Ueno’s technique and corroborates the technique, and yield expected predictable results (KSR).
Ueno, and Hanzawa, are silent in regard to:
and during the compare-phase, the set of auto-zero switches is each in a high-impedance state.
However, Berens, further teaches:
and during the compare-phase, the set of auto-zero switches is each in a high-impedance state (Figs. 3 & 4; [0023], [0025], [0027], : teaches that during the compare phase (PGB is LOW), switch 59 is open, an open switch is in a high-impedance state, breaking the short from the auto-zero phase and configures the comparator for normal operation to perform the comparison).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate during the compare-phase, the set of auto-zero switches is each in a high-impedance state, of Berens to Ueno and Hanzawa, in order to attain and improve the accuracy of the comparator disclosed by Ueno, which includes an AZ phase, would be motivated to incorporate the AZ technique of diode-connecting a load device to store offset, as taught by Berens, to achieve a more accurate comparison operation, accounting for device mismatch during the auto-zero period, and yield expected predictable results (KSR).
Regarding dependent claim 5, Ueno, teaches:
The current comparator of claim 4 (Fig. 17; [0031]-[0032], [0244], [0251]-[0252], [0266], & [0275]: comparator 500), wherein each of the first (Fig. 17; [0251]-[0253] & [0261]-[0262]: PMOS transistor PT511) and second transistors are PMOS transistors (Fig. 17; [0250]-[0254] & [0261]-[0262]: PMOS transistor PT512, amplifier 510 has PMOS transistors PT511 and PT512) and each of the third (Fig. 17; [0255]-[0256] & [0261]-[0263]: NMOS transistor NT511), fourth (Fig. 17; [0255]-[0257] & [0261]-[0263]: NMOS transistor NT512),
Ueno, and Hanzawa, are silent in regard to:
fifth, and sixth transistors are NMOS transistors.
However, Berens, further teaches:
fifth, and sixth transistors are NMOS transistors (Fig. 3; [0019]-[0020] & [0022]-[0024]: NMOS transistors NT 62, NT64, NT66, NT68, NT70, NT72, describes four NMOS transistors: differential pair NT62, NT64) and two NMOS input transistors NT68 and NT70, uses NMOS transistors as switches controlled by digital signals (e.g., PGB, NG) to configure the comparator’s operation mode (auto-zero, compare), describes how the NMOS transistors switch to set the input during the auto-zero phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate fifth, and sixth transistors are NMOS transistors, of Berens to Ueno and Hanzawa, according to known methods. In order to attain and improve the accuracy of the comparator disclosed by Ueno, combining the transistor scheme of Ueno with structural elements, such as the input switching/sampling arrangements or load elements found in the comparator of Berens, to achieve a robust comparator circuit, where selection of NMOS or PMOS devices for functions like current mirrors (PT511, PT512), differential pairs (NT511, NT512), or switching/current sources (NT513/NT521/NT522 in Ueno; or 62/64/68/70 in Berens) is a common practice to achieve desired performance metrics such as speed or noise cancellation, and the claimed language for the transistors describes a standard CMOS design that is apparent from the combination of prior art references, that yield expected predictable results (KSR).
Regarding dependent claim 6, Ueno, teaches:
The current comparator of claim 5 (Figs. 17 & 25; [0031]-[0032], [0244]-[0245], [0251]-[0252], [0263], [0266], [0273], [0275] & [0330]-[0331]: comparator 500), wherein each of the set of auto-zero switches is implemented as an NMOS transistor (Fig. 25; [0335]: describes an alternative embodiment where the auto-zero switches, which were implemented with PMOS transistors in the primary embodiment, are now implemented using NMOS transistors NT516 and NT517, instead of PMOS transistors PT513 and PT514 in Fig. 17).
Regarding dependent claim 18, Ueno, teaches:
The current comparator of claim 16 (Figs. 17 & 25; [Abstract], [0031]-[0032] & [0330]-[0331]: comparator 500), wherein the single-ended cascade amplifier comprises (Figs. 17 & 27; [0265]-[0269] & [0272]: second amplifier 520):
a fifth transistor having a control electrode configured as the input of the single-ended cascode amplifier, a first current electrode coupled to the second voltage supply terminal, and a second current electrode (Figs. 17 & 27; [0265]-[0269] & [0273]: PMOS transistor PT521 corresponds to the fifth transistor, its gate is the input (connected to ND512), its source (first current electrode) of PT521 is coupled to VDD (the second voltage supply terminal) and it has a drain (second current electrode)),
Ueno, in combination with Hanzawa, and Berens, are silent in regard to:
wherein the second terminal of the third capacitor is coupled to the control electrode of the fifth transistor; and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode, and a second current electrode coupled to the output of the single-ended cascode amplifier,
However, Omran, further teaches:
wherein the second terminal of the third capacitor is coupled to the control electrode of the fifth transistor (Figs. 8-9 & 11; [0115]-[0116] & [0122]: the series capacitor from the previous claim couples to the gate of the input transistor of the cascode stage); and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode, and a second current electrode coupled to the output of the single-ended cascode amplifier (Fig. 9; [0118] & [0125]: a second NMOS transistor (the cascode transistor, mapping to the “sixth transistor”) is stacked above the input transistors, its source (first current electrode) is coupled to the drain (second current electrode) of the input transistor. Its gate (control electrode) is coupled to a bias, and its drain (second current electrode) is coupled to the output of the single-ended cascode amplifier),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the auto-zeroed current comparator of Ueno to configure the amplifier stage as a single-ended cascode amplifier, as taught by Omran, according to known methods. A POSITA would have been motivated to make this modification for the predictable purpose of increasing the voltage gain of the comparator stage without requiring a fully differential architecture. Utilizing a cascode configuration increases the output impedance and the gain of the amplifier stage. Upgrading with Omran’s cascode architecture would yield the predictable result (KSR) of a higher-gain, higher-resolution comparator capable of resolving small voltage differences during the compare phase, which is a desirable and expected improvement in analog-to-digital conversion circuits.
Ueno, in combination with Hanzawa, Berens, and Omran, are silent in regard to:
wherein the current comparator is further configured to:
during the auto-zero phase, short the control electrode of the fifth transistor to the second current electrode of the fifth transistor and short the control electrode of the sixth transistor to the second current electrode of the sixth transistor; and
during the compare phase, not short the control electrode to the second current electrode of each of the fifth and sixth transistors.
However, Ebihara, further teaches:
wherein the current comparator is further configured to:
during the auto-zero phase, short the control electrode of the fifth transistor to the second current electrode of the fifth transistor and short the control electrode of the sixth transistor to the second current electrode of the sixth transistor (Disclosed in combination: Ueno: [Abstract], [0031]-[0032], [0259]-0260] & [0330]-[0331]: similarly teaches switches that short the gate to the drain of input transistors during the AZ phase; Omran: [0116]: teaches an auto-zero phase using a feedback switch; Ebihara: Fig. 5; [0049], [0055], [0070] & [0075]-[0076]: teaches an auto-zero phase (controlled by XAZ_1) that simultaneously shorts the input gate (via AZQ1 to auto-zero input) and shorts the cascode gate (via switch 552 to sample the CASC BIAS). Matches the dual-shorting configuration of the 5th and 6th control electrodes during the auto-zero phase); and
during the compare phase, not short the control electrode to the second current electrode of each of the fifth and sixth transistors (Disclosed in combination: Ueno: [Abstract], [0031]-[0032], [0259]-0260] & [0330]-[0331]: similarly teaches switches that short the gate to the drain of input transistors during the AZ phase; Omran: [0116]: teaches an auto-zero phase using a feedback switch; Ebihara: Fig. 5; [0049], [0055], [0070] & [0075]-[0076]: teaches shorting the control electrode (gate) to the second current electrode (drain) of an amplifier transistor during an auto-zero phase and opening this short during the compare phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the comparator of Ueno and Omran to incorporate the specific auto-zeroing switch configuration taught by Ebihara, according to known methods. Configuring switches to short the control electrode to the second current electrode of the amplifier transistors during the auto-zero phase, and opening the short during the compare phase. A POSITA would have been motivated to make this modification to sample and cancel the inherent offset voltage of the cascode amplifier and to reduce low-frequency (1/f) noise. Incorporating Ebihara’s gate-to-drain shorting technique into Ueno’s/Omran comparator would yield the predictable result (KSR) of increasing the accuracy, sensitivity, and overall conversion range of the analog-to-digital converter, which are well-known benefits of diode-connecting amplifier transistors during an auto-zeroing phase.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ueno, in view Hanzawa, in view of Berens, in view of Omran, in view of Mednik (US 10778080 B1, Pat. Date Sep. 15, 2020, hereinafter, Mednik), and further in view of Chaput et al. (US 2020/0014395 A1, Put. Date Jan. 9, 2020, hereinafter, Chaput).
Regarding dependent claim 14, Ueno, in combination with Hanzawa, Berens, and Omran are silent in regard to:
The DC-DC converter of claim 10, wherein:
and during the compare phase, the input signal switch couples a voltage indicative of a predetermined maximum current allowed by a current rating of the inductor and the internal circuit node of the power switch to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when a voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current.
However, Mednik, further teaches:
The DC-DC converter of claim 10 ([Abstract]: utilizes a comparator within a switching DC-DC power converter), wherein:
and during the compare phase, the input signal switch couples a voltage indicative of a predetermined maximum current through the inductor (Fig. 9; [Col. 5, ll. 48-55]: teaches comparing the sensed current against a static, predetermined “maximum threshold voltage” (max voltage source in Fig. 9), fulfilling an OCP) and the internal circuit node of the power switch to the first and second input signals of the current comparator (Fig. 9; [Col. 5, ll. 1-22 & 48-55]: the current sense element 120 measures the current through the low-voltage switch 112 (internal circuit node), which is routed to the comparator 133), wherein the output of the current comparator indicates when a voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current ([Col. 5, ll. 62-67]: comparator output triggers when the sensed node reaches the maximum safety limit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the DC-DC converter of the established combination to utilize the high-precision auto-zeroed comparator to compare the power switch node against a predetermined maximum current threshold, as taught by Mednik, according to known methods. A POSITA would have been motivated to make this modification to provide reliable Over-Current Protection (OCP) for the DC-DC converter. Implementing Mednik’s maximum-current detection methodology ensures that the power switch is immediately inhibited if the current exceeds the safe rating of the inductor or switching components, preventing inductor saturation and thermal damage. Furthermore, a POSITA would recognize that utilizing the auto-zeroed comparator architecture (as taught by Ueno and Omran) to perform Mednik’s OCP function would predictably yield an accurate current-limit detector (KSR) against DC offset drift and temperature variations.
Ueno, in combination with Hanzawa, Berens, Omran, and Mednik are silent in regard to:
during the auto-zero phase, the input signal switch couples a supply voltage to each of the first and second input signals of the current comparator,
However, Chaput, further teaches:
during the auto-zero phase, the input signal switch couples a supply voltage to each of the first and second input signals of the current comparator (Figs. 26 & 27; [0146]: teaches shorting the first and second inputs (V+ and V-) of the comparator to a supply voltage VDD using zeroing switches (SWzero) during the reset/zero phase),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the DC-DC converter OCP comparator of Mednik to include the supply-voltage auto-zeroing phase taught by Chaput, according to known methods. A POSITA would have been motivated to make this modification to cancel inherent offset voltages in Mednik’s comparator prior to the over-current phase, while utilizing the supply voltage shorting technique of Chaput to ensure the comparator’s inputs are biased at a stable, predictable common-mode level that prevents false tripping and accommodates high-side voltage sensing, yielding predictable results (KSR).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ueno, in view Hanzawa, in view of Berens, in view of Omran, in view of Mednik, in view of Chaput, and in view of Pullen et al. (WO 2016/122913 A1, Pub. Date Aug. 4, 2016, hereinafter, Pullen).
Regarding dependent claim 15, Ueno, in combination with Hanzawa, Berens, and Omran are silent in regard to:
The DC-DC converter of claim 14, further comprising:
However, Mednik, further teaches:
The DC-DC converter of claim 14 ([Abstract]: utilizes a comparator within a switching DC-DC power converter), further comprising:
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the DC-DC converter of the established combination to utilize the high-precision auto-zeroed comparator to compare the power switch node against a predetermined maximum current threshold, as taught by Mednik, according to known methods. A POSITA would have been motivated to make this modification to provide reliable Over-Current Protection (OCP) for the DC-DC converter. Implementing Mednik’s maximum-current detection methodology ensures that the power switch is immediately inhibited if the current exceeds the safe rating of the inductor or switching components, preventing inductor saturation and thermal damage. Furthermore, a POSITA would recognize that utilizing the auto-zeroed comparator architecture (as taught by Ueno and Omran) to perform Mednik’s OCP function would predictably yield an accurate current-limit detector (KSR) against DC offset drift and temperature variations.
Ueno, in combination with Hanzawa, Berens, Omran, Mednik, and Chaput, are silent in regard to:
a replica circuit configured to replicate the PMOS transistor and the first internal circuit node of the power switch to provide the voltage indicative of the predetermined maximum current to the input signal switch.
However, Pullen, further teaches:
a replica circuit configured to replicate the PMOS transistor (Fig. 1; [0034], [0036] & [0040]: identifies the main high-side power transistor 140 as a PMOS device and teaches using a scaled replica FET 110 to mirror its characteristics) and the first internal circuit node of the power switch (Fig. 1; illustrates the replica FET 110 having its source connected to Vbat exactly like the PMOS 140, mirroring the internal node structure to establish an identical baseline for the Vds measurement, the replica circuit shares the common supply to mirror the voltage drop across the internal switching node) to provide the voltage indicative of the predetermined maximum current ([0004] & [0036]: teaches the replica PMOS to generate a reference voltage (Vds) that equals the voltage of the power switch at the predetermined current limit) to the input signal switch (Fig. 1; [0037] & [0039]: the generated limit voltage is routed to the switches that deed the comparator’s inputs, aligning with the OCP evaluation phase).
PNG
media_image6.png
835
1093
media_image6.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the DC-DC converter of the Mednik and Chaput combination to include the PMOS replica circuit taught by Pullen to generate the maximum current threshold, according to known methods. A POSITA would have been motivated to do so because utilizing a scaled replica transistor to generate the OCP reference voltage is a predictable method for ensuring the safety threshold tracks the process, voltage, and temperature (PVT) variations of the main PMOS power switch. As the on-resistance (Rds(on)) of the main PMOS fluctuates with temperature, the replica PMOS drifts identically, preventing false over-current tripping and ensuring the DC-DC converter operates safely at its maximum rated capacity under all environmental conditions, yielding predictable results (KSR).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUGO NAVARRO whose telephone number is (571)272-6122. The examiner can normally be reached Monday-Friday 08:30-5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUGO NAVARRO/ Examiner, Art Unit 2858 April 3, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 4/7/2026
Prosecution Insights