DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12, 19-20 and new claims 21-26, in the reply filed on 6/18/26 is acknowledged.
Applicant’s cancellation of non-elected claims 13-18 is acknowledged.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 10, 11, 19, 21, 22 and 24-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moens et al., US Patent No. 9,741,840 B1.
Moens anticipates:
1. An HEMT device comprising (see fig. 8):
a semiconductor body (102/106/122/124/142) having a semiconductive heterostructure (122/124/142);
a control region (144), comprising a semiconductor material, on the semiconductor body, the control region having a top surface and a plurality of lateral sides;
a control terminal (426), of conductive material, extending on and in contact (e.g. through intervening layers) with the top surface of the control region (144);
a passivation layer (162) of non-conductive material, extending on the semiconductor body, partially on the top surface of the control region (144) and on the plurality of lateral sides of the control region (e.g. on the lateral sides because coplanar), the passivation layer (162) arranged laterally and at a distance from the control terminal (426); and
a plurality of spacer regions (326) of non-conductive material, extending between the control terminal (426) and the passivation layer (162), the passivation layer (162) not overlapping the plurality of spacer regions (326). See Moens at col 1-14, ln 1–67, figs. 1-15.
2. The HEMT device according to claim 1, wherein the plurality of spacer regions (326) is thicker than the passivation layer (326), fig. 8
3. The HEMT device according to claim 2, wherein the control terminal (426) comprises a narrow portion (e.g. bottom T-shape), extending between the plurality of spacer regions (326) , and an upper portion (e.g. upper T-shape), extending on the plurality of spacer regions (326), fig. 8.
4. The HEMT device according to claim 2, further comprising an insulating structure (164/166) extending on the passivation layer (162), wherein a control opening (e.g. labeled 926 in fig. 9) extends in the insulating structure (164/166) and through the passivation layer (162) and accommodates, at least partially, the control terminal (426) and the plurality of spacer regions (326), the control opening (926) having lateral sides, the plurality of spacer regions (326) extending on the plurality of lateral sides of the control opening (926), fig.8.
5. The HEMT device according to claim 2, wherein the insulating structure (164/166) comprises:
a first insulating layer (164) extending on passivation layer, and
a second insulating layer (166) extending on the first insulating layer, and
wherein the control opening (926) extends through the first insulating layer (164) and the passivation layer (162) and accommodates the plurality of spacer regions (326) and, at least in part, the control terminal (426), the second insulating layer (166) extending on (e.g. the left and right sides of) the control terminal (426), fig. 8.
6. The HEMT device according to claim 4, wherein the insulating structure (164/166)comprises:
a first insulating layer (164) extending on passivation layer, and
a second insulating layer (166) extending on the first insulating layer, and
wherein the control opening (926) extends throughout the first and the second insulating layers and the passivation layer (162) and accommodates the plurality of spacer regions (326) and the control terminal (426), fig. 8.
10. The HEMT device according to claim 6, wherein the insulating structure (164/166) and the plurality of spacer regions (326) are of different, selectively etchable materials, col 6, ln 20–50 , col 7, ln 5–25.
Regarding claim 11:
Moens further teaches:
11. The HEMT device according to claim 10, wherein the plurality of spacer regions are of silicon nitride, col 7, ln 5–25.
Moens does not expressly teach the insulating structure is of silicon oxide.
However, it would have been obvious to one having ordinary skill in the art to form the insulating structure is of silicon oxide, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
19. A device, comprising (see fig. 8):
a semiconductor heterostructure (122/124/142);
a control region (144) on the heterostructure, the control region having a first surface (e.g. top surface) and a plurality of sides;
a terminal (426) on and in contact (e.g. through intervening layers) with the first surface of the control region (144);
a passivation layer (162) on the heterostructure, on the first surface (e.g. top surface) of the control region and on the plurality of sides of the control region (e.g. on the plurality of the sides because coplanar), the passivation layer (162) having a second surface (e.g. vertical surface) that is transverse to the first surface; and
a plurality of non-conductive spacer regions (326) between the terminal (426) and the passivation layer (162), the second surface (e.g. vertical surface) of the passivation layer (162) in contact with the plurality of spacer regions (326). See Moens at col 1-14, ln 1–67, figs. 1-15.
21. A device, comprising (see fig. 8):
a semiconductor body (102/106/122/124/142) with a first surface (e.g. top surface);
a gate region (144) on the first surface of the semiconductor body, the gate region having a first surface(e.g. top surface) opposite the first surface of the semiconductor body and a plurality of sidewalls;
a passivation layer (162) on the first surface of the semiconductor body, the first surface of the gate region (144), and the plurality of sidewalls of the gate region, (e.g. on the sidewalls because coplanar) the passivation layer (162) having a first gap (e.g. labeled 926 in fig. 9) on the first surface of the gate region;
a gate metal region (426) coupled to the gate region (144) through the first gap (926), the gate metal region (426) partially filling the first gap (926); and
a plurality of spacers (326) on the gate region (144) in the first gap (926), each of the plurality of spacers (326) extending between the passivation layer (162) and the gate metal region (144). See Moens at col 1-14, ln 1–67, figs. 1-15.
22. The device of claim 21, wherein the semiconductor body includes (102/106/122/124/142):
a substrate layer (102);
a channel layer (122, 142) on the substrate layer; and
a barrier layer (124) on the channel layer, the gate region (144) being directly on the barrier layer (124), fig. 8.
24. The device of claim 21, further comprising (see fig. 8) a first insulating layer (164) on the
passivation layer (162), the first insulating layer (164) having a second gap (926 in fig. 9) on the first surface of the gate region (144) aligned with the first gap (926 in fig. 9).
25. The device of claim 24, wherein (see fig.8) the first insulating layer (164) has a plurality of
sidewalls at the second gap (e.g. 926 in fig. 9) and the passivation layer (162) has a plurality of sidewalls at the first gap (e.g. 926 in fig. 9), the plurality of sidewalls of the first insulating layer being coplanar with respective sidewalls of the plurality of sidewalls of the passivation layer (e.g. coplanar in fig. 9).
26. The device of claim 24, wherein the gate metal region (426) includes a first portion (e.g. bottom T-shape) in the first and second gaps (926) and a second portion (e.g. top T-shape) extending onto the first insulating layer (164), the first insulating layer (164) and the passivation layer (162) separating the second portion (e.g. top T-shape) of the gate metal region from the gate region (144), fig. 8.
Claim(s) 1, 19, 21, 22 and 24-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang, US Publication No. 2022/0310824 A1.
Yang anticipates:
1. An HEMT device comprising (see fig. 6):
a semiconductor body (102/103/104/106/108) having a semiconductive heterostructure (103/104/106);
a control region (108), comprising a semiconductor material, on the semiconductor body, the control region having a top surface and a plurality of lateral sides;
a control terminal (122/132), of conductive material, extending on and in contact with the top surface of the control region;
a passivation layer (128) of non-conductive material, extending on the semiconductor body, partially on the top surface of the control region (108) and on the plurality of lateral sides of the control region, the passivation layer (128) arranged laterally and at a distance from the control terminal (122/132); and
a plurality of spacer regions (124) of non-conductive material, extending between the control terminal (122/132) and the passivation layer (128), the passivation layer not overlapping the plurality of spacer regions (e.g. top portions of 128 not overlap spacer regions 124). See Yang at para. [0001] – [0039], figs. 1-13.
19. A device, comprising (see fig. 6):
a semiconductor heterostructure (103/104/106;
a control region (108) on the heterostructure, the control region having a first surface (e.g. top surface) and a plurality of sides;
a terminal (122/132) on and in contact with the first surface of the control region;
a passivation layer (126 and/or 128) on the heterostructure, on the first surface of the control region (108) and on the plurality of sides of the control region, the passivation layer having a second surface (e.g. vertical surface) that is transverse to the first surface; and
a plurality of non-conductive spacer regions (124) between the terminal (122/132) and the passivation layer (126 and/or 128), the second surface (e.g. vertical surface) of the passivation layer (126 and/or 128) in contact (e.g. in direct contact or in contact through intervening layers) with the plurality of spacer regions (124). See Yang at para. [0001] – [0039], figs. 1-13.
21. A device, comprising (see fig. 6):
a semiconductor body (102/103/104/106/108) with a first surface (e.g. top surface);
a gate region (108) on the first surface of the semiconductor body, the gate region having a first surface opposite the first surface of the semiconductor body and a plurality of sidewalls;
a passivation layer (126 and/or 128) on the first surface of the semiconductor body, the first surface of the gate region, and the plurality of sidewalls of the gate region, the passivation layer having a first gap (e.g. labeled 130 in fig. 4) on the first surface of the gate region;
a gate metal region (122/132) coupled to the gate region (108) through the first gap (130), the gate metal region partially filling the first gap; and
a plurality of spacers (124) on the gate region (108) in the first gap (130), each of the plurality of spacers (124) extending between the passivation layer (126 and/or 128) and the gate metal region (122/132). See Yang at para. [0001] – [0039], figs. 1-13.
22. The device of claim 21, wherein the semiconductor body (102/103/104/106/108) includes:
a substrate layer (102);
a channel layer (104) on the substrate layer; and
a barrier layer (106) on the channel layer, the gate region (108) being directly on the barrier layer (106), fig. 6.
24. The device of claim 21, (e.g. In claim 21, the passivation layer is interpreted to be 126) further comprising a first insulating layer (128) on the passivation layer (126), the first insulating layer having a second gap (also 130) on the first surface of the gate region (108) aligned with the first gap (130), fig. 6.
25. The device of claim 24, wherein the first insulating layer (128) has a plurality of
sidewalls at the second gap (also 130) and the passivation layer has a plurality of sidewalls at the first gap (130), the plurality of sidewalls of the first insulating layer (128) being coplanar (e.g. portion of 126 is coplanar with 128) with respective sidewalls of the plurality of sidewalls of the passivation layer (126), fig. 6.
26. The device of claim 24, wherein the gate metal region (122/133) includes a first portion (e.g. bottom portion) in the first and second gaps (130) and a second portion (e.g. upper portion) extending onto the first insulating layer (128), the first insulating layer (128) and the passivation layer (126) separating the second portion (e.g. upper portion) of the gate metal region (122/133) from the gate region (108), fig. 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moen, as applied to claims 1 and 19 above, and further in view of Jones et al. ,US Publication No. 2021/0111254 (from the IDS).
Regarding claim 7:
Moen teaches all the limitations of claim 1 above, but does not expressly teach:
further comprising a field plate, the field plate being between the first insulating layer and the second insulating layer.
In an analogous art, Jones teaches:
(see fig. 1) further comprising a field plate (33), the field plate being between a first insulating layer (27) and a second insulating layer (28), para. [0058].
Regarding claim 8:
Moens further teaches:
8. The device of claim 7, further comprising a first current conducting terminal (622) and a second current conducting terminal (624), the first and second current conducting terminal being partially between the first insulating layer (164) and the second insulating layer (166), the first (622) and the second (624) current conducting terminal being in contact with the semiconductor body (102/106/122/124/142), fig. 8
Regarding claim 9:
Moens further teaches:
9. The device of claim 7, further comprising a first current conducting terminal (622) and a second (624) current conducting terminal, the first and second current conducting terminal being partially above the first insulating layer (164) and the second insulating layer (166), the first (622) and the second (624) current conducting terminal being in contact with the semiconductor body (102/106/122/124/142), the first current conducting terminal (622) being partially above the control terminal (e.g. upper portions of 622 is above the bottom of T-shape 426) and…
Moens does not expressly teach a field plate.
Jones teaches a field plate as applied to claim 7 above.
Because the first current conducting terminal (622) is disposed higher than the second insulating layer (166) in Moen’s fig. 8, one of ordinary skill in the art modifying Moen with Jones would form the first current conducting terminal (622) being partially above the field plate, as recited in the claim.
Regarding claim 20:
Moen teaches:
20. The device of claim 19, further comprising (see fig. 8):
a first insulating layer (164) on the passivation layer (162);
a second insulating layer (166) on the first insulating layer, the first insulating layer and the second insulating layer in contact with the plurality of spacer regions (326) at the second surface (e.g. vertical surface); and…
Moens does not expressly teach:
a field plate between the first and the second insulating layers.
Jones teaches a field plate as applied to claim 7 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Moens with the teachings of Jones to allow for reduction of gate-to-drain capacitance (Cgd) and trapping effects, as well as reduction in peak electric field proximate the drain electrode. See Jone at para. [0058].
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang, as applied to claim 21 above, and further in view of Tsai et al., US Publication No. 2016/0141404 A1.
Regarding claim 23:
Yang teaches all the limitations of claim 21 above and further teaches:
the channel layer and the barrier layer have a first conductivity type and the gate region has a second conductivity type, para. [0014] – [0018].
Yang is silent the second conductivity type is opposite the first conductivity type.
In an analogous art, Tsai teaches:
(see fig. 1) wherein a channel layer (104) and a barrier layer (112) have a first conductivity type (n-type) and a gate region (114) has a second conductivity type (p-type) opposite the first conductivity type, para. [0014] – [0016].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Moens with the teachings of Tsai because “The doping and material selected for the cap 114 partially sets the threshold voltage of the HEMT device (e.g., by raising the conduction band energy EC and reducing the conduction band to Fermi level energy). For example, dimensions and material properties can be adjusted to set the threshold voltage.” See Tsai at para. [0018].
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Yang, US 20220376100 A1. Yang teaches a HEMT device with spacers in figs. 10 and 12.
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
28 August 2026
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