DETAILED ACTION
This Office Action is in response to an application that was filed on 02/29/2024. Claims 1-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 15 recites the limitation phrase “one hole” in the limitation “wherein plating the at least one hole includes plating an upper end of the via that is filled”, is confusing. Specifically, the cited limitation is CONTRADICTING the STRUCTURE of base claim 14, where “one hole” is a limitation structure that is “spaced apart from the via”. Consequently, claim 15 does NOT identify ANOTHER “one hole” in the limitation, such as “wherein plating the at least another one hole includes plating an upper end of the via that is filled”, so as to differentiate “one hole” in the claim FROM “one hole” in claim 14.
Claims 16-18 are rejected since base claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
Claim 19 recites the limitation phrase “one hole” in the limitation “wherein the at least one hole is a power via for the PCB”, is confusing. Specifically, the cited limitation is CONTRADICTING the STRUCTURE of base claim 14, where “one hole” is a limitation structure that is “spaced apart from the via”. Consequently, claim 19 does NOT identify ANOTHER “one hole” in the limitation, such as “wherein the at least another one hole is a power via for the PCB”, so as to differentiate “one hole” in the claim FROM “one hole” in claim 14.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20070124930A1 and Cheng hereinafter), in view of Chen et al. (US20170318685A1 and Cheng hereinafter), and in further view of Luo (CN116939961A and Luo hereinafter).
Regarding claim 1, Cheng discloses a printed circuit board (Figs. 12-13 and ¶[0019-0020 & 0026] shows and indicates printed circuit board of Fig. 13), comprising: a laminated structure having an upper end and a lower end opposite to the lower end (items 100, 90 of Fig. 13 & item 50 of Figs. 12 & items 80, 82, 84 of Figs. 12-13 and ¶[0026] shows and indicates laminated structure 100 {assembly of multiple PCBs 50 into a single, multi-layer PCB 100 through sequential lamination of PCB layers 80, 82, 84} having upper end 90-upper-surface {upper surface of layer 90} and lower end 90-lower-suface {lower surface of layer 90} opposite to lower end 90-lower-suface), the laminated structure including: layers (items 80, 82, 84 of Figs. 12-13 and ¶[0026] shows and indicates layers 80-layers & 82-layers & 84-layers {PCB layers 80, 82, 84}); thin core layers (items 80, 82, 84 of Figs. 12-13 and ¶[0026] shows and indicates thin core layers 80-core & 82-core & 84-core {cores that are formed by PCB layers 80, 82, 84}); a via that are drilled (item 86 of Fig. 13 and claims 7_17 & ¶[0026] shows and indicates vias 86-upper & 86-lower {upper set of vias 86 and lower set of vias 86} that are drilled); a through hole extending from the upper end to the lower end, the through hole being plated (items 80, 84 of Figs. 12-13 and ¶[0006 & 0026] shows and indicates through hole 80-top-suface-to-84-bottom-surface {through hole that is formed from the top surface of PCB layers 80 to the bottom surface of PCB layer 84} extending from upper end 90-upper-surface to lower end 90-lower-suface; where through hole 80-top-suface-to-84-bottom-surface is plated {is interpreted, based on the plated walls of the via shown in dark line}); and a first plating on the lower end of the laminated structure, wherein the first plating covers a lower end of the via and is an outer power layer (item 84 of Figs. 12-13 & item 50 of Fig. 12 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates first plating 84-bottom-layer {bottom layer of PCB layers 84 that is plated, since PCB 50 is plated on both top and bottom surfaces, shown in dark line, as indicated in claims 1, 7, and 12} on lower end 90-lower-suface of laminated structure 100; and where first plating 84-bottom-layer will cover lower end 90-lower-suface of via 86-lower; and where first plating 84-bottom-layer is outer power layer 84-bottom-power-layer {PCB layer 84 contains power layers}).
Cheng discloses the claimed invention except to explicitly disclose a plurality of prepreg layers; wherein a via that is back-drilled and filled with a resinous material.
Chen discloses a plurality of prepreg layers (items 40, 42, 12, 30, 20 of Fig. 4 and ¶[0004 & 0027] shows and indicates the plurality of prepreg layers 40 & 42 {forming a stacked/lamination structure by having prepreg 40 adhesively bonding core structure 12 to core structure 30, and by having prepreg 42 adhesively bonding core structure 30 to core structure 20}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a plurality of prepreg layers into the structure of Cheng. One would have been motivated in the printed circuit board of Cheng and have the plurality of prepreg layers, in order to provide the adhesive to laminate the PCB layers that is indicated by Cheng in ¶[0026], where prepreg is used as an adhesive layer to bond discrete layers (PCB layers of core 80, PCB layers of core 82, and PCB layers of core 84) of multilayer PCB construction, as indicated by Chen in ¶[0004 & 0027], in the printed circuit board of Cheng.
However, Cheng and Chen do not disclose wherein a via that is back-drilled and filled with a resinous material.
Luo discloses wherein a via that is back-drilled and filled with a resinous material (items 41, 42, of Figs. 4a-4b & item 52 of Fig. 5 & items 61, 62 of Fig. 6a & items 64, 61 of Fig. 6b & item 1011 of Fig. 10 and ¶[n0044-n0046_n0048-n0049 & n0098] from Espacenet Translation shows and indicates where vias 62 are back-drilled 42 and filled with a resinous material {back drill hole 42 and the through hole 41 are filled with resin forming preset area 52 where the groove is to be opened and consequently having the groove area of groove 61 be removed by back drilling so as to avoiding the Cu holes in the vias 62 in the surface Cu 64 from being exposed in the groove 61 to eventually place electronic component 1011 within the groove}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein a via that is back-drilled and filled with a resinous material into the structure of modified Cheng. One would have been motivated in the printed circuit board of modified Cheng and have the via be back-drilled and filled with a resinous material, in order to design a PCB with a capable groove through back-drilling that can be removed (after being filled with resin) to optionally place an electronic component and avoid any Cu in the PCB vias that can be exposed in the removable groove, as indicated and shown by Luo in ¶[n0045-n0046 & n0048-n0049] and Figs. 9-10, in the printed circuit board of modified Cheng.
Regarding claim 2, modified Cheng discloses a printed circuit board, comprising a second plating on the upper end of the laminated structure, the second plating covering an upper end of the via (Cheng: item 80 of Figs. 12-13 & item 50 of Fig. 12 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates a second plating 80-top-layer {top layer of PCB layers 80 that is plated, since PCB 50 is plated on both top and bottom surfaces, shown in dark line, as indicated in claims 1, 7, and 12} on upper end 90-upper-surface of laminated structure 100; where second plating 80-top-layer will cover upper end 90-upper-surface of via 86-upper).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Chen and Luo, as detailed in the rejection of claim 1 above, in further view of Benedict et al. (US20240098898A1 and Benedict hereinafter).
Regarding claim 3, modified Cheng discloses a printed circuit board, wherein the through hole is a first through hole (Cheng: Fig. 13 and ¶[0006 & 0026] shows and indicates through hole 80-top-suface-to-84-bottom-surface is a first through hole).
However, Cheng, Chen, and Lou do not disclose wherein a first through hole, and the laminated structure further comprises: a second through hole extending from the upper end to the lower end, and the second through hole being plated.
Benedict discloses wherein a first through hole, and the laminated structure further comprises: a second through hole extending from the upper end to the lower end, and the second through hole being plated (items 120, 122, 100, 118, 102 of Fig. 1 and ¶[0020-0021] shows and indicates where first through hole 120 {plated through-hole power via 120}; and where laminated structure 100 {PCB 100} is further comprised of second through hole 122 {plated through-hole power via 122} extending from upper end 118-bottom-surface {bottom surface of bottom-surface layer 118} to lower end 102-top-surface {top surface of top-surface layer 102} and second through hole 122 being plated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein a first through hole, and the laminated structure further comprises: a second through hole extending from the upper end to the lower end, and the second through hole being plated into the structure of modified Cheng. One would have been motivated in the printed circuit board of modified Cheng and have the first through hole, and where the laminated structure is further comprised of the second through hole extending from the upper end to the lower end, and where the second through hole being plated, in order to design a PCB where the power vias pass power to components mounted on the top surface that is the lower end from the conductive trace connection from the power plane layer, as indicated and shown by Benedict in ¶[0020] and Fig. 1, in the printed circuit board of modified Cheng.
Regarding claim 4, modified Cheng discloses a printed circuit board, wherein the first through hole is a first power via, the second through hole is a second power via, and the first through hole is connected to the second through hole by the first plating (Cheng: Figs. 12-13 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates first plating 84-bottom-layer; Benedict: item 120 of Fig. 1 and ¶[0020-0021] shows and indicates where first through hole 120 is the first power via; and where second through hole 122 is the second power via; and where first through hole 120 is connected to second through hole 122 by the first layer 102 {top-surface layer 102}).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Chen, and in further view of Luo.
Regarding claim 7, Cheng discloses a printed circuit board (Figs. 12-13 and ¶[0019-0020 & 0026] shows and indicates printed circuit board of Fig. 13), comprising: a plurality of layers including layers and thin core layers (items 80, 82, 84 of Figs. 12-13 & item 100 of Fig. 13 & item 50 of Fig. 12 and ¶[0026] shows and indicates that printed circuit board of Fig. 13 is comprised of the plurality of layers 100-layers {layers of multi-layer PCB 100; where the assembly of multiple PCBs 50 is into a single, multi-layer PCB 100 through sequential lamination of PCB layers 80, 82, 84} including layers 80-layers & 82-layers & 84-layers {PCB layers 80, 82, 84} and thin core layers 80-core & 82-core & 84-core {cores that are formed by PCB layers 80, 82, 84}), the plurality of layers having an upper end and a lower end (item 90 of Fig. 13 & items 80, 82, 84 of Figs. 12-13 and ¶[0026] shows and indicates the plurality of layers 100-layers having upper end 90-upper-surface {upper surface of layer 90} and lower end 90-lower-suface {lower surface of layer 90}); a via that is formed in the plurality of layers and drilled, the via being filled material, the via having a first end and a second end opposite to the first end (items 86, 90 of Fig. 13 and claims 7_17 & ¶[0026] shows and indicates vias 86-upper & 86-lower {upper set of vias 86 and lower set of vias 86} that are drilled and is formed in the plurality of layers 100-layers and drilled; and where vias 86-upper & 86-lower being filled material {vias 86 are interpreted to be filled plating, based on the plated walls of the via shown in dark line}; and where via 86-upper has first end 86-upper-surface-90 {upper set of vias 86 that has the upper surface end of layer 90}; and where via 86-lower has second end 86-lower-surface-90 {lower set of vias 86 that has the lower surface end of layer 90} opposite to first end 86-upper-surface-90); a through hole formed in the plurality of layers, the through hole extending from the upper end to the lower end, the through hole being plated (items 80, 84 of Figs. 12-13 and ¶[0006 & 0026] shows and indicates through hole 80-top-suface-to-84-bottom-surface {through hole that is formed from the top surface of PCB layers 80 to the bottom surface of PCB layer 84} formed in the plurality of layers 100-layers; where through hole 80-top-suface-to-84-bottom-surface is extending from upper end 90-upper-surface to lower end 90-lower-suface; and where through hole 80-top-suface-to-84-bottom-surface is plated {is interpreted, based on the plated walls of the via shown in dark line}); a first outer plating on the upper end of the plurality of layers, the first outer plating covering the first end of the via; and a second outer plating on the lower end of the plurality of layers, and the second outer plating covering the second end of the via, wherein the second outer plating is an outer power layer (items 80, 84 of Figs. 12-13 & item 50 of Fig. 12 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates first outer plating 80-top-layer {top layer of PCB layers 80 that is plated, since PCB 50 is plated on both top and bottom surfaces, shown in dark line, as indicated in claims 1, 7, and 12} on upper end 90-upper-surface of the plurality of layers 100-layers; where first outer plating 80-top-layer covering first end 86-upper-surface-90 of via 86-upper; and where second outer plating 84-bottom-layer {bottom layer of PCB layers 84 that is plated, since PCB 50 is plated on both top and bottom surfaces, shown in dark line, as indicated in claims 1, 7, and 12} on lower end 90-lower-suface of the plurality of layers 100-layers; and where second outer plating 84-bottom-layer is covering second end 86-lower-surface-90 of via 86-lower; and where second outer plating 84-bottom-layer is outer power layer 84-bottom-power-layer {PCB layer 84 contains power layers}).
Cheng discloses the claimed invention except to explicitly disclose a plurality of prepreg layers; a via that is formed in the plurality of layers and back-drilled, the via being filled with a resinous material.
Chen discloses a plurality of prepreg layers (items 40, 42, 12, 30, 20 of Fig. 4 and ¶[0004 & 0027] shows and indicates the plurality of prepreg layers 40 & 42 {forming a stacked/lamination structure by having prepreg 40 adhesively bonding core structure 12 to core structure 30, and by having prepreg 42 adhesively bonding core structure 30 to core structure 20}).
However, Cheng and Chen do not disclose a via that is formed in the plurality of layers and back-drilled, the via being filled with a resinous material.
Luo discloses a via that is formed in the plurality of layers and back-drilled, the via being filled with a resinous material (items 41, 42, of Figs. 4a-4b & item 52 of Fig. 5 & items 61, 62 of Fig. 6a & items 64, 61 of Fig. 6b & item 1011 of Fig. 10 and ¶[n0039_n0044-n0046_n0048-n0049_n0053 & n0098] from Espacenet Translation shows and indicates where vias 62 that is formed in the plurality of layers are back-drilled 42 and filled with a resinous material {PCB board with multiple layers of copper lines are treated by back drill holes 42 and through holes 41 that are filled with resin forming preset area 52 where the groove is to be opened and consequently having the groove area of groove 61 be removed by back drilling so as to avoiding the Cu holes in the vias 62 in the surface Cu 64 from being exposed in the groove 61 to eventually place electronic component 1011 within the groove}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a via that is formed in the plurality of layers and back-drilled, the via being filled with a resinous material into the structure of modified Cheng. One would have been motivated in the printed circuit board of modified Cheng and have the via that is formed in the plurality of layers and then back-drilled, where the via is then filled with a resinous material, in order to design a PCB with a capable groove through back-drilling that can be removed (after being filled with resin) to optionally place an electronic component and avoid any Cu in the PCB vias that can be exposed in the removable groove, as indicated and shown by Luo in ¶[n0045-n0046 & n0048-n0049] and Figs. 9-10, in the printed circuit board of modified Cheng.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Chen and Luo, as detailed in the rejection of claim 7 above, in further view of Benedict.
Regarding claim 8, modified Cheng discloses a printed circuit board, wherein the through hole is a first through hole (Cheng: Fig. 13 and ¶[0006 & 0026] shows and indicates through hole 80-top-suface-to-84-bottom-surface is a first through hole).
However, Cheng, Chen, and Lou do not disclose wherein a first through hole, and the printed circuit board further comprises: a second through hole extending from the upper end to the lower end, and the second through hole is plated.
Benedict discloses wherein a first through hole, and the printed circuit board further comprises: a second through hole extending from the upper end to the lower end, and the second through hole is plated (items 120, 122, 100, 118, 102 of Fig. 1 and ¶[0020-0021] shows and indicates where first through hole 120 {plated through-hole power via 120}; and where printed circuit board 100 {PCB 100} is further comprised of second through hole 122 {plated through-hole power via 122} extending from upper end 118-bottom-surface {bottom surface of bottom-surface layer 118} to lower end 102-top-surface {top surface of top-surface layer 102} and second through hole 122 is plated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein a first through hole, and the printed circuit board further comprises: a second through hole extending from the upper end to the lower end, and the second through hole is plated into the structure of modified Cheng. One would have been motivated in the printed circuit board of modified Cheng and have the first through hole, and where the printed circuit board is further comprised of the second through hole extending from the upper end to the lower end, and where the second through hole being plated, in order to design a PCB where the power vias pass power to components mounted on the top surface that is the lower end from the conductive trace connection from the power plane layer, as indicated and shown by Benedict in ¶[0020] and Fig. 1, in the printed circuit board of modified Cheng.
Regarding claim 9, modified Cheng discloses a printed circuit board, wherein the first through hole is a first power via, the second through hole is a second power via, and the first through hole is connected to the second through hole by the second outer plating (Cheng: Figs. 12-13 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates second outer plating 84-bottom-layer; Benedict: item 120 of Fig. 1 and ¶[0020-0021] shows and indicates where first through hole 120 is the first power via; and where second through hole 122 is the second power via; and where first through hole 120 is connected to second through hole 122 by second outer layer 102 {top-surface layer 102}).
Claims 12, 14, 15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view Luo.
Regarding claim 12, Cheng discloses a method of manufacturing a printed circuit board (PCB) (Figs. 12-13 and ¶[0019-0020 & 0026] shows and indicates the method of manufacturing printed circuit board of Fig. 13), comprising steps of: selecting a plurality of layers (items 80, 82, 84 of Figs. 12-13 and ¶[0026] shows and indicates selecting the plurality of layers 80-layers & 82-layers & 84-layers {PCB layers 80, 82, 84}); laminating the plurality of layers to form a laminated structure (item 100 of Fig. 13 & item 50 of Figs. 12 & items 80, 82, 84 of Figs. 12-13 and ¶[0026] shows and indicates laminating the plurality of layers 80-layers & 82-layers & 84-layers to form laminated structure 100 {assembly of multiple PCBs 50 into a single, multi-layer PCB 100 through sequential lamination of PCB layers 80, 82, 84}); forming a via through the laminated structure (item 86 of Fig. 13 and ¶[0026] shows and indicates forming vias 86-upper & 86-lower {upper set of vias 86 and lower set of vias 86} through laminated structure 100); plating an upper surface of the laminated structure and an inner surface of the via (item 80 of Figs. 12-13 & item 50 of Fig. 12 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates plating upper surface 80-top-layer {top layer of PCB layers 80 that is plated, since PCB 50 is plated on both top and bottom surfaces, shown in dark line, as indicated in claims 1, 7, and 12} of laminated structure 100; and where plating the inner surface of vias 86-upper & 86-lower {plating the inner walls of vias 86 shown in dark line in Fig. 13}); filling the via with a material (Fig. 13 and ¶[0026] shows vias 86-upper & 86-lower are filled with plating material); and plating a lower surface of the laminated structure to form an outer power plane (item 84 of Figs. 12-13 & item 50 of Fig. 12 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates plating a lower surface 84-bottom-layer {bottom layer of PCB layers 84 that is plated, since PCB 50 is plated on both top and bottom surfaces, shown in dark line, as indicated in claims 1, 7, and 12} of laminated structure 100 to form outer power plane 84-bottom-power-layer {PCB layer 84 contains power layers}).
Cheng discloses the claimed method except to explicitly disclose wherein back-drilling the via.
Luo discloses wherein back-drilling the via (items 41, 42, of Figs. 4a-4b & item 52 of Fig. 5 & items 61, 62 of Fig. 6a & items 64, 61 of Fig. 6b & item 1011 of Fig. 10 and ¶[n0044-n0046_n0048-n0049 & n0098] from Espacenet Translation shows and indicates where vias 62 are back-drilled 42 {back drill hole 42 and the through hole 41 are filled with resin forming preset area 52 where the groove is to be opened and consequently having the groove area of groove 61 be removed by back drilling so as to avoiding the Cu holes in the vias 62 in the surface Cu 64 from being exposed in the groove 61 to eventually place electronic component 1011 within the groove}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein back-drilling the via into the method of Cheng. One would have been motivated in the method of manufacturing a printed circuit board of Cheng and have the via be back-drilled, in order for the method of design a PCB with a capable groove through back-drilling that can be removed (after being filled with resin) to optionally place an electronic component and avoid any Cu in the PCB vias that can be exposed in the removable groove, as indicated and shown by Luo in ¶[n0045-n0046 & n0048-n0049] and Figs. 9-10, in the method of manufacturing a printed circuit board of Cheng.
Regarding claim 14, modified Cheng discloses a method of manufacturing a printed circuit board, further comprises: after the step of back-drilling the via, drilling at least one hole through the laminated structure spaced apart from the via; and plating the at least one hole (Cheng: items 80, 84 of Figs. 12-13 and claims 7_17 & ¶[0026] is understood to show where the method is further comprised that after the step of drilling vias 86-upper & 86-lower, then drilling holes of through hole 80-top-suface-to-84-bottom-surface {through hole that is formed from the top surface of PCB layers 80 to the bottom surface of PCB layer 84} through laminated structure 100 spaced apart from vias 86-upper & 86-lower; and where holes of through hole 80-top-suface-to-84-bottom-surface are plated {as interpreted, based on the plated walls of the vias shown in dark line in Fig. 13}; Lou: Figs. 4a-4b_5_6a-6b_10 and ¶[n0044-n0046_n0048-n0049 & n0098] from Espacenet Translation shows and indicates where vias 62 are back-drilled 42).
Regarding claim 15, modified Cheng discloses a method of manufacturing a printed circuit board, wherein plating the at least another one hole includes plating an upper end of the via that is filled (Cheng: item 90 of Fig. 13 and ¶[0026] shows and indicates where plating the another one hole of via 86-upper will also include plating upper end 90-upper-surface {upper surface of layer 90} of via 86-upper that is filled).
Regarding claim 19, modified Cheng discloses a method of manufacturing a printed circuit board, wherein the at least another one hole is a via for the PCB (Cheng: item 90 of Fig. 13 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates where another one hole of via 86-lower for printed circuit board of Fig. 13).
Regarding claim 20, modified Cheng discloses a method of manufacturing a printed circuit board, wherein plating a lower surface of the laminated structure includes plating an entire lower surface of the laminated structure to form a continuous power plane (Cheng: item 90 of Fig. 13 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates where plating lower surface 84-bottom-layer of laminated structure 100 includes plating {plating shown in dark line in Fig. 13} the entire lower surface 84-bottom-layer of laminated structure 100 to form a continuous power plane).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Luo, as detailed in the rejection of claim 12 above, in further view of Chen.
Regarding claim 13, modified Cheng discloses a method of manufacturing a printed circuit board, wherein the plurality of layers includes multiple layers and multiple thin core layers (Cheng: items 80, 82, 84 of Figs. 12-13 and ¶[0026] shows and indicates where the method has the plurality of layers 80-layers & 82-layers & 84-layers includes multiple layers 80-layers & 82-layers & 84-layers {PCB layers 80, 82, 84}) and multiple thin core layers 80-core & 82-core & 84-core {cores that are formed by PCB layers 80, 82, 84}).
However, Cheng and Luo do not disclose wherein the plurality of layers includes multiple prepreg layers.
Chen discloses wherein the plurality of layers includes multiple prepreg layers (items 40, 42, 12, 30, 20 of Fig. 4 and ¶[0004 & 0027] shows and indicates where the plurality of layers of core structures 12 & 30 & 20 includes multiple prepreg layers 40 & 42 {forming a stacked/lamination structure by having prepreg 40 adhesively bonding core structure 12 to core structure 30, and by having prepreg 42 adhesively bonding core structure 30 to core structure 20}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the plurality of layers includes multiple prepreg layers into the method of modified Cheng. One would have been motivated in the method of manufacturing a printed circuit board of modified Cheng and have the plurality of layers include multiple prepreg layers, in order for the method to provide the adhesive to laminate the PCB layers that is indicated by Cheng in ¶[0026], where prepreg is used as an adhesive layer to bond discrete layers (PCB layers of core 80, PCB layers of core 82, and PCB layers of core 84) of multilayer PCB construction, as indicated by Chen in ¶[0004 & 0027], in the method of manufacturing a printed circuit board of modified Cheng.
Claims 16, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Luo, as detailed in the rejection of claim 15 above, in further view of Chen.
Regarding claim 16, modified Cheng discloses a method of manufacturing a printed circuit board, further comprising: adding another prepreg layer to the laminated structure (Cheng: items 80, 82, 84 of Figs. 12-13 and ¶[0026] shows and indicates where the method is further comprised of adding another layer 80-layers or 82-layers or 84-layers {PCB layers 80, 82, 84}) to laminated structure 100}).
However, Cheng and Lou do not disclose a prepreg layer.
Chen discloses a prepreg layer (items 40, 42, 12, 30, 20 of Fig. 4 and ¶[0004 & 0027] shows and indicates where the plurality of layers of core structures 12 & 30 & 20 includes prepreg layer 40 or 42 {forming a stacked/lamination structure by having prepreg 40 adhesively bonding core structure 12 to core structure 30, and by having prepreg 42 adhesively bonding core structure 30 to core structure 20}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a prepreg layer into the method of modified Cheng. One would have been motivated in the method of manufacturing a printed circuit board of modified Cheng and have the prepreg layer, in order for the method to provide the adhesive to laminate the PCB layers that is indicated by Cheng in ¶[0026], where prepreg is used as an adhesive layer to bond discrete layers (PCB layers of core 80, PCB layers of core 82, and PCB layers of core 84) of multilayer PCB construction, as indicated by Chen in ¶[0004 & 0027], in the method of manufacturing a printed circuit board of modified Cheng.
Regarding claim 17, modified Cheng discloses a method of manufacturing a printed circuit board, wherein plating a lower surface of the laminated structure to form an outer power plane includes plating a lower end of the via (Cheng: item 90 of Fig. 13 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates where plating a lower surface 84-bottom-layer of laminated structure 100 to form outer power plane 84-bottom-power-layer includes plating {plating shown in dark line in Fig. 13} the lower end 90-lower-suface {lower surface of layer 90} of via 86-lower).
Regarding claim 18, modified Cheng discloses a method of manufacturing a printed circuit board, wherein plating a lower surface of the laminated structure to form an outer power plane includes plating a lower surface of the laminated structure proximate to the at least another one hole (Cheng: item 90 of Fig. 13 and claims 1_7_12 & ¶[0023 & 0026] shows and indicates where plating a lower surface 84-bottom-layer of laminated structure 100 to form outer power plane 84-bottom-power-layer includes plating {plating shown in dark line in Fig. 13} the lower surface 84-bottom-layer of laminated structure 100 that is proximate to another one hole of via 86-lower).
Allowable Subject Matter
Claims 5-6 and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the primary reason for allowance is due to a printed circuit board, wherein the laminated structure includes an additional prepreg layer laminated thereon, the additional prepreg layer covers a lower end of each of the first through hole and the second through hole.
Regarding claim 6, the primary reason for allowance is due to the dependency on claim 5.
Regarding claim 10, the primary reason for allowance is due to a printed circuit board, wherein the plurality of layers are laminated together, and the printed circuit board further comprises: an additional prepreg layer laminated thereon, the additional prepreg layer covering a lower end of the first through hole and a lower end of the second through hole.
Regarding claim 11, the primary reason for allowance is due to the dependency on claim 10.
Conclusion
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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