Allowable Subject Matter
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Drawings
The drawings filed on 05/01/2024 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 02/29/2024 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-20 are is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lewandowski (US 2022/0020715).
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Regarding claims 13 and 20, Lewandowski discloses:
A substrate (1306, ¶0086) comprising:
a plurality of superconducting qubits or parts thereof (¶0016, ¶0036, ¶0086 taken together disclose substrate 1306 is a qubit chip comprising multiple qubit devices);
a plurality of contact pads (1308, ¶0087) formed of superconducting material (¶0087 discloses 1308 is formed from indium), each pad being electrically connected to one or more of the qubits or qubit parts (¶0087); and
a plurality of solder bumps comprising a superconducting solder material (1008, ¶0078 discloses the bumps are indium) and disposed on the plurality of contact pads (1308).
Regarding claims 14-18, Lweandowski does not disclose the claimed limitations. However, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product. In re Stephens 145 USPQ 656 (CCPA 1965). Therefore, the claimed limitations are considered met.
Regarding claim 19, Lewandowski further discloses:
a plurality of spacer bumps (608, ¶0090).
Allowable Subject Matter
Claims 1-12 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art does not disclose “conductive layer configured to conduct current in an electrodeposition process; producing a mask layer on the seed layer and patterning the mask layer to form openings therein, the surface area of the openings lying within respective exposed areas of the contact pads; removing the material of the seed layer from the bottom of the openings; thereafter, depositing the superconducting solder material by electrodeposition on the bottom of the respective openings, thereby forming the solder bumps; removing the mask layer; and after the electrodeposition, removing the seed layer and the protection layer” in combination with the remaining claimed features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899
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