DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed August 4, 2026 has been entered. Claims 1, 3-4, 6, 8, 11, 13, and 16-28 remain pending in this application. Claims 2, 5, 7, 9-10, 12, and 14-15 cancelled at applicant’s request. Claims 1, 6, and 11 have been amended. Claims 21-28 have been added. No new matter has been added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 6, 11, 16-20, and 27-28 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: Independent Claims 1, 6, and 11 each reference ‘package reliability’ without every clearly defining what is meant by the term. For instance, claim 1 explains package reliability is determined by a comparison of an initial state of the FBC and the thermal history output from the thermal history monitor, without every explaining how these elements are compared or what constitutes a favorable/unfavorable comparison. The specification is even more ambiguous, explaining only that package reliability is determined ‘based on thermal history’ (Specification, ¶[0009]). The specification further describes a usage proportion ‘with respect to the package reliability when the thermal history is less than the allowable value of the package reliability.’ (Specification, ¶[0031]). There is no explanation of units, formulae, or how the accumulated thermal history is converted into the usage proportion. This language is facially indefinite.
Dependent claims 16-20 and 27-28 rejected because they similarly reference the indefinite ‘package reliability.’
Remaining dependent claims 3-4, 8, 13, and 21-26 objected to for depending from a rejected independent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 6, 8, 11, 13, and 16-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,472,274 B2 to Anthony Fai, et al. (hereafter Fai) in view of US 2016/0179597 A1 to Sergey Anatolievich Gorobets, et al. (hereafter Gorobets) and further in view of US 2012/0268995 A1 to Akira Sugimoto, et al. (hereafter Sugimoto).
Regarding Amended Independent Claim 1, Fai discloses a semiconductor storage device (Memory 206: Fai, Figure 2) comprising:
a thermal history monitor (Thermal history monitor: Fai, col.1:26-34)
configured to output a thermal history (Outputting stored temperature data: Fai, col.11:38-40)
when a reliability detection command is input from a controller or a host device (Retrieving the thermal history of a cell as a result of receiving a command: Fai, col.11:38); and
a determination circuit (Processor 208: Fai, Figure 2) configured to determine package reliability
based on a comparison of:
(b) the thermal history output from the thermal history monitor (Writing data to multiple locations if temperature information exceeds a threshold level to improve reliability: Fai, col.13:31-39).
Fai does not disclose the thermal history monitor estimating the thermal history by using a relationship between an integrated time of a thermal stress and an increased amount of a Fail Bit Count (FBC) and further using a variation amount of the FBC. Gorobets, however, discloses a semiconductor memory device as in Claim 1, including a thermal history monitor configured to:
estimated using a relationship (Disclosing the relationship between thermal stress and data loss: Gorobets, ¶[0116]) between
an integrated time of a thermal stress applied on memory cells (Increased temperature: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
an increase amount of a Fail Bit Count (FBC) of the memory cells (Leading to data retention losses: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
further using a variation amount of the FBC (Tracking data retention losses over a period of time to estimate and predict thermal stress: Gorobets, ¶[0123]),
based on a comparison of:
(a) an initial state of the FBC (Recording the initial FBC for comparison: Gorobets, ¶[0164]; The predicted FBC shift being at least in part temperature related: Gorobets, ¶[0168]) recorded in a manufacturing step up to a multi-chip package (MCP) (Baseline measurements taken at the time of manufacture: Gorobets, ¶[0095]).
Gorobets discloses the relationship between temperature stress and increased Bit Error Rate is well known in the industry (Gorobets, ¶[0004]) and teaches tracking changes in the Bit Error Rate can more accurately track the effective temperature accelerated stress (Gorobets, ¶[0123]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the thermal stress tracking system of Gorobets with the thermal stress mitigation methods of Fai, with a reasonable expectation of success. Both inventions are well known in the field of thermal stress mitigation in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Fai and Gorobets disclose tracking the thermal stress experienced by a memory device and Fai goes on to disclose outputting an alarm when the thermal history is equal to or higher than the allowable value (Logging the exceeded temperature threshold data: Fai, col.13:59-63). They do not disclose determining the usage proportion of the package with respect to the package reliability when the thermal history is less than the allowable value of the package reliability.
Sugimoto, however, discloses a memory device wherein:
wherein the determination circuit is further configured to
determine whether the thermal history is equal to or higher than an allowable value of the package reliability (Using the thermal history to determine whether the thermal stress has exceeded the expected lifetime of the circuit: Sugimoto, ¶[0121]), and
to output an alarm when the thermal history is equal to or higher than the allowable value (Outputting a signal when the thermal exposure exceeds the guaranteed range: Sugimoto, ¶[0091]) and
a usage proportion of the package with respect to the package reliability when the thermal history is less than the allowable value of the package reliability (Predicting usable period from the history of thermal stress and current status: Sugimoto, ¶[0121]).
Sugimoto teaches these determinations allow the device to predict the remaining usable period for the memory device (Sugimoto, ¶[0121]). Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of this application, to combine the predictive logic of Sugimoto with the thermal stress tracking and mitigation techniques of Fai and Gorobets, with a reasonable expectation of success. All inventions were well known in the field of thermal stress management in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 3 and the substantially similar limitations of Claims 8 and 13, Fai discloses the semiconductor storage device according to claim 1, wherein
the thermal history includes the FBC at a predetermined read level (Indicating a thermal-related fail bit count exceeding a predetermined level: Fai, col.12:52-56; This read failure being incorporated into cell characteristics: Fai, col.12:28-29).
Regarding Amended Independent Claim 6, Fai discloses a memory system comprising:
a controller (Controller 204: Fai, Figure 2); and
a semiconductor storage device (Memory 206: Fai, Figure 2) that stores data based on control of the controller,
wherein the semiconductor storage device (Memory 206: Fai, Figure 2) has
a thermal history monitor (Thermal history monitor: Fai, col.1:26-34) configured to output a thermal history (Outputting stored temperature data: Fai, col.11:38-40)
when a reliability detection command is input from the controller or a host device (Retrieving the thermal history of a cell as a result of receiving a command: Fai, col.11:38), and
a determination circuit configured to determine package reliability
based on a comparison of:
(b) the thermal history output from the thermal history monitor (Writing data to multiple locations if temperature information exceeds a threshold level to improve reliability: Fai, col.13:31-39).
Fai does not disclose the thermal history monitor estimating the thermal history by using a relationship between an integrated time of a thermal stress and an increased amount of a Fail Bit Count (FBC) and further using a variation amount of the FBC. Gorobets, however, discloses a semiconductor memory device as in Claim 1, including a thermal history monitor configured to:
estimated using a relationship (Disclosing the relationship between thermal stress and data loss: Gorobets, ¶[0116]) between
an integrated time of a thermal stress applied on memory cells (Increased temperature: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
an increase amount of a Fail Bit Count (FBC) of the memory cells (Leading to data retention losses: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
initiated based on detecting a loss of linearity of the relationship (Teaching the error rate may not reflect a linear progression: Gorobets, ¶[0162]),
based on a comparison of:
(a) an initial state of the FBC (Recording the initial FBC for comparison: Gorobets, ¶[0164]; The predicted FBC shift being at least in part temperature related: Gorobets, ¶[0168]) recorded in a manufacturing step up to a multi-chip package (MCP) (Baseline measurements taken at the time of manufacture: Gorobets, ¶[0095]).
Gorobets discloses the relationship between temperature stress and increased Bit Error Rate is well known in the industry (Gorobets, ¶[0004]) and teaches tracking changes in the Bit Error Rate can more accurately track the effective temperature accelerated stress (Gorobets, ¶[0123]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the thermal stress tracking system of Gorobets with the thermal stress mitigation methods of Fai, with a reasonable expectation of success. Both inventions are well known in the field of thermal stress mitigation in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Fai and Gorobets disclose tracking the thermal stress experienced by a memory device and Fai goes on to disclose outputting an alarm when the thermal history is equal to or higher than the allowable value (Logging the exceeded temperature threshold data: Fai, col.13:59-63). They do not disclose determining the usage proportion of the package with respect to the package reliability when the thermal history is less than the allowable value of the package reliability.
Sugimoto, however, discloses a memory device wherein:
to determine
whether the thermal history is equal to or higher than an allowable value of the package reliability (Using the thermal history to determine whether the thermal stress has exceeded the expected lifetime of the circuit: Sugimoto, ¶[0121]), and
to output an alarm when the thermal history is equal to or higher than the allowable value (Outputting a signal when the thermal exposure exceeds the guaranteed range: Sugimoto, ¶[0091]) and
a usage proportion of the package with respect to the package reliability when the thermal history is less than the allowable value of the package reliability (Predicting usable period from the history of thermal stress and current status: Sugimoto, ¶[0121]).
Sugimoto teaches these determinations allow the device to predict the remaining usable period for the memory device (Sugimoto, ¶[0121]). Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of this application, to combine the predictive logic of Sugimoto with the thermal stress tracking and mitigation techniques of Fai and Gorobets, with a reasonable expectation of success. All inventions were well known in the field of thermal stress management in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Independent Claim 11, Fai discloses a method, comprising:
outputting a thermal history (Outputting stored temperature data: Fai, col.11:38-40)
when a reliability detection command is input from a controller or a host device (Retrieving the thermal history of a cell as a result of receiving a command: Fai, col.11:38); and
determining package reliability
based on a comparison of:
(b) the output thermal history (Writing data to multiple locations if temperature information exceeds a threshold level to improve reliability: Fai, col.13:31-39).
Fai does not disclose the thermal history monitor estimating the thermal history by using a relationship between an integrated time of a thermal stress and an increased amount of a Fail Bit Count (FBC) and further using a variation amount of the FBC. Gorobets, however, discloses a semiconductor memory device as in Claim 1, including a thermal history monitor configured to:
estimated using a relationship (Disclosing the relationship between thermal stress and data loss: Gorobets, ¶[0116]) between
an integrated time of a thermal stress applied on memory cells (Increased temperature: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
an increase amount of a Fail Bit Count (FBC) of the memory cells (Leading to data retention losses: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
further using a variation amount of the FBC (Tracking data retention losses over a period of time to estimate and predict thermal stress: Gorobets, ¶[0123]),
based on a comparison of:
(a) an initial state of the FBC (Recording the initial FBC for comparison: Gorobets, ¶[0164]; The predicted FBC shift being at least in part temperature related: Gorobets, ¶[0168]) recorded in a manufacturing step up to a multi-chip package (MCP) (Baseline measurements taken at the time of manufacture: Gorobets, ¶[0095]).
Gorobets discloses the relationship between temperature stress and increased Bit Error Rate is well known in the industry (Gorobets, ¶[0004]) and teaches tracking changes in the Bit Error Rate can more accurately track the effective temperature accelerated stress (Gorobets, ¶[0123]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the thermal stress tracking system of Gorobets with the thermal stress mitigation methods of Fai, with a reasonable expectation of success. Both inventions are well known in the field of thermal stress mitigation in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Fai and Gorobets disclose tracking the thermal stress experienced by a memory device and Fai goes on to disclose outputting an alarm when the thermal history is equal to or higher than the allowable value (Logging the exceeded temperature threshold data: Fai, col.13:59-63). They do not disclose determining the usage proportion of the package with respect to the package reliability when the thermal history is less than the allowable value of the package reliability.
Sugimoto, however, discloses a memory device wherein:
determining
whether the thermal history is equal to or higher than an allowable value of the package reliability (Using the thermal history to determine whether the thermal stress has exceeded the expected lifetime of the circuit: Sugimoto, ¶[0121]), and
to output an alarm when the thermal history is equal to or higher than the allowable value (Outputting a signal when the thermal exposure exceeds the guaranteed range: Sugimoto, ¶[0091]) and
a usage proportion of the package with respect to the package reliability when the thermal history is less than the allowable value of the package reliability (Predicting usable period from the history of thermal stress and current status: Sugimoto, ¶[0121]).
Sugimoto teaches these determinations allow the device to predict the remaining usable period for the memory device (Sugimoto, ¶[0121]). Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of this application, to combine the predictive logic of Sugimoto with the thermal stress tracking and mitigation techniques of Fai and Gorobets, with a reasonable expectation of success. All inventions were well known in the field of thermal stress management in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 16 and the substantially similar limitations of Claim 17, Gorobets discloses the semiconductor storage device according to claim 1, wherein
the determination circuit is configured to determine the package reliability further based on an allowable variation amount of the FBC for package reliability (The failed bit count approximated by multiple reads against optimal thresholds, implying allowable variations from pristine readings: Gorobets, ¶[0151]; FBC further determined including an allowable margin: Gorobets, ¶¶[0061-68]).
Regarding Claim 18 and the substantially similar limitations of Claims 19-20, Fai discloses the semiconductor storage device according to claim 1, wherein
the determination circuit is configured to determine the package reliability further by averaging a thermal history output from a plurality of the thermal history monitor (Using a variety of temperature readings from differing locations: Fai, Figure 4 and Fai, col.10:62-11:10; Or inferring the temperature through measurements taken at different times: Fai, col.11:11-22).
Regarding New Claim 21 and the substantially similar limitations of Claim 23, Sugimoto discloses the semiconductor storage device according to claim 1, wherein
the determination circuit is in the non-volatile memory (The sense amplifier circuit 126 making the determination: Sugimoto, ¶[0063]).
Regarding New Claim 22, Sugimoto discloses the memory system according to claim 6, wherein
the determination circuit is in the non-volatile memory different from the controller (The sense amplifier circuit 126 making the determination separate from the controller: Sugimoto, ¶[0063]).
Regarding New Claim 24 and the substantially similar limitations of New Claims 25 and 26, Sugimoto discloses the semiconductor storage device according to claim 1, wherein
the reliability detection command that is different from a read command or a write command (A request signal input separate from a read/write signal: Sugimoto, ¶[0062]) is input from the controller or the host device (The request signal coming from circuitry external to the memory device: Sugimoto, ¶[0062]).
Regarding New Claim 27, Fai discloses the memory system (Memory 206: Fai, Figure 2) according to claim 6, wherein
the semiconductor storage device includes a plurality of a non-volatile memory (The device containing semiconductor memory: Fai, col.15:21-29),
each of the plurality of the non-volatile memory includes the thermal history monitor (Thermal history monitor: Fai, col.1:26-34) and the determination circuit (Processor 208: Fai, Figure 2);
the thermal history monitor outputs the thermal history to the determination circuit based on a instruction of a control circuit (Retrieving the thermal history of a cell as a result of receiving a command: Fai, col.11:38),
the determination circuit determines whether the averaged thermal history is equal to or higher than the allowable value of the package reliability (Using the thermal history to determine whether the thermal stress has exceeded the expected lifetime of the circuit: Sugimoto, ¶[0121]).
Regarding New Claim 28, Fai discloses the memory system (Memory 206: Fai, Figure 2) according to claim 6, wherein
the controller includes the determination circuit (Processor 208: Fai, Figure 2);
the semiconductor storage device includes a plurality of a non-volatile memory (The device containing semiconductor memory: Fai, col.15:21-29),
each of the plurality of the non-volatile memory includes the thermal history monitor (Thermal history monitor: Fai, col.1:26-34);
a control circuit receives a thermal history from the thermal history monitor and outputs the thermal history to the memory controller (Retrieving the thermal history of a cell as a result of receiving a command: Fai, col.11:38),
the thermal history input to the memory controller is input to a determination circuit (The thermal history data being input to the determination circuit: Sugimoto, ¶[0063]),
the determination circuit averages the thermal history and determines whether the averaged thermal history is equal to or higher than the allowable value of the package reliability (Using the thermal history to determine whether the thermal stress has exceeded the expected lifetime of the circuit: Sugimoto, ¶[0121]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,472,274 B2 to Anthony Fai, et al. (hereafter Fai), US 2016/0179597 A1 to Sergey Anatolievich Gorobets, et al. (hereafter Gorobets), and US 2012/0268995 A1 to Akira Sugimoto, et al. (hereafter Sugimoto) in view of US 10,008,277 B2 to Liang Pang, et al. (hereafter Pang).
Regarding Claim 4, Fai discloses the semiconductor storage device according to Claim 1, but fails to include the further limitations of Claim 4. Pang, however, discloses a semiconductor storage device as in Claim 1, wherein the thermal history monitor is configured to
output the thermal history (Tracking the overall health of a memory cell, including temperature data retention effects: Pang, col.4:10-14) based on a characteristic variation of a select gate or a dummy gate (Through analysis of the health of dummy memory cells: Pang, col.4:24-26).
Pang teaches evaluating dummy memory cells, rather than the cells themselves, allows the evaluation to be performed at any time without interfering with the normal operation of the memory cells (Pang, col.4:26-29). Therefore, it would have been obvious, before the effective filing date of this application, to combine the dummy cell evaluation process of Pang with the thermal history tracking logic of Fai, with a reasonable expectation of success. Both inventions are well known in the field of data retention analysis and memory cell management, and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,331,377 B2 to Naveen Vittal Prabhu: Teaching evaluating the historical thermal condition of a NAND array in response to an operation request.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 08/31/2026
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