DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 28, 2026 has been entered.
Response to Amendment
The amendment filed March 30, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 1, 5-6, 10-11, and 15 have been amended. Claims 16-20 have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 6-8, 11-13, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,472,274 B2 to Anthony Fai, et al. (hereafter Fai) in view of US 2016/0179597 A1 to Sergey Anatolievich Gorobets, et al. (hereafter Gorobets).
Regarding Amended Independent Claim 1, Fai discloses a semiconductor storage device (Memory 206: Fai, Figure 2) comprising:
a thermal history monitor (Thermal history monitor: Fai, col.1:26-34)
configured to output a thermal history (Outputting stored temperature data: Fai, col.11:38-40)
when a reliability detection command is input from a controller or a host device (Retrieving the thermal history of a cell as a result of receiving a command: Fai, col.11:38); and
a determination circuit (Processor 208: Fai, Figure 2) configured to determine package reliability based on:
(b) the thermal history output from the thermal history monitor (Writing data to multiple locations if temperature information exceeds a threshold level to improve reliability: Fai, col.13:31-39).
Fai does not disclose the thermal history monitor estimating the thermal history by using a relationship between an integrated time of a thermal stress and an increased amount of a Fail Bit Count (FBC) and further using a variation amount of the FBC. Gorobets, however, discloses a semiconductor memory device as in Claim 1, including:
a thermal history monitor configured to estimate the thermal history using a relationship (Disclosing the relationship between thermal stress and data loss: Gorobets, ¶[0116]) between
an integrated time of a thermal stress applied on memory cells (Increased temperature: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
an increase amount of a Fail Bit Count (FBC) of the memory cells (Leading to data retention losses: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
further using a variation amount of the FBC (Tracking data retention losses over a period of time to estimate and predict thermal stress: Gorobets, ¶[0123]), and
the determination circuit configured to determine package reliability based on a comparison including:
(a) an initial state of the FBC (Recording the initial FBC for comparison: Gorobets, ¶[0164]; The predicted FBC shift being at least in part temperature related: Gorobets, ¶[0168]) recorded in a manufacturing step up to a multi-chip package (MCP) (Baseline measurements taken at the time of manufacture: Gorobets, ¶[0095]).
Gorobets discloses the relationship between temperature stress and increased Bit Error Rate is well known in the industry (Gorobets, ¶[0004]) and teaches tracking changes in the Bit Error Rate can more accurately track the effective temperature accelerated stress (Gorobets, ¶[0123]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the thermal stress tracking system of Gorobets with the thermal stress mitigation methods of Fai, with a reasonable expectation of success. Both inventions are well known in the field of thermal stress mitigation in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2 and the substantially similar limitations of Claims 7 and 12, Fai discloses the semiconductor storage device according to claim 1, wherein the determination circuit is configured to
determine whether the thermal history is equal to or higher than an allowable value of the package reliability (Determining that temperatures exceed a threshold value: Fai, col.13:31-32), and
output an alarm when the thermal history is equal to or higher than the allowable value (Logging the exceeded temperature threshold data: Fai, col.13:59-63).
Regarding Claim 3 and the substantially similar limitations of Claims 8 and 13, Fai discloses the semiconductor storage device according to claim 1, wherein
the thermal history includes the FBC at a predetermined read level (Indicating a thermal-related fail bit count exceeding a predetermined level: Fai, col.12:52-56; This read failure being incorporated into cell characteristics: Fai, col.12:28-29).
Regarding Independent Claim 6, Fai discloses a memory system comprising:
a controller (Controller 204: Fai, Figure 2); and
a semiconductor storage device (Memory 206: Fai, Figure 2) that stores data based on control of the controller,
wherein the semiconductor storage device (Memory 206: Fai, Figure 2) has
a thermal history monitor (Thermal history monitor: Fai, col.1:26-34) configured to output a thermal history (Outputting stored temperature data: Fai, col.11:38-40)
when a reliability detection command is input from the controller or a host device (Retrieving the thermal history of a cell as a result of receiving a command: Fai, col.11:38), and
the controller has a determination circuit configured to determine package reliability based on
(b) the thermal history output from the thermal history monitor (Writing data to multiple locations if temperature information exceeds a threshold level to improve reliability: Fai, col.13:31-39).
Fai does not disclose the thermal history monitor estimating the thermal history by using a relationship between an integrated time of a thermal stress and an increased amount of a Fail Bit Count (FBC) and further using a variation amount of the FBC. Gorobets, however, discloses a semiconductor memory device as in Claim 1, including including:
a thermal history monitor configured to estimate the thermal history using a relationship (Disclosing the relationship between thermal stress and data loss: Gorobets, ¶[0116]) between
an integrated time of a thermal stress applied on memory cells (Increased temperature: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
an increase amount of a Fail Bit Count (FBC) of the memory cells (Leading to data retention losses: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
initiated based on detecting a loss of linearity of the relationship (Teaching the error rate may not reflect a linear progression: Gorobets, ¶[0162]),
the determination circuit configured to determine package reliability based on a comparison including:
(a) an initial state of the FBC (Recording the initial FBC for comparison: Gorobets, ¶[0164]; The predicted FBC shift being at least in part temperature related: Gorobets, ¶[0168]) recorded in a manufacturing step up to a multi-chip package (MCP) (Baseline measurements taken at the time of manufacture: Gorobets, ¶[0095]).
Gorobets discloses the relationship between temperature stress and increased Bit Error Rate is well known in the industry (Gorobets, ¶[0004]) and teaches tracking changes in the Bit Error Rate can more accurately track the effective temperature accelerated stress (Gorobets, ¶[0123]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the thermal stress tracking system of Gorobets with the thermal stress mitigation methods of Fai, with a reasonable expectation of success. Both inventions are well known in the field of thermal stress mitigation in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 11, Fai discloses a method, comprising:
outputting a thermal history (Outputting stored temperature data: Fai, col.11:38-40)
when a reliability detection command is input from a controller or a host device (Retrieving the thermal history of a cell as a result of receiving a command: Fai, col.11:38); and
determining package reliability based on
(b) the output thermal history (Writing data to multiple locations if temperature information exceeds a threshold level to improve reliability: Fai, col.13:31-39).
Fai does not disclose the thermal history monitor estimating the thermal history by using a relationship between an integrated time of a thermal stress and an increased amount of a Fail Bit Count (FBC) and further using a variation amount of the FBC. Gorobets, however, discloses a semiconductor memory device as in Claim 1, including:
a thermal history monitor configured to estimate the thermal history using a relationship (Disclosing the relationship between thermal stress and data loss: Gorobets, ¶[0116]) between
an integrated time of a thermal stress applied on memory cells (Increased temperature: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
an increase amount of a Fail Bit Count (FBC) of the memory cells (Leading to data retention losses: Gorobets, ¶[0004]; Thermal stress directly contributing temperature accelerated stress time: Gorobets, ¶[0123]) and
further using a variation amount of the FBC (Tracking data retention losses over a period of time to estimate and predict thermal stress: Gorobets, ¶[0123]), and
the determination circuit configured to determine package reliability based on a comparison including:
(a) an initial state of the FBC (Recording the initial FBC for comparison: Gorobets, ¶[0164]; The predicted FBC shift being at least in part temperature related: Gorobets, ¶[0168]) recorded in a manufacturing step up to a multi-chip package (MCP) (Baseline measurements taken at the time of manufacture: Gorobets, ¶[0095]).
Gorobets discloses the relationship between temperature stress and increased Bit Error Rate is well known in the industry (Gorobets, ¶[0004]) and teaches tracking changes in the Bit Error Rate can more accurately track the effective temperature accelerated stress (Gorobets, ¶[0123]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the thermal stress tracking system of Gorobets with the thermal stress mitigation methods of Fai, with a reasonable expectation of success. Both inventions are well known in the field of thermal stress mitigation in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding New Claim 16 and the substantially similar limitations of New Claim 17, Gorobets discloses the semiconductor storage device according to claim 1, wherein
the determination circuit is configured to determine the package reliability further based on an allowable variation amount of the FBC for package reliability (The failed bit count approximated by multiple reads against optimal thresholds, implying allowable variations from pristine readings: Gorobets, ¶[0151]; FBC further determined including an allowable margin: Gorobets, ¶¶[0061-68]).
Regarding New Claim 18 and the substantially similar limitations of Claims 19-20, Fai discloses the semiconductor storage device according to claim 1, wherein
the determination circuit is configured to determine the package reliability further by averaging a thermal history output from a plurality of the thermal history monitor (Using a variety of temperature readings from differing locations: Fai, Figure 4 and Fai, col.10:62-11:10; Or inferring the temperature through measurements taken at different times: Fai, col.11:11-22).
Claim(s) 4, 9, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,472,274 B2 to Anthony Fai, et al. (hereafter Fai) and US 2016/0179597 A1 to Sergey Anatolievich Gorobets, et al. (hereafter Gorobets) in view of US 10,008,277 B2 to Liang Pang, et al. (hereafter Pang).
Regarding Claim 4 and the substantially similar limitations of Claims 9 and 14, Fai discloses the semiconductor storage device according to Claim 1, but fails to include the further limitations of Claim 4. Pang, however, discloses a semiconductor storage device as in Claim 1, wherein the thermal history monitor is configured to
output the thermal history (Tracking the overall health of a memory cell, including temperature data retention effects: Pang, col.4:10-14) based on a characteristic variation of a select gate or a dummy gate (Through analysis of the health of dummy memory cells: Pang, col.4:24-26).
Pang teaches evaluating dummy memory cells, rather than the cells themselves, allows the evaluation to be performed at any time without interfering with the normal operation of the memory cells (Pang, col.4:26-29). Therefore, it would have been obvious, before the effective filing date of this application, to combine the dummy cell evaluation process of Pang with the thermal history tracking logic of Fai, with a reasonable expectation of success. Both inventions are well known in the field of data retention analysis and memory cell management, and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 5, 10, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,472,274 B2 to Anthony Fai, et al. (hereafter Fai) and US 2016/0179597 A1 to Sergey Anatolievich Gorobets, et al. (hereafter Gorobets) in view of US 2011/0055468 A1 to Carlos J. Gonzalez, et al. (hereafter Gonzalez).
Regarding Amended Claim 5 and the substantially similar limitations of Claims 10 and 15, Fai discloses the semiconductor storage device according to claim 1, but fails to disclose the further limitations of Claim 5. Gonzalez, however, discloses a memory device as in Claim 1, wherein the determination circuit is further configured to
initialize data of the memory cells (Disclosing a scrub operation, including reading out data and rewriting to the same or a different location: Gonzalez, ¶[0016]) and
store the number of times of initialization (Tracking the number of times particular groups of memory cells need scrubbing: Gonzalez, ¶[0023]) when linearity of the characteristic variation of the memory cells is not obtained (Scrubbing cells when error counts fall outside the acceptable range: Gonzalez, ¶[0020]).
Gonzalez discloses these operations help maintain a high level of system performance while avoiding scrubbing operations that are unlikely to improve data integrity (Gonzalez, ¶[0017]). Therefore, it would have been obvious, before the effective filing date of this application, to combine the efficient data scrubbing method of Gonzalez with the thermal history tracking method of Fai, with a reasonable expectation of success. Both inventions are well known in the field of data retention analysis and memory cell management, and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,331,377 B2 to Naveen Vittal Prabhu: Teaching evaluating the historical thermal condition of a NAND array in response to an operation request.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 05/06/2026
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