Prosecution Insights
Last updated: July 17, 2026
Application No. 18/591,859

INTEGRATED MODULE HAVING A THERMAL NETWORK

Non-Final OA
Filed
Feb 29, 2024
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
721 granted / 850 resolved
+16.8% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
859
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
48.2%
+8.2% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 850 resolved cases

Prosecution Timeline

Feb 29, 2024
Application Filed
Apr 09, 2026
Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12667017
LIGHT EMITTING DEVICE MODULE AND DISPLAY APPARATUS HAVING THE SAME
2y 11m to grant Granted Jun 23, 2026
Patent 12666630
SEMICONDUCTOR DEVICE
2y 10m to grant Granted Jun 23, 2026
Patent 12667025
SEMICONDUCTOR MEMORY DEVICE
2y 1m to grant Granted Jun 23, 2026
Patent 12660722
POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN
3y 7m to grant Granted Jun 16, 2026
Patent 12660208
STORAGE WAFER AND MANUFACTURING METHOD OF STORAGE WAFER
3y 3m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+7.8%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 850 resolved cases by this examiner. Grant probability derived from career allowance rate.

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