Prosecution Insights
Last updated: April 19, 2026
Application No. 18/591,877

CURRENT SENSOR CIRCUIT WITH DIFFERENCE AMPLIFIER

Non-Final OA §102
Filed
Feb 29, 2024
Examiner
HOLLINGTON, JERMELE M
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
70%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
772 granted / 897 resolved
+18.1% vs TC avg
Minimal -16% lift
Without
With
+-15.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
22 currently pending
Career history
919
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
27.2%
-12.8% vs TC avg
§102
46.2%
+6.2% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 897 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 9, 13-15 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guedon et al (US PUB 2023/0275508 A1). PNG media_image1.png 569 867 media_image1.png Greyscale Regarding claim 1, Guedon et al disclose [see Fig. 12 above] a current sensor circuit comprising: a sensing resistor (sense resistor Rs1 & Rs2) having a first node [not numbered but shown as the connection point of the amplifier and sense resistor] adapted to [see Note below] be coupled to a high side terminal of a voltage supply (power source 19) and a second node [not numbered] adapted to [see Note below] be coupled to a high side terminal of a DUT (device under test) (load 18) [via switch block 27], wherein a low side terminal of the DUT (18) is coupled to a first ground node [shown but not numbered]; a difference amplifier (amplifiers 21 and 22) coupled to the first node and the second node of the sensing resistor (Rs1 and Rs2), wherein a low side power terminal of the difference amplifier (21 and 22) is coupled to a second ground node [not numbered but shown], and the second ground node is coupled to the high side terminal of the DUT (18); and an isolation DC (direct current)-to-DC converter (DC-Dc converter 12) having an output coupled to a high side power terminal of the difference amplifier (21 and 22). [Note: Claim limitations that employ phrases of the type “adapted to” are typical of claim limitations, which may not distinguish over the prior art. It has been held that the recitation that an element is “adapted to” perform a function is not a positive limitation but only requires the ability to so perform. See also MPEP 2111.04] Regarding claim 2, Guedon et al disclose wherein the first ground node and the second ground node [not numbered but shown as the connection point of the amplifier and sense resistor] are galvanically isolated. Regarding claim 3, Guedon et al disclose wherein the isolation DC-to-DC converter (12) is coupled to a third ground node [not numbered but shown as the connection point of the item 12 and power source 19] galvanically isolated from the first ground node and the second ground node. Regarding claim 9, Guedon et al disclose wherein the difference amplifier (21 and 22) is configured to output a sensed voltage that varies as a function of a current across the sensing resistor (Rs1 and Rs2). Regarding claim 13, Guedon et al disclose [see Fig. 12 above] a current sensor circuit comprising: a sensing resistor (sense resistor Rs1 & Rs2) having a first node [not numbered but shown as the connection point of the amplifier and sense resistor] adapted to [see Note below] be coupled to a high side terminal of a voltage supply (power source 19) and a second node [not numbered] adapted to [see Note below] be coupled to a high side terminal of a DUT (device under test) (load 18) [via switch block 27], wherein a low side terminal of the DUT (18) is coupled to a first ground node [shown but not numbered]; a difference amplifier (amplifiers 21 and 22) coupled to the first node and the second node of the sensing resistor (Rs1 and Rs2), wherein a low side power terminal of the difference amplifier (21 and 22) is coupled to a second ground node [not numbered but shown] that is galvanically isolated from the first ground node, and the second ground node is coupled to the high side terminal of the DUT (18), the difference amplifier (21 and 22) is configured to output a sensed voltage that varies as a function of a current across the sensing resistor (Rs1 and Rs2); and an isolation DC (direct current)-to-DC converter (DC-Dc converter 12) having an output coupled to a high side power terminal of the difference amplifier (21 and 22). [Note: Claim limitations that employ phrases of the type “adapted to” are typical of claim limitations, which may not distinguish over the prior art. It has been held that the recitation that an element is “adapted to” perform a function is not a positive limitation but only requires the ability to so perform. See also MPEP 2111.04] Regarding claim 14, Guedon et al disclose wherein the first ground node and the second ground node [not numbered but shown as the connection point of the amplifier and sense resistor] are galvanically isolated. Regarding claim 15, Guedon et al disclose wherein the isolation DC-to-DC converter (12) is coupled to a third ground node [not numbered but shown as the connection point of the item 12 and power source 19] galvanically isolated from the first ground node and the second ground node. Regarding claim 18, Guedon et al disclose a method for sensing current, the method comprising: sensing, by a difference amplifier (amplifier 21 and 22), a voltage drop across a sensing resistor (sense resistor Rs1 & Rs2) having a first node [not numbered but shown as the connection point of the amplifier and sense resistor] adapted to [see Note below] be coupled to a high side terminal of a voltage supply (power source 19) and a second node [not numbered] adapted to [see Note below] be coupled to a high side terminal of a DUT (device under test) (load 18) [via switch block 27], wherein a low side terminal of the DUT (18) is coupled to a first ground node [shown but not numbered]; the difference amplifier (21 and 22) coupled to the first node and the second node of the sensing resistor (Rs1 and Rs2), wherein a low side power terminal of the difference amplifier (21 and 22) is coupled to a second ground node [not numbered but shown], and the second ground node is coupled to the high side terminal of the DUT (18); and outputting, by the difference amplifier (21 and 22), a sensed voltage that varies as a function of a current across the sensing resistor (Rs1 and Rs2) in response to receiving an isolated voltage at a high side power terminal of the difference amplifier (21 and 22) provided from an isolation DC (direct current)-to-DC converter (DC-DC converter 12). [Note: Claim limitations that employ phrases of the type “adapted to” are typical of claim limitations, which may not distinguish over the prior art. It has been held that the recitation that an element is “adapted to” perform a function is not a positive limitation but only requires the ability to so perform. See also MPEP 2111.04] Regarding claim 19, Guedon et al disclose wherein the first ground node and the second ground node [not numbered but shown as the connection point of the amplifier and sense resistor] are galvanically isolated. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 for details. Allowable Subject Matter Claims 4-8, 10-12, 16-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: regarding claim 4, the primary reason for the allowance of the claim is due to an isolation ADC (analog-to-digital converter) coupled to an output of the difference amplifier. Since claims 5-8 depend from claim 4, they also have allowable subject matter. Regarding claim 10, the primary reason for the allowance of the claim is due to wherein the voltage supply is configured to supply a voltage of at least 400 volts on the high side terminal of the voltage supply. Since claim 11 depends from claim 10, it also has allowable subject matter. Regarding claim 12, the primary reason for the allowance of the claim is due to wherein the voltage supply is configured to supply a voltage of at least 1500 volts on the high side terminal of the voltage supply. Regarding claim 16, the primary reason for the allowance of the claim is due to an isolation ADC (analog-to-digital converter) configured to receive the sensed voltage from the difference amplifier and to output a digital value characterizing the current across the sensing resistor. Regarding claim 17, the primary reason for the allowance of the claim is due to wherein the voltage supply is configured to supply a voltage of at least 400 volts on the high side terminal of the voltage supply, and there is a voltage drop of about 5 volts or less between the first node and the second node. Regarding claim 20, the primary reason for the allowance of the claim is due to receiving, at an isolation ADC (analog-to-digital converter) the sensed voltage from the difference amplifier; and outputting, by the isolation ADC, a digital value characterizing the current across the sensing resistor. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERMELE M HOLLINGTON whose telephone number is (571)272-1960. The examiner can normally be reached Mon-Fri 7:00am-3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee E Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JERMELE M HOLLINGTON/ Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Feb 29, 2024
Application Filed
Dec 23, 2025
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12592561
MULTICHANNEL TEST SYSTEM WITH GALVANIC COUPLING OF INTERMEDIATE CIRCUITS, AND METHOD FOR GALVANICALLY COUPLING INTERMEDIATE CIRCUITS
2y 5m to grant Granted Mar 31, 2026
Patent 12591028
RESISTIVE ELECTROMAGNET SYSTEMS AND METHODS
2y 5m to grant Granted Mar 31, 2026
Patent 12584958
ELECTRONICS TESTER
2y 5m to grant Granted Mar 24, 2026
Patent 12584959
SIGNAL PROCESSING METHOD AND ABNORMAL SOUND DETECTION SYSTEM
2y 5m to grant Granted Mar 24, 2026
Patent 12571835
METHOD OF INSPECTING TEMPERATURE CONTROLLING SYSTEM
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
70%
With Interview (-15.9%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 897 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month