DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) reading a data segment from one memory location into a temporary storage (“registry”),
setting an “indicator” to change a location’s status from “unread” to “read,”
determining/using a destination memory location based on its status, and
writing the data to the destination.
. This judicial exception is not integrated into a practical application because all of the above limitations encompass steps that a person would perform when manipulating, organizing and moving data within memory and each step can be practically be performed in the mind as a mental step. This amounts to manipulating and organizing information (data movement/housekeeping) by labeling locations with statuses and copying data accordingly. Courts have characterized similar information manipulation/organization as abstract ideas. See, e.g., Electric Power Group, 830 F.3d at 1353–54 (collecting/analyzing information is abstract). Nothing in the claim precludes the steps of manipulating organizing and moving data from being performed in the human mind as mental steps grouping abstract ideas - that is, directed to a judicial exception under Prong 1 of Step 2A.
Because the claim is recites a judicial exception, Prong 2 of Step 2A determines whether the recited judicial exception is integrated into a practical application. For example, a claim may integrate the exception into a practical application if an additional element reflects an improvement in the functions of a computer, or an improvement to other technology or technical field.
Though the claim recites a “processor,” “one or more circuits,” a “system,” a “registry,” and an “indicator,” without specifying any particular hardware implementation or specific improvement to computer functionality. The steps (read, set, determine, write) are recited at a high level of generality and are result-oriented i.e., as a generic system performing generic computer functions of reading, setting, determining and writing. These additional elements, considered in the context of reading, setting, determining and writing as a whole, do not integrate the abstract idea into a practical application. Rather, these additional limitations merely use a computer (server, a user device) to perform generic computer activity, reading, setting, determining and writing. Such elements are not sufficient to integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Accordingly, claim 1 is not integrated into a practical application.
Under Step 2B, claim 1 does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional computer elements, which are recited at a high level of generality, provide conventional computer functions that do not add meaningful limits to practicing the abstract idea. The additional elements—“processor,” “one or more circuits,” “registry,” “indicator,” “memory location”—are generic computing components performing routine functions (reading/writing memory, setting a status/flag, and making a determination). Implementing an abstract idea on a generic computer does not supply an inventive concept as recited does not provide any requisite of what the system comprises and how its components achieve the reading, setting, determining and writing. The claims as drafted do not recite unconventional hardware, a specific atomic operation, a defined per-chunk flag array, or a non-conventional data structure/algorithm that would transform the nature of the claim into a patent-eligible application.
Accordingly, the additional limitations, considered individually and in combination, do not provide an inventive concept.
Examiner notes that the Applicant’s preamble does not afford patentable weight to the Applicant’s claims because this claim’s preamble is not “necessary to give life, meaning, and vitality” to the claim.
The dependent claims corresponding to the rejected claims 9, 21 and 27 do not include language that would preclude the steps of categorizing and updating, of claims 9, 21 and 27 from practically being performed in the human mind, nor with respect to the individual claims. Further limitations do not integrate into a practical application. The claims do not include additional elements that are sufficient to amount to significantly more than the abstract idea because the additional computer elements, which are recited at a high level of generality, provide conventional computer functions that do not add meaningful limits to practicing the abstract idea.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 21 and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Per claims 9 and 21, the limitation “determine a destination memory location for the first data segment is a second read memory location.” is ungrammatical and ambiguous. The construction is ungrammatical and indefinite. It is unclear whether the limitation requires (i) determining that the destination “is” of a certain status, or (ii) determining the destination memory location, “the destination memory location being a second read memory location.” The grammatical defect prevents a POSITA from ascertaining the scope with reasonable certainty.
The phrases “unread memory location,” “first read memory location,” “second read memory location, and “indicator”” in claim 9 are relative terms which renders the claim indefinite. The phrases ““unread memory location,” “first read memory location,” “second read memory location, and “indicator””” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The claims do not define “unread”/“read” or provide an objective mechanism for how a memory location’s status is determined or changed (e.g., via a status bit/flag). Without reciting the status criterion or its representation, these are relative/functional labels lacking clear boundaries.
“Indicator”: The claim does not identify whether the “indicator” is a flag bit, a field in a descriptor, a table entry, etc., or how it relates to the “unread/read” status. The breadth and ambiguity of “indicator” render the limitation indefinite.
Per claim 27, the limitations: “read a first data segment into a registry from an unread memory location, set an indicator to change the unread memory location to a first read memory location, and … write the first data segment … to a second read memory location.” are not defined structurally or functionally beyond a result (“change … to a … read memory location”).
The claim writes to “a second read memory location” without stating how that location is selected or identified within the system; absent a determinative criterion or a prior determination step (which appears only in dependent claim 28), the scope is ambiguous as to the required “second read memory location.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9-12, 14, and 21-24, 27-31 and 34 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bourd et al 20130194286 herein Bourd.
Per claim 9, Bourd discloses: one or more circuits to: read a first data segment into a registry from an unread memory location; (fig. 4, ¶0120; PMU 18 may store state information of buffers 22 within IC 12 (e.g., within registers 44). PMU 18 may receive such state information of buffers 22 from processor 14. The state information of buffers 22 may include one or more of a starting address of buffers 22, an ending address of buffers 22, an address within buffers 22 where produced data is to be stored, and an address within buffers where data is to be retrieved. In these examples, PMU 18 may determine the location within the buffer for where the data produced by the execution of the first thread is to be stored based on the stored state information of buffers 22. Moreover, in some examples, PMU 18 may determine the location within the buffer for where the data produced by the execution of the first thread is to be stored without the first thread indicating the location of where the data is to be stored in the buffer; the examiner notes that the unread memory location is interpreted as not being accessed or not under atomic control by another thread. i.e. having access) set an indicator to change the unread memory location to a first read memory location; (¶0101; PMU 18 may store an atomic counter within registers 44. Registers 44 may be part of cache 34, or part of some other memory within GPU 16 or IC 12. The atomic counter may indicate whether access for one of programmable compute units 28 is available (e.g., whether data is available to be read or whether two or more kernels are attempting to write or read at the same time from the same buffers 22). Based on the atomic counter, PMU 18 may be able to properly allow access to one of programmable compute units 28 while denying access to other ones of programmable compute units 28 to avoid data corruption of buffers 22, which may occur if two threads attempt to write data at the same time; the examiner interprets the limitation as setting the indicator to indicate usage) determine a destination memory location for the first data segment is a second read memory location; and write the first data segment from the registry to the second read memory location (¶0102; PMU 18 may determine the starting and ending location of the requested data. However, PMU 18 may retrieve additional data that is stored in buffers 22 after the determined ending location of the requested data. PMU 18 may retrieve such additional data when PMU 18 determines that storage space is available in buffers 36. As described above, PMU 18 may manage both buffers 22 in global memory 20, as well as buffers 36 within cache 34. PMU 18 may then store the retrieved data in cache 34. In this manner, the additional data is already available within GPU 16 when such data is needed).
Per claim 10, Bourd discloses: wherein two or more workers execute, in parallel, to read the unread memory location and the second read memory location (¶0101; The atomic counter may indicate whether access for one of programmable compute units 28 is available (e.g., whether data is available to be read or whether two or more kernels are attempting to write or read at the same time from the same buffers 22). Based on the atomic counter, PMU 18 may be able to properly allow access to one of programmable compute units 28 while denying access to other ones of programmable compute units 28 to avoid data corruption of buffers 22, which may occur if two threads attempt to write data at the same time; See ¶0026; parallel threads executing).
Per claim 11, Bourd discloses: wherein the destination memory location is determined based at least on an updated data object to be added to a memory buffer (¶0076; after a programmable compute unit, executing threads of a kernel, produces data and outputs the produced data, PMU 18 may receive the data, and determine the address for where the data is to be stored. For example, PMU 18 may determine in which one of buffers 22 to store the data. In examples where buffers 22 are ring buffers or FIFO buffers, PMU 18 may store the information for the pointers that identify the start and end of buffers 22. For ring buffers, PMU 18 may also store the information for pointers that identify start of valid data and the end of valid data; parallel threads executing; the examiner notes that the data object is merely graphics data).
Per claim 12, Bourd discloses: wherein the one or more circuits are further to: determine a second destination memory location for a second data segment read from the second memory location; determine the second destination memory location is unread; read a third data segment from the second destination memory location; set a second indicator to change the second destination memory location into a third read memory location; and write the second data segment from the registry to the third read memory location (¶0101; Based on the atomic counter, PMU 18 may be able to properly allow access to one of programmable compute units 28 while denying access to other ones of programmable compute units 28 to avoid data corruption of buffers 22, which may occur if two threads attempt to write data at the same time. In some instances, when PMU 18 denies access to one of programmable compute units 28, PMU 18 may allow the task that request the access (e.g., a thread) to go to sleep, and allow the denied one of programmable compute units 28 to continue executing other tasks (e.g., threads). When access to the denied one of programmable compute units 28 becomes available, PMU 18 may awaken that task and provide the data to that task for further execution. In this way, programmable compute units 28 may not go completely idle, and other tasks of programmable compute units 28 may execute; the examiner notes that the claim is merely an iteration process of acquiring access to read from multiple threads).
Per claim 13, Bourd discloses: wherein the one or more circuits are further to: determine a second destination memory location for a second data segment read from the second memory location; determine the second destination memory location is unread; read a third data segment from the second destination memory location; set a second indicator to change the second destination memory location into a third read memory location; and write the second data segment from the registry to the third read memory location (¶0101; Based on the atomic counter, PMU 18 may be able to properly allow access to one of programmable compute units 28 while denying access to other ones of programmable compute units 28 to avoid data corruption of buffers 22, which may occur if two threads attempt to write data at the same time. In some instances, when PMU 18 denies access to one of programmable compute units 28, PMU 18 may allow the task that request the access (e.g., a thread) to go to sleep, and allow the denied one of programmable compute units 28 to continue executing other tasks (e.g., threads). When access to the denied one of programmable compute units 28 becomes available, PMU 18 may awaken that task and provide the data to that task for further execution. In this way, programmable compute units 28 may not go completely idle, and other tasks of programmable compute units 28 may execute; the examiner notes that the claim is merely an iteration process of acquiring access to read from multiple threads).
Per claim 14, Bourd discloses: wherein the one or more circuits are further to: determine a second destination memory location for a second data segment read from the second memory location; determine the second destination memory location is unread; read a third data segment from the second destination memory location; set a second indicator to change the second destination memory location into a third read memory location; and write the second data segment from the registry to the third read memory location (¶0124; Examples of device 10 include, but are not limited to, wireless devices, mobile telephones, personal digital assistants (PDAs), video gaming consoles that include video displays, mobile video conferencing units, laptop computers, desktop computers, television set-top boxes, tablet computing devices, e-book readers, and the like. Device 10 may include processor 14, GPU 16, global memory 20, display 68, user interface 70, and transceiver module 72. In the illustrated example, PMU 18 is formed within GPU 16. In some examples, PMU 18 may be formed within the same IC that houses GPU 16 (i.e., IC 12). Also as illustrated, GPU 16 resides within IC 12. However, processor 14 may also reside within IC 12; the edge device is interpreted as any computing device on a network).
Claims 21-24 are the method claims corresponding to the processor claims 9-13 and are rejected under the same reasons set forth in connection with the rejection of claims 9-13.
Claims 27-31 and 34 are the system claims corresponding to the processor claims 9-13 and 14 and are rejected under the same reasons set forth in connection with the rejection of claims 9-13 ad 14.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13, 25-26, 32-33 and is/are rejected under 35 U.S.C. 103 as being unpatentable over Bourd in view of Hakke Patel et al. 20230196677 herein Patel.
Per claim 13, Bourd does not specifically disclose: wherein the one or more circuits are further to: determine a total number of data segments for a task; and determine a number of processing units to execute the task based on the total number of data segments.
However, Patel discloses: wherein the one or more circuits are further to: determine a total number of data segments for a task; and determine a number of processing units to execute the task based on the total number of data segments (¶0213; In at least one embodiment, scheduler unit 2404 receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2400. In at least one embodiment, scheduler unit 2404 schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit 2404 manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from a plurality of different cooperative groups to various functional units (e.g., processing cores 2410, SFUs 2412, and LSUs 2414) during each clock cycle).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Bourd and Patel’s task distribution to achieve parallel processing. Patel efficiently uses the processors bandwidth (¶0150; allowing partition units 1720A-1720N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory 1722).
Claim 25 is the method claim corresponding to the processor claim 13 and is rejected under the same reasons set forth in connection with the rejection of claim 13.
Claim 32 is the system claim corresponding to the processor claim 13 and is rejected under the same reasons set forth in connection with the rejection of claim 13.
Per claim 26, Bourd discloses: determining a number of contiguous portions for a new data object; determining an existing number of contiguous portions is less than the number; and selecting the destination memory location based at least on the number, wherein the destination memory location forms the number of contiguous portions for the new data object (¶0213; In at least one embodiment, scheduler unit 2404 receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2400. In at least one embodiment, scheduler unit 2404 schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit 2404 manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from a plurality of different cooperative groups to various functional units (e.g., processing cores 2410, SFUs 2412, and LSUs 2414) during each clock cycle; the examiner notes that the claims nor the specification set forth the metes and bounds of the contiguous portions and the portion being less than a number. In the interest of compact prosecution, the examiner interprets the claim as a collection of threads similarly to Warps).
Claim 33 is the system claim corresponding to the processor claim 26 and is rejected under the same reasons set forth in connection with the rejection of claim 26.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Prosecution Insights