DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B, claims 1-7 and 12-19, in the reply filed on June 12, 2026 is acknowledged.
Accordingly, claims 8-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 12, 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 29, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on April 21, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilhelm et al (US Patent 5, 543,994) in view of Schoofs et al (US Patent 5,412,234).
In re claim 1, Wilhelm et al discloses a gate driver circuit (i.e. see at least Figure 2), comprising: a low side part configured to output a first gate drive signal between a first gate output and a first reference potential (i.e. see at least column 1, lines 5-47, when referring to the typical gate driver IR2110 and having a high side island); a high side part (i.e. see at least Figures 2 and 3) configured to generate a high side data signal (i.e. 32) and to output a second gate drive signal between a second gate output (i.e. OUT) and a second reference potential (i.e. VS); and a p-type structure (i.e. Q3) configured to pass the high side data signal to the low side part (i.e. FLT).
Wilhelm et al does not explicitly disclose a junction transistor.
However, Schoofs et al discloses the use of JFETs (i.e. see at least Figure 1: T3).
The advantage is to obtain a configuration that occupies less space while the properties such as breakdown voltage and low parasitic currents the same (i.e. see at least column 2, lines 26-30).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the gate driver circuit as taught by Wilhelm et al with the use of JFETs in order to obtain a configuration that occupies less space while the properties such as breakdown voltage and low parasitic currents the same.
In re claim 2, Wilhelm et al discloses wherein a hole current through the p-type structure is controllable (i.e. see at least Figure 2: through switches, etc.).
Wilhelm et al does not explicitly disclose a junction transistor.
However, Schoofs et al discloses the use of JFETs (i.e. see at least Figure 1: T3).
The advantage is to obtain a configuration that occupies less space while the properties such as breakdown voltage and low parasitic currents the same (i.e. see at least column 2, lines 26-30).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the gate driver circuit as taught by Wilhelm et al with the use of JFETs in order to obtain a configuration that occupies less space while the properties such as breakdown voltage and low parasitic currents the same.
In re claim 3, Wilhelm et al discloses wherein a controlled path of the p-type structure is electrically connected between the high side part and the low side part (i.e. see at least Figure 2).
Wilhelm et al does not explicitly disclose a junction transistor.
However, Schoofs et al discloses the use of JFETs (i.e. see at least Figure 1: T3).
The advantage is to obtain a configuration that occupies less space while the properties such as breakdown voltage and low parasitic currents the same (i.e. see at least column 2, lines 26-30).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the gate driver circuit as taught by Wilhelm et al with the use of JFETs in order to obtain a configuration that occupies less space while the properties such as breakdown voltage and low parasitic currents the same.
Allowable Subject Matter
Claims 4-7 and 12-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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