CTNF 18/592,004 CTNF 81465 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim s 8 and 14 are objected to because of the following informalities: in claim 8, line 2, remove the extraneous word “to” for proper grammar (i.e. replace the phrase “and to connecting” with --and connecting--); in claim 14, line 9, remove the second semicolon from the end of the line for proper punctuation . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-6 and 8-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Patent Application Publication 2020/0153110) in view of Yu et al (US Patent Application Publication 2013/0037950) . Regarding claim 1, Kim et al disclose a semiconductor package comprising: a support substrate 355h having a through hole extending from a first side of the support substrate to a second side of the support substrate opposite to the first side of the support substrate [see Fig. 8A; see also paragraph 0104] and comprising: an insulating layer 280h ; one or more wiring layers 310h comprising a first wiring layer; and a first electronic device on the first wiring layer [see Fig. 1; see also paragraph 0110]; a semiconductor chip 301c positioned in the through hole to be at least partially surrounded by the support substrate and comprising a connection pad 340a on a first surface of the semiconductor chip; an encapsulant 305a filling at least a portion of the through hole and encapsulating at least a portion of the semiconductor chip [see Fig. 1]; a second redistribution layer 200 over a second surface of the semiconductor chip that is opposite to the first surface of the semiconductor chip, the second redistribution layer structure comprising a second redistribution layer, wherein the first wiring layer is between the first electronic device and the second redistribution layer structure, and wherein the insulating layer integrally covers the first wiring layer, a side surface of the first electronic device, and a surface of the first electronic device opposite to a surface of the first electronic device facing the first wiring layer. Kim et al do not disclose a first redistribution layer structure on the first surface of the semiconductor chip and comprising a first redistribution layer. One such as Yu et al disclose a substantially similar semiconductor package comprising a first redistribution layer structure 114 on the first surface of a semiconductor chip and comprising a first redistribution layer; and a second redistribution layer structure 126 over a second surface of the semiconductor chip that is opposite to the first surface of the semiconductor chip, the second redistribution layer structure comprising a second redistribution layer [see Fig. 1; see also paragraph 0018]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the first redistribution layer of Yu et al in the semiconductor package of Kim et al in order to provide external electrical connection between the semiconductor chip and an external device. Regarding claim 2, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, Kim et al disclose wherein the first electronic device is electrically connected to the second redistribution layer structure [see Fig. 1]. Regarding claim 3, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, Kim et al disclose wherein the first electronic device comprises a pad facing the first wiring layer [see Fig. 1]. Regarding claim 4, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 3. Furthermore, Kim et al disclose wherein the support substrate further comprises a conductive bump 250a between the first electronic device and the first wiring layer, and connecting the first electronic device and the first wiring layer through the pad [see Fig. 1]. Regarding claim 5, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, Kim et al disclose wherein the one or more wiring layers further comprises a second wiring layer, and wherein the first wiring layer is the wiring layer closest to the second redistribution structure among the wiring layers [see Fig. 1]. Regarding claim 6, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, Kim et al disclose wherein the one or more wiring layers further comprises a second wiring layer on the insulating layer, and wherein the support substrate further comprises a via 230a penetrating the insulating layer and connecting the first wiring layer and the second wiring layer [see Fig. 1]. Regarding claim 8, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, Kim et al disclose comprising a via penetrating the encapsulant and connecting the second redistribution layer to one of the one or more wiring layers [see Fig. 2]. Regarding claim 9, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, Kim et al disclose wherein the first electronic device is a capacitor [see paragraph 0059]. Regarding claim 10, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, Kim et al disclose wherein one surface of the support substrate, one surface of the semiconductor chip, and one surface of the encapsulant are substantially coplanar [see Fig. 1]. Regarding claim 11, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, Kim et al disclose wherein the first wiring layer is exposed at one surface of the insulating layer [see Fig. 1]. Regarding claim 12, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore, the combination of Kim et al and Yu et al would disclose comprising a second electronic device on a first surface of the first redistribution layer structure opposite to a second surface of the first redistribution layer structure facing the semiconductor chip. Regarding claim 13, the prior art of Kim et al and Yu et al disclose the semiconductor device of claim 1. Furthermore to the first redistribution layer, Yu et al disclose comprising a connection structure on a first surface of the first redistribution layer structure opposite to a second surface of the first redistribution layer structure facing the semiconductor chip [see Fig. 1]. Regarding claim 14, Kim et al disclose a semiconductor package comprising: a first semiconductor package; and a second semiconductor package on the first semiconductor package, wherein the first semiconductor package comprises: a support substrate 355h comprising: one or more wiring layers 310h comprising a first wiring layer; a first electronic device on the first wiring layer [see Fig. 1; see also paragraph 0110]; an insulating layer 280h at least partially covering the first wiring layer and the first electronic device; a first semiconductor chip 301c ; an encapsulant 305a encapsulating at least a portion of the first semiconductor chip [see Fig. 1]; a second redistribution layer 200 comprising a second redistribution layer over a second surface of the first semiconductor chip, the first redistribution layer being connected to the one or more wiring layers, and wherein the second semiconductor package comprises a second semiconductor chip electrically connected to the first electronic device [see Fig. 2]. Kim et al do not disclose a first redistribution layer structure on the first surface of the semiconductor chip and comprising a first redistribution layer. One such as Yu et al disclose a substantially similar semiconductor package comprising a first redistribution layer structure 114 on the first surface of a semiconductor chip and comprising a first redistribution layer; and a second redistribution layer structure 126 over a second surface of the semiconductor chip that is opposite to the first surface of the semiconductor chip, the second redistribution layer structure comprising a second redistribution layer [see Fig. 1; see also paragraph 0018]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the first redistribution layer of Yu et al in the semiconductor package of Kim et al in order to provide external electrical connection between the semiconductor chip and an external device. Regarding claim 15, the prior art of Kim et al and Yu et al disclose the semiconductor package of claim 14. Furthermore, Kim et al disclose wherein the second semiconductor package is on the second redistribution layer structure, and wherein the first wiring layer is between the first electronic device and the second redistribution layer structure [see Fig. 1]. Regarding claim 16, the prior art of Kim et al and Yu et al disclose the semiconductor package of claim 14. Furthermore, Kim et al disclose wherein the one or more wiring layers further comprises a second wiring layer, and wherein the first wiring layer is the wiring layer closest to the second redistribution structure among the wiring layers [see Fig. 1]. Regarding claim 17, the prior art of Kim et al and Yu et al disclose the semiconductor package of claim 14. Furthermore, Kim et al disclose comprising a second electronic device on a first surface of the first redistribution layer structure opposite to a second surface of the first redistribution layer structure facing the first semiconductor chip, wherein the second electronic device is connected to the first semiconductor chip [see paragraph 0110]. Regarding claim 18, Kim et al disclose a method of manufacturing a semiconductor package comprising: preparing a support substrate 355h ; forming a through hole in the support substrate [see Fig. 8A; see also paragraph 0104]; providing a semiconductor chip 301c in the through hole; encapsulating the semiconductor chip [see Figs. 1 and 2; see also paragraph 0063]; forming a second redistribution layer 200 over a second surface of the semiconductor chip opposite to the first surface of the semiconductor chip, the second redistribution layer structure comprising a second redistribution layer, wherein the preparing the support substrate comprises: forming a wiring layer 310h ; providing an electronic device on the wiring layer [see Fig. 1; see also paragraph 0110]; and forming an insulating layer 280h to at least partially cover the wiring layer and the electronic device. Kim et al do not disclose forming a first redistribution layer structure on a first surface of the semiconductor chip, the first redistribution layer structure comprising a first redistribution layer. One such as Yu et al disclose a substantially similar semiconductor package comprising a first redistribution layer structure 114 on the first surface of a semiconductor chip and comprising a first redistribution layer; and a second redistribution layer structure 126 over a second surface of the semiconductor chip that is opposite to the first surface of the semiconductor chip, the second redistribution layer structure comprising a second redistribution layer [see Fig. 1; see also paragraph 0018]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the first redistribution layer of Yu et al in the semiconductor package of Kim et al in order to provide external electrical connection between the semiconductor chip and an external device . 07-22-aia AIA Claim s 7, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Patent Application Publication 2020/0153110) in view of Yu et al (US Patent Application Publication 2013/0037950) as applied to claim 18 above, and further in view of Lee et al (US Patent Application Publication 2021/0193555) . Regarding claim 7, the prior art of Kim et al and Yu et al disclose the semiconductor package of claim 6. Neither Kim et al nor Yu et al disclose wherein the via has a tapered shape with a width that narrows in a direction from the second wiring layer to the first wiring layer. One such as Lee et al disclose a substantially similar package structure, comprising a via penetrating an insulating layer and connecting a first wiring layer and a second wiring layer, furthermore wherein the via has a tapered shape with a width that narrows in a direction from the second wiring layer to the first wiring layer [see Fig. 5]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the via to have a tapered shape because one of ordinary skill would recognize that a tapered shape is a known artifact of many etching procedures. Regarding claims 19 and 20, the prior art of Kim et al and Yu et al disclose the method of claim 18. Neither Kim et al nor Yu et al disclose wherein the support substrate is prepared on a first carrier film. One such as Lee et al disclose a substantially similar package structure and method of forming thereof, wherein a support substrate on a first carrier film 210 , wherein the method further comprises: positioning the support substrate on a second carrier film 220 ; removing the first carrier film [see Figs. 7A and 7B; see also paragraph 0088]; and removing the second carrier film [see Fig. 7C; see also paragraph 0091], wherein the providing of the semiconductor chip in the through hole is performed on the second barrier film, and wherein the semiconductor chip is provided directly on the second carrier film. It would have been obvious to one of ordinary skill in the art at the time of invention to include the first and second carrier films of Lee et al in the method of Kim et al , as modified by Yu et al , in order to allow for processing from the front- and back-ends of the substrate. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN E SNOW whose telephone number is (571)272-8603. The examiner can normally be reached M-W, 8am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.E.S./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/592,004 Page 2 Art Unit: 2899 Application/Control Number: 18/592,004 Page 3 Art Unit: 2899 Application/Control Number: 18/592,004 Page 4 Art Unit: 2899 Application/Control Number: 18/592,004 Page 5 Art Unit: 2899 Application/Control Number: 18/592,004 Page 6 Art Unit: 2899 Application/Control Number: 18/592,004 Page 7 Art Unit: 2899 Application/Control Number: 18/592,004 Page 8 Art Unit: 2899 Application/Control Number: 18/592,004 Page 9 Art Unit: 2899 Application/Control Number: 18/592,004 Page 10 Art Unit: 2899
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