DETAILED ACTION
This office action is in response to the election filed 7/17/2026.
Claims 1-6 and 8-9 are pending, of which claim 8 is withdrawn from consideration. Claim 7 has been canceled.
Election/Restrictions
Applicant’s election without traverse of Species I is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “a blocking insulating layer and a charge trap layer sequentially interposed between sidewalls of the even conductive layer and the odd conductive layer”. It is not clear what is meant by “interposed” in light of the specification, and appears to contradict the plain meaning of the term. As seen in FIG. 3, the only layer that is between the even conductive layer CDLe and the odd conductive layer CDLo is interlayer insulating layer ISL2, which is interposed between the top surface of the even conductive layer and the bottom surface of the odd conductive layer. Although there are blocking insulators and charge trap layers that are adjacent each sidewall of the even and odd conductive layers, this location does not match the description of “between sidewalls of the even conductive layer and the odd conductive layer”. A similar limitation is repeated explicitly in claims 4, 6 and 9, and is recited in the other claims via dependency on an independent claim reciting the limitation. The disclosure teaches that the blocking insulating layer, charge trap layer, and tunnel insulating are located between the conductive layer and the channel layer, and thus, for purposes of examination, the limitation is interpreted as such.
Furthermore, claim 2 recites the limitation “a sidewall of the first interlayer insulating layers and the second interlayer insulating layer contacting the channel layer”. It is not clear what is meant by “contacting” in light of the specification, and appears to contradict the plain meaning of the term. As seen in FIG. 3, tunnel insulating layer TIL is located between the sidewalls of the first interlayer insulating layers and the second interlayer insulating layer and the channel layer CHL, and therefore prevents contact between the sidewalls of the first interlayer insulating layers and the second interlayer insulating layer and the channel layer.
Claim 3 recites the limitation “the first interlayer insulating layers and the second interlayer insulating layer further protrude in a direction of the channel layer than the even conductive layer and the odd conductive layer. It is not clear what is meant by “direction of the channel layer” in light of the specification. As seen in FIG. 3, the direction in which the channel layer CHL extends is near vertical. However, FIG. 3 shows the first interlayer insulating layers and the second interlayer insulating layer being stacked in the same direction in which the channel extends. It is then not clear how it could be said that one element protrudes further in that direction than the other. For purposes of examination, the limitation is interpreted as a direction towards the channel, which is consistent with the disclosure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 11,227,870).
Pertaining to claim 1, Kang shows, with reference to FIG. 2, a semiconductor device comprising:
a gate stack including first interlayer insulating layers (e.g. 162, 166) and word line stack layers (e.g. insulating layer 164 and conductive layers WL above and below 164), which are alternately stacked;
a channel layer (106) extending in a vertical direction in the gate stack; and
memory structures (110a, 110b) interposed between the word line stack layers and the channel layer,
wherein each of the word line stack layers includes an even conductive layer (below 164), a second interlayer insulating layer (164), and an odd conductive layer (above 164) sequentially stacked, and
wherein the thickness of each of the first interlayer insulating layers (162, 164) is greater than the thickness of any one of the second interlayer insulating layers (164) included in any one of the word line stack layers (FIG. 2).
Pertaining to claim 6, Kang shows a semiconductor device comprising:
a gate stack including first interlayer insulating layers (e.g. 162, 166) and word line stack layers (e.g. insulating layer 164 and conductive layers WL above and below 164), which are alternately stacked;
a channel layer (106) extending in a vertical direction in the gate stack; and
memory structures (102/110/104) interposed between the word line stack layers and the channel layer,
wherein each of the word line stack layers includes an even conductive layer (below 164), a second interlayer insulating layer (164), and an odd conductive layer (above 164) sequentially stacked,
wherein each of the memory structures includes a blocking insulating layer (102), a charge trap layer (110a/b), and a tunnel insulating layer (106) sequentially interposed between sidewalls of the even conductive layer and the odd conductive layer, and
wherein the thickness of any one of the first interlayer insulating layers is greater than the thickness of any one of the second interlayer insulating layers (FIG. 2).
Pertaining to claim 2, Kang shows each of the memory structures includes a blocking insulating layer (102) and a charge trap layer (110a/b) sequentially interposed between sidewalls of the even conductive layer and the odd conductive layer, and wherein a sidewall of the first interlayer insulating layers and the second interlayer insulating layer contacting the channel layer is positioned on the same line as a sidewall of the charge trap layer contacting the channel layer (a meandering line may be drawn that traces the sidewalls).
Pertaining to claim 3, Kang shows the first interlayer insulating layers and the second interlayer insulating layer further protrude in a direction of the channel layer than the even conductive layer and the odd conductive layer, and wherein the blocking insulating layer and the charge trap layer are interposed in a space between the protruded first interlayer insulating layers and the second interlayer insulating layer (FIG. 2).
Pertaining to claims 4 and 9, Kang shows the charge trap layers are spaced apart from each other by the first interlayer insulating layers and the second interlayer insulating layer (FIG. 2).
Pertaining to claim 5, Kang shows a tunnel insulating layer (106) extending in the vertical direction along a sidewall of the first interlayer insulating layers, a sidewall of the second interlayer insulating layer, and a sidewall of the charge trap layer, wherein the channel layer extends in the vertical direction along a sidewall of the tunnel insulating layer (FIG. 2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Son et al. (US 2023/0109996), Kang et al. (US 2022/0189988), Yang et al. (US 2012/0156848), Sotome (US 2022/0302163), and Hopkins (US 9,793,124) all disclose inventions similar to Applicant’s.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
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