Prosecution Insights
Last updated: October 02, 2026
Application No. 18/592,284

CHIP PACKAGE ASSEMBLY WITH ON-PACKAGE CONTAINMENT SYSTEM

Non-Final OA §102§103§112
Filed
Feb 29, 2024
Examiner
CIESLEWICZ, ANETA B
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices Inc.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
67%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
163 granted / 243 resolved
-0.9% vs TC avg
Minimal -0% lift
Without
With
+-0.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
17 currently pending
Career history
277
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
48.7%
+8.7% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
24.0%
-16.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 243 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Invention I, Species 3 in the reply filed on July 21, 2026 is acknowledged. The traversal is on the ground(s) that there would be no undue burden on the Examiner to examine both inventions as some of the elements are shared between the two inventions. This is not found persuasive because, even though some of the elements might be shared between the two inventions, the process as claimed can be used to make another and materially different product and the product as claimed can be made by another and materially different process, as outlined in the Election/Restriction requirement. With respect to claims 2 and 10, the claims appear to be covering the elected Species 3 and thus will be examined with the elected Invention I, Species 3. The requirement is still deemed proper and is therefore made FINAL. Claim(s) 16-20 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Accordingly, claims 1-15 are ready for examination. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 2 and 6-15 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to claim 2, as currently presented the claim requires that an integrated circuit (IC) die has as first height and a stiffener is at a second height “that is greater than the first height”. The first height appears to be referring to a vertical dimension of the IC die, and the second height appears to be referring to a vertical position of an opening. It is not clear, however, what is considered the second height (e.g. width of the opening, position of the lower boundary of the opening, a part of the opening, or something else), and how a vertical dimension compares to a vertical position. For the purpose of the examination, it will be assumed that the IC has a top surface positioned at a first height, as measured from the top surface of the package substrate, and a part of the opening is positioned at a second height, as measured from a top surface of the package substrate, wherein the second height is greater than the first height. With respect to claim 6, as currently presented the claim requires TIM “extending preferentially into the cavity”. The scope of the phrase “extending preferentially” is unclear. For example, under one interpretation the term “preferentially” can mean that the TIM enters the cavity more readily, as the cavity provides a lower-flow resistance path for the TIM than the tortuous gap, or under a different interpretation, the term preferentially can mean that during dispensing of TIM a greater volume of TIM enters the cavity than enters the tortuous gap. For the purpose of the examination, it will be assumed that greater volume of TIM is present in the cavity in the stiffener than the tortuous gap. With respect to claim 7, as currently presented the claim requires that “a distance across the opening is larger than a distance across the tortuous gap”. The scope of the term “distance” is unclear. Specifically, it is not clear if the claimed distance is describing a dimension, such as width or height, or some other distance across the opening or the tortuous gap. For purpose of the examination, it will be assumed that the term “a distance” is related to the dimension (i.e. width or height) of the opening or tortuous gap. With respect to claim 8, as currently presented the claim requires that “the cavity extends away from the top of the stiffener”. The scope of the phrase “extends away” is unclear. In particular, it is not clear in which direction the cavity is extending. Specifically, it is not clear if the cavity is extending downwards from the top of the stiffener toward the package substrate or from the opening into the stiffener that is away from the top of the stiffener. For purpose of compact prosecution, it will be assumed that the cavity extends downwards from the top of the stiffener toward the package substrate. With respect to claim 9, as currently presented, the claim requires that “cavity having an opening formed through the stiffener facing the IC die”. It is unclear, however, if it is the opening that is facing the IC die or the surface of the stiffener having the opening that is facing the IC die. For purpose of compact prosecution, it will be assumed that it is the surface of the stiffener having the opening that is facing the IC die. Claims 10-15 which either directly or indirectly depend from claim 9 and which inherit issues of claim 9, are rejected for similar reasons. With respect to claim 10, as currently presented the claim requires that an integrated circuit (IC) die has as first height and a stiffener is at a second height “that is greater than the first height”. The first height appears to be referring to a vertical dimension of the IC die, and the second height appears to be referring to a vertical position of an opening. It is not clear, however, what is considered the second height (e.g. width of the opening, position of the lower boundary of the opening, or something else) and how a vertical dimension compares to a vertical position. For the purpose of the examination, it will be assumed that the IC has a top surface positioned at a first height, as measured from the top surface of the package substrate, and the opening has a lower boundary positioned at a second height, as measured from a top surface of the package substrate, wherein the second height is greater than the first height. With respect to claim 13, as currently presented the claim requires TIM “extending preferentially into the cavity”. The scope of the phrase “extending preferentially” is unclear. For example, under one interpretation the term “preferentially” can mean that the TIM enters the cavity more readily, as the cavity provides a lower-flow resistance path for the TIM than the tortuous gap, or under a different interpretation, the term preferentially can mean that during dispensing of TIM a greater volume of TIM enters the cavity than enters the tortuous gap. For the purpose of the examination, it will be assumed that greater volume of TIM is present in the cavity in the stiffener than the tortuous gap. With respect to claim 14, as currently presented the claim requires that “the cavity extends away from the top of the stiffener”. The scope of the phrase “extends away” is unclear. In particular, it is not clear in which direction the cavity is extending. Specifically, it is not clear if the cavity is extending downwards from the top of the stiffener toward the package substrate or from the opening into the stiffener that is away from the top of the stiffener. For purpose of compact prosecution, it will be assumed that the cavity extends downwards from the top of the stiffener toward the package substrate. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 3-4 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kao et al. (EP 3693991, hereinafter “Kao”). Regarding claim 1, Kao teaches in Figs. 1A-1C (shown below) and related text a chip package comprising: a package substrate (120, Figs. 1A, 1C and ¶[0017]) having a top surface (Figs. 1A and 1C); an integrated circuit (IC) die (110, Figs. 1A, 1C and ¶[0017]) having a first height mounted on the top surface of the package substrate (Figs. 1A and 1C); a stiffener (128, Figs. 1A, 1C and ¶[0018]) mounted to the top surface of the package substrate (Figs. 1A and 1C), the stiffener having a first side facing the IC die and a top (Figs. 1A and 1C); and a cavity (112, Fig. 1A and ¶[0019]) disposed in the stiffener, the cavity having an opening (i.e. opening between the top of the stiffener and package substrate facing 110, Figs. 1A and 1C) formed through the first side of the stiffener. PNG media_image1.png 578 900 media_image1.png Greyscale Regarding claim 3 (1), Kao teaches wherein the stiffener (128, Figs. 1A-1C) is positioned at an outer border of the package substrate (Figs. 1A-1C). Regarding claim 4 (1), Kao teaches wherein a heat sink (130, Figs. 1A, 1C and ¶[0018] is disposed over the IC die (110, Figs. 1A and 1C). Regarding claim 8 (1), Kao teaches wherein the cavity (112, Figs. 1A and 1C) extends away from the top of the stiffener (Figs. 1A and 1C). Claim(s) 1-5, 7-12 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Graf et al. (US 2024/0250068, hereinafter “Graf”). Regarding claim 1, Graf teaches in Fig. 2 (shown below) and related text a chip package comprising: a package substrate (101, Fig. 2 and ¶[0048]) having a top surface (Fig. 2); an integrated circuit (IC) die (103, Fig. 2 and ¶[0048]) having a first height mounted on the top surface of the package substrate (Fig. 2); a stiffener (108, Fig. 2 and ¶[0051]) mounted to the top surface of the package substrate (Fig. 2), the stiffener having a first side facing the IC die and a top (Fig. 2); and a cavity (i.e. cavity in which 102 is disposed, Fig. 2) disposed in the stiffener, the cavity having an opening (i.e. opening between the top of the stiffener and package substrate facing 103, Fig. 2) formed through the first side of the stiffener. PNG media_image2.png 489 538 media_image2.png Greyscale Regarding claim 2 (1), Graf teaches wherein the opening in the stiffener is on the first side of the stiffener and at a second height that is greater than the first height of the IC die (Fig. 2). Regarding claim 3 (1), Graf teaches wherein the stiffener (108, Fig. 2) is positioned at an outer border of the package substrate (101, Fig. 2). Regarding claim 4 (1), Graf teaches wherein a heat sink (201, Fig. 2 and ¶[0058] is disposed over the IC die (103, Fig. 2). Regarding claim 5 (4), Graf teaches wherein a space between the heat sink and the stiffener forms a tortuous gap (i.e. a narrow gap between the stiffener 108 and heat sink 201, Fig. 2, where according to paragraph [0036] of the specification as published, a tortuous gap is considered a gap that discourages flow, which would be met by the narrow gap disclosed by Graf) . Regarding claim 7 (5), Graf teaches wherein a distance across the opening (i.e. opening extending between top of stiffener 108 and package substrate 101, Fig. 2) is larger than a distance across the tortuous gap (i.e. distance across the gap between top surface of stiffener 108 and the heat sink 201, Fig. 2). Regarding claim 8 (1), Graf teaches wherein the cavity (Fig. 2) extends away from the top of the stiffener (108, Fig. 2). Regarding claim 9, Graf teaches in Fig. 2 (shown above) and related text an electronic device, comprising: a package substrate (101, Fig. 2 and ¶[0048]) having a top surface (Fig. 2); an integrated circuit (IC) die (103, Fig. 2 and ¶[0048]) having a first height mounted on the top surface of the package substrate (Fig. 2); a stiffener (108, Fig. 2 and ¶[0051]) mounted to the top surface of the package substrate (101, Fig. 2), the stiffener having a first side and a top (Fig. 2); a first electronic component (102, Fig. 2 and ¶[0050]) mounted to a first region of the package substrate defined between the stiffener and the IC die (Fig. 2); a cavity (i.e. cavity in which 102 is disposed and similar cavity on the other side of 103, Fig. 2) formed in the stiffener, the cavity having an opening formed through the stiffener facing the IC die (i.e. opening between the top of the stiffener and package substrate facing 103, Fig. 2); a heat sink (201, Fig. 2 and ¶[0058]) mounted on the IC die (103, Fig. 2); and a thermal interface material (TIM) (202, Fig. 2 and ¶[0058]) disposed between the IC die (202, Fig. 2) and the heat sink (201, Fig. 2). Regarding claim 10 (9), Graf teaches wherein the opening in the stiffener (108, Fig. 2) is on the first side of the stiffener and at a second height that is greater than the first height of the IC die (103, Fig. 2). Regarding claim 11 (9), Graf teaches wherein the stiffener is positioned at an outer border of the package substrate (101, Fig. 2). Regarding claim 12 (9), Graf teaches wherein a tortuous gap (i.e. a narrow gap between the stiffener 108 and heat sink 201, Fig. 2, where according to paragraph [0036] of the specification as published, a tortuous gap is considered a gap that discourages flow, which would be met by the narrow gap disclosed by Graf) is defined between the heat sink and the stiffener (Fig. 2). Regarding claim 15 (9), Graf teaches wherein the cavity extends away from the top of the stiffener (Fig. 2). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Graf as applied to claim 9 above, and further in view of Lan et al. (US 2025/0105086, hereinafter “Lan”). Regarding claim 14 (9), teaching of Graf was discussed above in the rejection of claim 9 and includes a teaching of TIM (202, Fig. 2 and ¶[0058]) disposed between the IC die (202, Fig. 2) and the heat sink (201, Fig. 2). Graf, however, does not explicitly teach that the TIM extends into the cavity of the stiffener. Lan, in a similar field of endeavor, teaches in Fig. 9 and related text that TIM between an IC die (70, Fig. 9 and ¶[0051]) and a heat sink (134, Fig. 9 and ¶¶[0050]-[0053]) can extend into the cavity of the stiffener (122, Fig. 9 and ¶[0047]) in order to provide greater thermal conductivity and adhesion between elements. Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to extend the TIM disclosed by Graf into the cavity of the stiffener, as disclosed by Lan, in order to provide greater thermal conductivity and adhesion between elements. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.B.C/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Feb 29, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
67%
With Interview (-0.2%)
3y 3m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 243 resolved cases by this examiner. Grant probability derived from career allowance rate.

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