DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 12 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein a lower surface of the metal wire is substantially coplanar with the lower surface of the insulating layer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 6 and 12 – 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yamano (US 2006/0097378 A1).
Regarding Claim 1, Yamano (US 2006/0097378 A1) discloses a printed circuit board (Fig 34) comprising: an insulating layer (51,53; [0030-0031]); a through-hole (122) penetrating between an upper surface (upper surface of 53) and a lower surface (lower surface of 51) of the insulating layer (51,53) opposing in a thickness direction; a metal wire (123; [0078]) disposed inside the through-hole (122), wherein a lower surface (lower surface of 123) of the metal wire (123) is substantially (not exactly; note that this is a relative term; note also that the Applicant’s specification has not provided any criticality for this claimed feature) coplanar (see Fig 34 showing the lower surface of 123 at 64 is shown substantially coplanar to the lower surface of lower 51) with the lower surface of the insulating layer (51,53) and an upper surface (upper surface of 123) of the metal wire (123) is disposed on a level (see Fig 34 showing an upper surface of 123 is lower than an upper surface of upper 53 and above a central thickness of 51) between a center of the insulating layer and the upper surface of the insulating layer based on the thickness direction; and a metal via (124; [0077]), which is a single layer filling the through-hole (122) and covering the metal wire (123), wherein an upper surface and a lower surface of the metal via are substantially (not exactly; note that this is a relative term; note also that the Applicant’s specification has not provided any criticality for this claimed feature) coplanar (as seen in Fig 34, upper and lower surfaces of 124 are shown substantially coplanar, to an extent though not exactly, with the upper surface of 53 and lower surface of 51) with the upper surface and the lower surface of the insulating layer.
Regarding Claim 2, Yamano further discloses the printed circuit board (Fig 34) according to claim 1, wherein the metal wire (123) includes a bonding portion (a region or area of 123 close to and affixed to 64; [0038] “bonding”; note that the structural limits or periphery of this claimed “portion”) and a wire portion (a region or area of 123 away from 164; note that the structural limits or periphery of this claimed “portion”) connected to the bonding portion.
Regarding Claim 3, Yamano further discloses the printed circuit board (Fig 34) according to claim 2, wherein a lower surface (surface of 123) of the bonding portion (a region or area of 123) is substantially coplanar with the lower surface (as seen in Fig 34, end of 123 is substantially, not exactly, coplanar with 51) of the insulating layer (51,53) and the lower surface of the metal via (124).
Regarding Claim 4, Yamano further discloses the printed circuit board (Fig 34) according to claim 2, wherein an end (upper end of 123) of the wire portion (a region or area of 123; note that the structural limits or periphery of this claimed “portion”; this portion can be centrally located and as the structural limitations of this “portion” are not structurally defined, the end of this portion can be within the middle of 123) is disposed on a level between a center of the insulating layer (51,53) and the upper surface of the insulating layer (upper surface of 53) based on the thickness direction.
Regarding Claim 5, Yamano further discloses the printed circuit board (Fig 34) according to claim 1, wherein the metal via (124) includes a first metal layer (124; [0040]) but does not include a seed metal layer ([0040]; no seed layer is formed).
Regarding Claim 6, Yamano further discloses the printed circuit board (Fig 34) according to claim 1, further comprising: first and second metal wirings (127,61) disposed on the upper surface and the lower surface of the insulating layer (51,53), respectively, and connected to each other through the metal via (124).
Regarding Claim 12, Yamano discloses a discloses a printed circuit board (Fig 34) comprising: an insulating layer (51,53) having a through-hole (122); a metal wire (123) disposed inside the through-hole; a first metal layer (124) filling the through-hole and covering the metal wire (123); a first seed metal layer (128) disposed on and substantially coplanar with an upper surface of each of the insulating layer (51,53) and the first metal layer (124), wherein a lower surface of the first seed metal layer (128) is spaced apart from an upper surface of the metal wire (123) in a thickness direction; a second seed metal layer (64) disposed on and substantially coplanar with a lower surface of each of the insulating layer (51,53), the first metal layer (124), and the metal wire (123); a second metal layer (72) disposed on an upper surface of the first seed metal layer; and a third metal layer (63) disposed on a lower surface of the second seed metal layer.
Regarding Claim 13, Yamano further discloses the printed circuit board (Fig 34) according to claim 12, wherein the metal wire (123) includes a bonding portion (a region or area of 123 close to and affixed to 64; note that the structural limits or periphery of this claimed “portion”) and a wire portion (a region or area of 123 away from 64 and centrally located in 122; note that the structural limits or periphery of this claimed “portion”) connected to the bonding portion, an upper surface of the wire portion (a region or area of 123 away from 64; note that the structural limits or periphery of this claimed “portion”; this portion can be centrally located and as the structural limitations of this “portion” are not structurally defined, the end of this portion can be within the middle of 122) is spaced apart (this portion can be an area centrally located within 113 and away from 141a) from the first seed metal layer (128), and a lower surface of the bonding portion is in contact with the second seed metal layer (64). Note that the structural aspects of the claimed “portion” are not structurally defined in the claim language and the two portions can include one another.
Regarding Claim 14, Yamano further teaches the printed circuit board (Fig 34) according to claim 12, wherein the upper surface of the first metal layer (124) is substantially coplanar with the upper surface of the insulating layer (51,53), and the lower surface of the first metal layer (124) is substantially coplanar with the lower surface of the insulating layer (51).
Regarding Claim 15, Yamano further teaches the printed circuit board (Fig 34) according to claim 14, wherein the first metal layer (124) is a single layer, and the first metal layer is in contact with a wall surface of the through-hole (122).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yamano (US 2006/0097378 A1) as applied to claim 6 above, and further in view of Aoki (US 2023/0009751 A1).
Regarding Claim 7, Yamano discloses the limitations of the preceding claim.
Yamano does not disclose printed circuit board according to claim 6, wherein the first metal wiring comprises: a first seed metal layer configured to cover the upper surface of each of the insulating layer and the metal via; and a second metal layer configured to cover an upper surface of the first seed metal layer and to be thicker than the first seed metal layer, and the second metal wiring comprises: a second seed metal layer configured to cover the lower surface of each of the insulating layer, the metal via and the metal wire; and a third metal layer configured to cover a lower surface of the second seed metal layer and to be thicker than the second seed metal layer.
Aoki (US 2023/0009751 A1) teaches of a printed circuit board (Fig 1-2), wherein a first metal wiring (140b) comprises: a first seed metal layer (141a) configured to cover an upper surface of each of the insulating layer (110) and the metal via (202); and a second metal layer (141b) configured to cover an upper surface of the first seed metal layer (141a) and to be thicker (see Fig 1-2) than the first seed metal layer (141a), and the second metal wiring (140b) comprises: a second seed metal layer (141a) configured to cover a lower surface of each of the insulating layer (110), the metal via (202) and the metal wire (201); and a third metal layer (141b) configured to cover a lower surface of the second seed metal layer (141a) and to be thicker (see Fig 1-2) than the second seed metal layer (141a).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Yamano, wherein the first metal wiring comprises: a first seed metal layer configured to cover the upper surface of each of the insulating layer and the metal via; and a second metal layer configured to cover an upper surface of the first seed metal layer and to be thicker than the first seed metal layer, and the second metal wiring comprises: a second seed metal layer configured to cover the lower surface of each of the insulating layer, the metal via and the metal wire; and a third metal layer configured to cover a lower surface of the second seed metal layer and to be thicker than the second seed metal layer as taught by Aoki, in order to better control the thickness of the layers and improve electrical characteristics (Aoki, [0008,0078-0082,0089,0092,0093,0099]).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yamano (US 2006/0097378 A1) as applied to claim 1 above, and further in view of Shueh (US 2022/0210916 A1).
Regarding Claim 8, Yamano further discloses the printed circuit board (Fig 34) according to claim 1, wherein the insulating layer (51,53) includes a glass substrate ([0031,0054-0055] “glass member”, “SiO2”; note that the Applicant states in Applicant’s Specification p. 14, [0031] “glass substrate may include glass that is an amorphous solid. Glass may include, for example, pure silicon dioxide (about 100% SiO2), soda lime glass, borosilicate glass, and alumino-silicate glass. However, the present disclosure is not limited thereto, and alternative glass materials, such as fluorine glass, phosphoric acid glass, chalcogen glass, and the like, may also be used as materials”).
Yamano does not disclose the metal wire includes an alloy including at least one of copper (Cu), gold (Au), silver (Ag), or palladium (Pd), and the metal via includes copper (Cu).
Shueh teaches of a printed circuit board (Fig 2), wherein an insulating layer (111) includes a glass substrate ([0066] “glass”), a metal wire includes an alloy ([0070] “alloy thereof”) including at least one of copper (Cu) ([0070] “copper”), gold (Au) ([0070] “gold”), silver (Ag), or palladium (Pd), and the metal via (13; [0072] “copper”) includes copper (Cu).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Yamano, wherein the metal wire includes an alloy including at least one of copper (Cu), gold (Au), silver (Ag), or palladium (Pd), and the metal via includes copper (Cu) as taught by Shueh, in order to provide conduction (Shueh, [0066,0070,0072]) and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice such as to prevent tarnishing, provide reliability and to resist corrosion. In re Leshin, 125 USPQ 416. Please note that in the instant application, page 16, [0035], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamano (US 2006/0097378 A1) as applied to claim 1 above, and further in view of Ikeda (US 2006/0083895 A1).
Regarding Claim 9, Yamano discloses the limitations of the preceding claim.
Yamano does not disclose the printed circuit board according to claim 1, wherein the through-hole is tapered so that a width of an upper end thereof is larger than a width of a lower end thereof on a cross-section.
Ikeda (US 2006/0083895 A1) teaches of a printed circuit board (Fig 1), wherein a through-hole (aperture in 40 for 51) is tapered so that a width of an upper end thereof is larger than a width of a lower end thereof on a cross-section.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Yamano, wherein the through-hole is tapered so that a width of an upper end thereof is larger than a width of a lower end thereof on a cross-section as taught by Ikeda, as a tapered via can be more densely arranged than a straight-shaped via (Ikeda, [0007]), such that the through-hole is tapered so that a width of an upper end thereof is larger than a width of a lower end thereof on a cross-section. Furthermore it has been held obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the shape of the hole wherein the through-hole is tapered so that a width of an upper end thereof is larger than a width of a lower end thereof on a cross-section, as a tapered via can be more densely arranged than a straight-shaped via. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). Please note that in the instant application, pages 18-19, [0039-0041], Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 10, Yamano discloses the limitations of the preceding claim.
Yamano does not disclose the printed circuit board according to claim 1, wherein the through-hole is tapered so that a width of a lower end thereof is larger than a width of an upper end thereof on a cross-section.
Ikeda (US 2006/0083895 A1) teaches of a printed circuit board (Fig 1), wherein a through-hole (aperture in 26 for 53) is tapered so that a width of a lower end thereof is larger than a width of an upper end thereof on a cross-section.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Yamano, wherein the through-hole is tapered so that a width of a lower end thereof is larger than a width of an upper end thereof on a cross-section as taught by Ikeda, as a tapered via can be more densely arranged than a straight-shaped via (Ikeda, [0007]), such that the through-hole is tapered so that a width of a lower end thereof is larger than a width of an upper end thereof on a cross-section. Furthermore it has been held obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the shape of the hole wherein the through-hole is tapered so that a width of a lower end thereof is larger than a width of an upper end thereof on a cross-section, as a tapered via can be more densely arranged than a straight-shaped via. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). Please note that in the instant application, pages 18-19, [0039-0041], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yamano (US 2006/0097378 A1) as applied to claim 1 above, and further in view of Hibino (US 10,420,214 B2).
Regarding Claim 11, Yamano discloses the limitations of the preceding claim.
Yamano does not disclose the printed circuit board according to claim 1, wherein the through-hole is tapered to both sides so that a width of each of an upper end and a lower end thereof is larger than a width of a certain interior between the upper end and the lower end thereof on a cross-section.
Hibino (US 10,420,214 B2) teaches of a printed circuit board (Fig 2), wherein a through-hole (24) is tapered to both sides so that a width of each of an upper end (at 24F) and a lower end (24S) thereof is larger than a width of a certain interior (central portion of 24) between the upper end and the lower end thereof on a cross-section.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Yamano, wherein the through-hole is tapered to both sides so that a width of each of an upper end and a lower end thereof is larger than a width of a certain interior between the upper end and the lower end thereof on a cross-section as taught by Hibino, in order to allow for laser processing of the substrate from both surfaces, reduce voids and increase reliability (Hibino, Column 2, lines 52-68, Column 3, line 1-Column 4, line 45, Column 6, lines 3-33). Furthermore it has been held obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the shape of the hole wherein the through-hole is tapered to both sides so that a width of each of an upper end and a lower end thereof is larger than a width of a certain interior between the upper end and the lower end thereof on a cross-section, in order to allow for laser processing of the substrate from both surfaces, reduce voids and increase reliability. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). Please note that in the instant application, pages 18-19, [0039-0041], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yamano (US 2006/0097378 A1) as applied to claim 12 above, and further in view of Eldridge (US 2002/0117330 A1).
Regarding Claim 16, Yamano further discloses the printed circuit board (Fig 34) according to claim 12, wherein the insulating layer (51,53) includes a glass substrate ([0031,0054-0055] “glass member”, “SiO2”; note that the Applicant states in Applicant’s Specification p. 14, [0031] “glass substrate may include glass that is an amorphous solid. Glass may include, for example, pure silicon dioxide (about 100% SiO2), soda lime glass, borosilicate glass, and alumino-silicate glass. However, the present disclosure is not limited thereto, and alternative glass materials, such as fluorine glass, phosphoric acid glass, chalcogen glass, and the like, may also be used as materials”).
Yamano does not explicitly disclose each of the first and second seed metal layers includes copper (Cu), and each of the first to third metal layers includes copper (Cu), the metal wire includes a palladium (Pd)-copper (Cu) alloy.
Eldridge (US 2002/0117330 A1) teaches of a metal wire ([0307-0324]; Claims 106,173-181) includes a palladium (Pd)-copper (Cu) alloy ([0324]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Yamano, wherein the metal wire includes a palladium (Pd)-copper (Cu) alloy as taught by Eldridge, in order to prevent tarnishing, provide reliability and resist corrosion (Eldridge, [0561,0562] Claims 106,173-181) and it would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Yamano in view of Eldridge wherein each of the first and second seed metal layers includes copper (Cu), and each of the first to third metal layers includes copper (Cu), in order to provide a commonly found conductive material such as copper, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice such as to prevent tarnishing, provide reliability and to resist corrosion. In re Leshin, 125 USPQ 416. Please note that in the instant application, page 16, [0035], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yamano (US 2006/0097378 A1) in view of Ikeda (US 2006/0083895 A1).
Regarding Claim 17, Yamano discloses a printed circuit board (Fig 34) comprising: an insulating layer (51,53; [0030-0031]); a through-hole (122) penetrating between an upper surface (upper surface of 53) and a lower surface (lower surface of 51) of the insulating layer opposing in a thickness direction, the through-hole (122); a first metal portion (annotated FIRST METAL PORTION with 125 having a trapezoidal shape; note that the structural limits or periphery of this claimed “portion”) disposed inside the through-hole (122), the first metal portion (portion of 125) comprising a bonding portion (annotated BONDING PORTION OF FIRST METAL PORTION; a region or area of 123 close to and affixed to 64; [0038] “bonding”; note that the structural limits or periphery of this claimed “portion”) and a wire portion (annotated WIRE PORTION OF FIRST METAL PORTION; a region or area of 123 away from 64; note that the structural limits or periphery of this claimed “portion”), the bonding portion having a first width (width of annotated 125 at lower end of 123) in a width direction perpendicular to the thickness direction, and the wire portion having a second width (width of 125 at upper end of 123) in the width direction that is greater than the first width; and a second metal portion (portion of 124 surrounding the FIRST METAL PORTION) filling the through-hole (122) and covering both the first metal portion and an entirety of a wall surface of the through-hole (122), wherein a thickness of the first metal portion in the thickness direction is larger than the first width and the second width.
Yamano does not disclose having a tapered shape so that a width of a portion thereof is larger than a width of another portion thereof on a cross-section.
Ikeda (US 2006/0083895 A1) teaches of a printed circuit board (Fig 1), wherein a through-hole (aperture in 40 for 51) is tapered so that a width of an upper end thereof is larger than a width of a lower end thereof on a cross-section.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Yamano, having a tapered shape so that a width of a portion thereof is larger than a width of another portion thereof on a cross-section as taught by Ikeda, as a tapered via can be more densely arranged than a straight-shaped via (Ikeda, [0007]), such that the through-hole is tapered so that a width of an upper end thereof is larger than a width of a lower end thereof on a cross-section. Furthermore it has been held obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the shape of the hole wherein the through-hole is tapered so that a width of an upper end thereof is larger than a width of a lower end thereof on a cross-section, as a tapered via can be more densely arranged than a straight-shaped via. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). Please note that in the instant application, pages 18-19, [0039-0041], Applicant has not disclosed any criticality for the claimed limitations.
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Annotated Fig 34 from Yamano (US 2006/0097378 A1)
Regarding Claim 18, Yamano further discloses the printed circuit board (Fig 34) according to claim 17, further comprising: first and second metal wirings (61,127) disposed on the upper surface and the lower surface of the insulating layer (51,53), respectively, and connected to each other through the second metal portion (124).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yamano (US 2006/0097378 A1) in view of Ikeda (US 2006/0083895 A1) as applied to claim 18 above, and further in view of Aoki (US 2023/0009751 A1).
Regarding Claim 19, Yamano in view of Ikeda teaches the limitations of the preceding claim.
Yamano does not disclose printed circuit board according to claim 18, wherein the first metal wiring comprises: a first seed metal layer covering each of the upper surface of the insulating layer and an upper surface of the second metal portion; and a second metal layer covering an upper surface of the first seed metal layer, the second metal layer being thicker than the first seed metal layer, and the second metal wiring comprises: a second seed metal layer covering each of the lower surface of the insulating layer and a lower surface of the second metal portion; and a third metal layer covering a lower surface of the second seed metal layer, the third metal layer being thicker than the second seed metal layer.
Aoki (US 2023/0009751 A1) teaches of a printed circuit board (Fig 1-2), wherein a first metal wiring (140b) comprises: a first seed metal layer (141a) configured to cover an upper surface of each of the insulating layer (110) and the metal via (202); and a second metal layer (141b) configured to cover an upper surface of the first seed metal layer (141a) and to be thicker (see Fig 1-2) than the first seed metal layer (141a), and the second metal wiring (140b) comprises: a second seed metal layer (141a) configured to cover a lower surface of each of the insulating layer (110), the metal via (202) and the metal wire (201); and a third metal layer (141b) configured to cover a lower surface of the second seed metal layer (141a) and to be thicker (see Fig 1-2) than the second seed metal layer (141a).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught by Yamano in view of Ikeda, wherein the first metal wiring comprises: a first seed metal layer covering each of the upper surface of the insulating layer and an upper surface of the second metal portion; and a second metal layer covering an upper surface of the first seed metal layer, the second metal layer being thicker than the first seed metal layer, and the second metal wiring comprises: a second seed metal layer covering each of the lower surface of the insulating layer and a lower surface of the second metal portion; and a third metal layer covering a lower surface of the second seed metal layer, the third metal layer being thicker than the second seed metal layer as taught by Aoki, in order to better control the thickness of the layers and improve electrical characteristics (Aoki, [0008,0078-0082,0089,0092,0093,0099]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896
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