Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 10-11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (US-20130020654-A1 referred as Yamada) in view of Hsiung et al. (US-20230352478-A1 referred as Hsiung).
Regarding claim 1. Yamada discloses a semiconductor device, comprising:
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a substrate comprising a first active region and a second active region defined by an element isolation structure ([0098], figure 4b annotated above, a substrate #10/12c comprises of a first active region #nMIS/pMIS and a second active region #Dummy-Region defined by an element isolation structure #EIS which encloses their boundaries. Please note that #12a-12c are part of the substrate #10 as described in [0078]);
a first element disposed in the first active region and comprising a gate structure disposed on the substrate and source/drain regions disposed in the first active region at opposite sides of the gate structure ([0100], figure 4b annotated above, a first element #20a/15a/23a is disposed in the first active region #nMIS/pMIS comprising of a gate structure #20a/15a and a source/drain region #23a disposed at opposite sides of the gate structure #20a/15a); and
a second element disposed in the second active region and comprising an insulation pattern embedded in the substrate, wherein the insulation pattern comprises a first portion and a second portion ([0100], figure 4b annotated above, a second element #11a/11b in the second active region #Dummy-Region and comprising an insulation pattern #11a/11b embedded in the substrate #10/12c. The insulation pattern #11a/11b comprises of a first portion #11a and a second portion #11b); and
a dummy gate structure disposed in the second active region and comprising a first pattern disposed on the first portion of the insulation pattern, a second pattern disposed on the second portion of the insulation pattern, and a third pattern disposed on the element isolation structure ([0096], figure 4b annotated above, a dummy gate structure #E2/E4/E5 is disposed in the second active region #Dummy-Region and comprising of a first pattern #E2 on the first portion of the insulation pattern #11a, a second pattern #E4 disposed on the second portion of the insulation pattern #11b, and a third pattern #E5 disposed on the element isolation structure #EIS).
Yamada lacks a second element disposed in the second active region and comprising a first doped region and second doped regions in the substrate, wherein the insulation pattern comprises a first portion and a second portion surrounding the first portion, the second portion and the element isolation structure define a region in the second active region where the first doped region is formed therein, and the second portion and the first portion define a region in the second active region where the second doped regions are formed therein.
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Hsiung discloses a second element disposed in the second active region and comprising an insulation pattern embedded in the substrate and a first doped region and second doped regions in the substrate ([0027], figure 2B annotated above, a second element #20C/2ndPor/EIS2 disposed in the second active region and comprising an insulation pattern #20C/2ndPor embedded in the substrate #10/10A/10D and a first doped region #504 and second doped region #104 embedded in the substrate #10/10A/10D), wherein the insulation pattern comprises a first portion and a second portion surrounding the first portion ([0031], figure 2B annotated above, wherein the insulation pattern #20C/2ndPor comprises a first portion #20C and a second portion #2ndPor surrounding the first portion #20C], the second portion and the element isolation structure define a region in the second active region where the first doped region is formed therein ([0031], figure 2B annotated above, the second portion #2ndPor and the element isolation structure #EIS2 define a region where the first doped region #504 is formed therein), and the second portion and the first portion define a region in the second active region where the second doped regions are formed therein ([0031], figure 2B annotated above, the second portion #2ndPor and the first portion #20C define a region where the second doped region #104 is formed therein).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Yamada to have further modification of the insulation pattern and also including additional elements in the second active region such as the first doped region and second doped region as taught by Hsiung in order to enhance device efficiency, increase substrates integrity, and to reduce manufacturing material.
Regarding claim 10. Yamada discloses a method of forming a semiconductor device, comprising:
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forming an element isolation structure defining a first active region and a second active region in a substrate ([0098], figure 1a annotated above, a substrate #10/12c comprises of a first active region #nMIS/pMIS and a second active region #Dummy-Region defined by an element isolation structure #EIS which encloses their boundaries. Please note that #12a-12c are part of the substrate #10 as described in [0078]);
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forming a first element in the first active region of the substrate, wherein the first element comprises a gate structure formed on the substrate ([0100], figure 4b annotated above, a first element #20a/15a is disposed in the first active region #nMIS/pMIS comprising of a gate structure #20a/15a formed on the substrate #10/12c);
forming a second element in the second active region of the substrate, wherein the second element comprises an insulation pattern embedded in the substrate, the insulation pattern comprises a first portion and a second portion ([0100], figure 4b annotated above, a second element #11a/11b in the second active region #Dummy-Region and comprising a insulation pattern #11a/11b embedded in the substrate #10/12c. The insulation pattern #11a/11b comprises of a first portion #11a and a second portion #11b); and
forming a dummy gate structure in the second active region of the substrate, wherein the dummy gate structure comprises a first pattern formed on the first portion of the insulation pattern, a second pattern formed on the second portion of the insulation pattern, and a third pattern formed on the element isolation structure ([0096], figure 4b annotated above, a dummy gate structure #E2/E4/E5 is disposed in the second active region #Dummy-Region and comprising of a first pattern #E2 on the first portion of the insulation pattern #11a, a second pattern #E4 disposed on the second portion of the insulation pattern #11b, and a third pattern #E5 disposed on the element isolation structure #EIS). Yamada lacks in forming a second element in the second active region of the substrate, wherein the second element comprises an insulation pattern embedded in the substrate and a first doped region and second doped regions formed in the substrate, the insulation pattern comprises a first portion and a second portion surrounding the first portion, the second portion and the element isolation structure define a region in the second active region where the first doped region is formed therein, and the second portion and the first portion define a region in the second active region where the second doped regions are formed therein.
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Hsiung discloses forming a second element in the second active region of the substrate, wherein the second element comprises an insulation pattern embedded in the substrate and a first doped region and second doped regions formed in the substrate ([0027], figure 2B annotated above, a second element #20C/2ndPor/EIS2 disposed in the second active region and comprising an insulation pattern #20C/2ndPor embedded in the substrate #10/10A/10D and a first doped region #504 and second doped region #104 embedded in the substrate #10/10A/10D), the insulation pattern comprises a first portion and a second portion surrounding the first portion ([0031], figure 2B annotated above, wherein the insulation pattern #20C/2ndPor comprises a first portion #20C and a second portion #2ndPor surrounding the first portion #20C), the second portion and the element isolation structure define a region in the second active region where the first doped region is formed therein ([0031], figure 2B annotated above, the second portion #2ndPor and the element isolation structure #EIS2 define a region where the first doped region #504 is formed therein), and the second portion and the first portion define a region in the second active region where the second doped regions are formed therein ([0031], figure 2B annotated above, the second portion #2ndPor and the first portion #20C define a region where the second doped region #104 is formed therein).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Yamada to have further modification of the insulation pattern and also including additional elements in the second active region such as the first doped region and second doped region as taught by Hsiung in order to enhance device efficiency, increase substrates integrity, and to reduce manufacturing material.
Regarding claim 2 and claim 11. Yamada as modified discloses
[claim 2] wherein the gate structure comprises a first high dielectric constant layer, a first capping layer and a first metal gate disposed on the substrate sequentially ([0094], figure 4B, the gate structure #20a/15a comprises of a first high dielectric constant layer #13a (which contains SiON which is a high dielectric as described in [0079]), a first capping layer #14a, and a first metal gate #18a disposed on the substrate #10/12a sequentially), and the dummy gate structure comprises a second high dielectric constant layer, a second capping layer and a second metal gate disposed on the substrate sequentially ([0107], figure 4b, the dummy gate structure #E2/E4/E5 comprises of a second high dielectric constant layer #13d/13f/13g, second capping layer #14d/14f/14g, and a second metal gate #18d/18f/18g on the substrate #10/12c sequentially), and the first metal gate and the second metal gate are disposed at the same level height respective to the substrate ([0094, 0107], figure 4b, the first metal gate #18a and the second metal gate #18d/18f/18g are all disposed at the same level height respective to the substrate #10).
[claim 11] wherein the gate structure comprises a first high dielectric constant layer, a first capping layer and a first metal gate formed on the substrate sequentially ([0094], figure 4B, the gate structure #20a/15a comprises of a first high dielectric constant layer #13a (which contains SiON which is a high dielectric as described in [0079]), a first capping layer #14a, and a first metal gate #18a disposed on the substrate #10/12a sequentially), and the dummy gate structure comprises a second high dielectric constant layer, a second capping layer and a second metal gate formed on the substrate sequentially ([0107], figure 4b, the dummy gate structure #E2/E4/E5 comprises of a second high dielectric constant layer #13d/13f/13g, second capping layer #14d/14f/14g, and a second metal gate #18d/18f/18g on the substrate #10/12c sequentially), and the first metal gate and the second metal gate are formed at the same level height respective to the substrate ([0094, 0107], figure 4b, the first metal gate #18a and the second metal gate #18d/18f/18g are all disposed at the same level height respective to the substrate #10).
Regarding claim 6 and 15. Yamada as modified discloses
[claim 6] a first dielectric structure disposed between the first pattern and the second pattern of the dummy gate structure above the insulation pattern ([0099], figure 4b annotated above, the first dielectric structure #22d is disposed between the first pattern #E2 and the second pattern #E4 of the dummy gate structure and vertically above of the insulation pattern insulation pattern #11a/11b); and
a second dielectric structure disposed between the second pattern and the third pattern of the dummy gate structure above the insulation pattern ([0099], figure 4b annotated above, the second dielectric structure #22f is disposed between he second pattern #E4 and the third pattern #E5 of the dummy gate structure and vertically above the insulation pattern #11a/11b),
wherein the first dielectric structure and the second dielectric structure are spaced apart from each other ([0099], figure 4b annotated above, the first dielectric structure #22d and the second dielectric structure #22f are spaced apart from each other).
[claim 15] forming a first dielectric structure between the first pattern and the second pattern of the dummy gate structure above the insulation pattern ([0099], figure 4b annotated above, the first dielectric structure #22d is formed between the first pattern #E2 and the second pattern #E4 of the dummy gate structure and vertically above of the insulation pattern insulation pattern #11a/11b); and
forming a second dielectric structure between the second pattern and the third pattern of the dummy gate structure above the insulation pattern ([0099], figure 4b annotated above, the second dielectric structure #22f is formed between he second pattern #E4 and the third pattern #E5 of the dummy gate structure and vertically above the insulation pattern #11a/11b),
wherein the first dielectric structure and the second dielectric structure are spaced apart from each other ([0099], figure 4b annotated above, the first dielectric structure #22d and the second dielectric structure #22f are spaced apart from each other).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (US-20130020654-A1 referred as Yamada) and Hsiung et al. (US-20230352478-A1 referred as Hsiung) in further view of Zhu et al. (US-20150008537-A1 referred as Zhu).
Regarding claim 3. Yamada as modified lacks wherein the first pattern comprises annular patterns, dot patterns, or strip patterns arranged in a first direction and extending in a second direction.
Zhu discloses wherein the first pattern comprises annular patterns, dot patterns, or strip patterns arranged in a first direction and extending in a second direction ([0020], fig 3, the first pattern #105 comprises of strip pattern as described and is illustrated extending in the second directio).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Yamada as modified to have wherein the first pattern comprises strip patterns arranged in a first direction and extending in a second direction as taught by Zhu in order to increase device efficiency, reduce the test cycle times, and to reduce capital costs.
Claims 4-5, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (US-20130020654-A1 referred as Yamada) and Hsiung et al. (US-20230352478-A1 referred as Hsiung) in further view of Chao (US-20200365600-A1).
Regarding claims 4, 5, 13, and 14. Yamada as modified lacks
[claim 4] wherein the second doped regions of the second element extend in the first direction and are spaced apart from each other in the second direction.
[claim 5] wherein the first doped region of the second element surrounds the insulation pattern and has a conductivity type different from the second doped regions.
[claim 13] wherein the second doped regions of the second element are formed to extend in a first direction and to be spaced apart from each other in a second direction.
[claim 14] wherein the first doped region of the second element is formed to surround the insulation pattern and has a conductivity type different from the second doped regions.
Chao discloses
[claim 4] wherein the second doped regions of the second element extend in the first direction and are spaced apart from each other in the second direction ([0035], figure 2, the second doped regions #114/112 of the second element extend in the first (vertical) direction and are spaced apart from each other in the second (horizontal) direction).
[claim 5] wherein the first doped region of the second element surrounds the insulation pattern and has a conductivity type different from the second doped regions ([0045, 0035], figure 2, the first doped region #154/152 surrounds the insulation pattern #250 and has a conductivity type different from the second doped region as described).
[claim 13] wherein the second doped regions of the second element are formed to extend in a first direction and to be spaced apart from each other in a second direction ([0035], figure 2, the second doped regions #114/112 of the second element extend in the first (vertical) direction and are spaced apart from each other in the second (horizontal) direction).
[claim 14] wherein the first doped region of the second element is formed to surround the insulation pattern and has a conductivity type different from the second doped regions ([0045, 0035], figure 2, the first doped region #154/152 surrounds the insulation pattern #250 and has a conductivity type different from the second doped region as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Yamada as modified to have further modification the first and second doped region as taught by Chao in order to increase circuit safety, extend the devices life, and to further isolate the circuitry from short circuits.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (US-20130020654-A1 referred as Yamada) and Hsiung et al. (US-20230352478-A1 referred as Hsiung) in further view of Chiang et al. (US-20230299217-A1 referred as Chiang).
Regarding claim 7 and claim 16. Yamada as modified lacks
[claim 7] wherein the first dielectric structure covers the second doped regions, and the second dielectric structure covers the first doped region.
[claim 16] wherein the first dielectric structure covers the second doped regions, and the second dielectric structure covers the first doped region.
Chiang discloses
[claim 7] wherein the first dielectric structure covers the second doped regions, and the second dielectric structure covers the first doped region ([[0028-0029], figure 2, the first dielectric structure #114a covers the second doped region #110 and the second dielectric structure covers the first doped region #112).
[claim 16] wherein the first dielectric structure covers the second doped regions, and the second dielectric structure covers the first doped region ([[0028-0029], figure 2, the first dielectric structure #114a covers the second doped region #110 and the second dielectric structure covers the first doped region #112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Yamada as modified to have further include the first and second dielectric structure to the first and second doped region as taught by Chiang in order to increase the circuit protection, reduce device failure and to extend the devices lifetime.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (US-20130020654-A1 referred as Yamada) and Hsiung et al. (US-20230352478-A1 referred as Hsiung) in further view of Yu et al. (US-20210407900-A1 referred as Yu).
Regarding claim 9 and claim 18. Yamada as modified lacks
[claim 9] wherein the dummy gate structure is electrically floating.
[claim 18] wherein the dummy gate structure is electrically floating.
Yu discloses
[claim 9] wherein the dummy gate structure is electrically floating ([0175], figure 15, the dummy gate structure #450 is electrically floating as described).
[claim 18] wherein the dummy gate structure is electrically floating ([0175], figure 15, the dummy gate structure #450 is electrically floating as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Yamada as modified to have wherein the dummy gate structure is electrically floating as taught by Yu in order to reduce noise, enhance stability, and to increase the circuits versatility.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (US-20130020654-A1 referred as Yamada) and Hsiung et al. (US-20230352478-A1 referred as Hsiung) in further view of Reznicek et al. (US-20200303388-A1 referred as Reznicek).
Regarding claim 12. Yamada as modified lacks wherein a process of forming the first metal gate and the second metal gate comprises a chemical mechanical polishing (CMP) process.
Reznicek discloses wherein a process of forming the first metal gate and the second metal gate comprises a chemical mechanical polishing (CMP) process ([0057, 0070], figure 7 and figure 13, the formation of the first metal gate #161 comprises of the CMP process as described. And the formation of the second metal gate #133 comprises of the CMP process as descibred).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Yamada as modified to have wherein a process of forming the first metal gate and the second metal gate comprises a chemical mechanical polishing (CMP) process as taught by Reznicek in order to achieve uniformity in the metal formation, improve interconnection quality, and to reduce manufacturing costs.
Allowable Subject Matter
Claims 8 and 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Chuang et al. (US-20250324723-A1) and Lin (US-20250234614-A1) for teaching the doped regions, deep wells, and gate structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272 - 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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