Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng et al. (US 2024/0014126).
Regarding claim 15, Cheng discloses a packaged integrated circuit including:
a package substrate (RDL) including:
pins (V4/60) [Fig. 4b, annotated below];
a first metal layer (RDL3) on the pins [Fig. 4b, annotated below];
a second metal layer (RDL2/RDL1) on the first metal layer [Fig. 4b, annotated below];
vias (V2/V1/V0) on the second metal layer [Fig. 4b, annotated below];
an insulation material (50) covering the pins, the first metal layer, the second metal layer, and the vias, and exposing surfaces of the pins (V4/60) and the vias (V0) [Fig. 4b, annotated below];
a semiconductor die (300/200) on the package substrate, the semiconductor die having a surface (Top surface) opposing the second metal layer [Fig. 4b, annotated below];
metal posts (Pad) coupled between the semiconductor die (300/200) and the exposed surfaces of the vias (V0) [Fig. 4b, annotated below]; and
a mold compound (glass 40) covering the semiconductor die and the metal posts, in which the surface is separated from the second metal layer by the insulation material (50) and the mold compound (40) [Fig. 4b, annotated below, and paragraph 0068].
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Regarding claim 16, Cheng discloses wherein the first metal layer (RDL3) has a first winding of a transformer (Ls), and wherein the second metal layer (RDL1) includes a second winding of the transformer (Lp) [Figs. 4a-4b].
Regarding claim 17, Cheng discloses:
wherein the transformer is a first transformer (T1) [Fig. 4a. annotated below], wherein the package substrate includes
a second transformer (T2) having a first winding (Ls) on the first metal layer and a second winding (Lp) on the second metal layer [Figs. 4a (annotated below) and Fig. 4b (annotated below)].
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Regarding claim 18, Cheng discloses wherein portions of the first and second windings (Ls/Lp) of the second transformer (T2) are within footprints of the first and second windings of the first transformer (T1) [Fig. 4a, annotated above].
Regarding claim 19, Cheng discloses:
wherein the semiconductor die (300/200) is a first semiconductor die (300), wherein the metal posts (Pad) are a first set of metal posts (Pad), wherein the vias (V0) are a first set of vias (V0) [Fig. 4b, annotated above],
wherein the package integrated circuit includes a second semiconductor die (200) on the package substrate (RDL), the second semiconductor die (200) having a surface (Top surface) opposing the second metal layer (RDL2/RDL1) [Fig. 4b, annotated above],
wherein the package substrate includes a second set of vias (V0) on the first metal layer (T3) [Fig. 4b, annotated above],
wherein the package integrated circuit includes a second set of metal posts (Pad) coupled between the second semiconductor die (200) and exposed surface of the second set of vias [Fig. 4b, annotated above].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 2022/0028593) in view of Cheng et al. (US 2024/0014126).
Regarding claim 15, Tang discloses a packaged integrated circuit including:
a package substrate (107) including:
pins (V3/131/138) [Fig. 1A];
a first metal layer (T3) on the pins [Fig. 1A];
a second metal layer (T2) on the first metal layer [Fig. 1A];
vias (V2/V1) on the second metal layer [Fig. 1A and paragraph 0019];
an insulation material (501/901/1301) covering the pins, the first metal layer, the second metal layer, and the vias, and exposing surfaces of the pins
a semiconductor die (102/106) on the package substrate, the semiconductor die having a surface (Top surface) opposing the second metal layer [Fig. 1A];
metal posts (116) coupled between the semiconductor die (116)
a mold compound (120) covering the semiconductor die and the metal posts, in which the surface is separated from the second metal layer by the insulation material (901/1301) and the mold compound (120) [Fig. 1A].
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However, Tang does not teach exposing surfaces of the vias.
Cheng teaches an insulation material (50) covering the first, second, and third metal layers (RDL3,RDL2,RDL1) and vias (V3,V1,V0), and exposing surfaces of the pins (V4/60) and the vias (V0) [Fig. 4b, rotated and annotated below].
In addition, Cheng teaches first and second dies (300/200) couple to exposed third vias (V0) [Fig. 4b, rotated and annotated below].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Tang by including exposed third vias as taught by Cheng because it helps to improve power density [paragraph 0004].
Regarding claim 19, Tang discloses:
wherein the semiconductor die (102/106) is a first semiconductor die (102), wherein the metal posts (116) are a first set of metal posts (116), wherein the vias are a first set of vias (V2/V1) [Fig. 1A],
wherein the package integrated circuit includes a second semiconductor die (106) on the package substrate (107), the second semiconductor die (106) having a surface (Top surface) opposing the second metal layer (T2) [Fig. 1A],
wherein the package substrate includes a second set of vias (V2/V1) on the first metal layer (T3) [Fig. 1A],
wherein the package integrated circuit includes a second set of metal posts (116) coupled between the second semiconductor die (106)
However, Tang does not teach exposing surfaces of the vias.
Cheng, as stated above, teaches first and second dies (300/200) couple to exposed third vias (V0) [Fig. 4b, rotated and annotated above].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Tang by including exposed third vias as taught by Cheng because it helps to improve power density [paragraph 0004].
Allowable Subject Matter
Claims 1-14 and 20-24 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bertoni et al. (US 2025/0201792) is related to the current application and teaches a packaged integrated circuit (400) in Figure 4.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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